Abstract: An integrated circuit fabrication process is disclosed herein. The process includes exposing a photoresist layer to a plasma, and transforming the top surface and the side surfaces of the photoresist layer to form a hardened surface. The process further includes etching the substrate in accordance with the transformed feature, wherein an etch stability of the feature is increased by the hardened surface. The photoresist layer is provided at a thickness less than 0.25 &mgr;m, for use in deep ultraviolet lithography, or for use in extreme ultraviolet lithography.

Abstract: A new method is provided for the improvement of breakdown performance of a layer of dielectric and the removal of a layer of copper oxide (CuO) from copper interconnects. The formed layer of dielectric, thereby including a formed layer of CuO or Cu2O is, using the invention, exposed to a H2 plasma treatment. The H2 plasma treatment reduces the dielectric constant of the exposed and surrounding layer of low-k dielectric while at the same time removing the layer of CuO.

Abstract: The present invention is a plasma etching method including: an arranging step of arranging a pair of electrodes oppositely in a chamber and making one of the electrodes support a substrate to be processed in such a manner that the substrate is arranged between the electrodes, the substrate having an organic-material film and an inorganic-material film; and an etching step of applying a high-frequency electric power to at least one of the electrodes to form a high-frequency electric field between the pair of the electrodes, supplying a process gas into the chamber to form a plasma of the process gas by means of the electric field, and selectively plasma-etching the organic-material film of the substrate with respect to the inorganic-material film by means of the plasma; wherein a frequency of the high-frequency electric power applied to the at least one of the electrodes is 50 to 150 MHz in the etching step.

Abstract: A plasma etching process is described. A substrate having a low-k material layer and a metal hard mask layer sequentially formed thereon is provided, wherein the metal hard mask layer exposes a portion of the low-k material layer. The low-k material layer is then etched with plasma of a gas mixture of helium (He) and at least one fluorinated hydrocarbon by using the metal hard mask layer as a mask.

Abstract: A rapid thermal processor, having a process chamber, including a stable heat source in the form of a heatable mass. Heat is provided to the heatable mass using a series of heating devices. The temperature of the heatable mass establishes the temperature of a semiconductor wafer placed in contact or in close proximity to the heatable mass. To reduce thermal gradients, the heatable mass can be included in an insulative compartment made of an insulating material, such as opaque quartz and the like. The top of the insulative compartment can include an access portion to allow the semiconductor wafer to be placed on the heatable mass disposed therein. During processing, the wafer may be further exposed to a high intensity radiation energy source for a short duration of time.

Abstract: One aspect of the invention relates to a method of removing a hard mask from a surface, especially a silicon surface. The hard mask is removed by first applying a sacrificial coating and then plasma etching. The sacrificial material fills pattern gaps formed using the hard mask and protects insulators, such as oxides, within those pattern gaps. The sacrificial material is removed together with the hard mask by the plasma etching. The invention provides a process for removing hard masks from silicon layers without significantly damaging either the silicon layer or any exposed oxides and can be applied in a variety of integrated circuit device manufacturing processes, such as patterning the floating gate layer of a flash memory device.

Abstract: A process for optically reducing charge build-up in an integrated circuit includes exposing the integrated circuit or portions thereof to a broadband radiation source. The process effectively reduces charge buildup that occurs in the manufacture of integrated circuits.

Abstract: A method for forming an adhesion/barrier liner with reduced fluorine contamination to improve adhesion and a specific contact resistance of metal interconnects including providing a semiconductor wafer having a process surface including an etched opening extending through a dielectric insulating layer thickness and in closed communication with a conductive underlayer surface; pre-heating the semiconductor wafer in a plasma reactor to a pre-heating temperature of at least about 400° C.; cleaning the etched opening according to a plasma assisted reactive pre-cleaning process (RPC) comprising nitrogen trifluoride (NF3); and, blanket depositing at least a first adhesion/barrier layer over the etched opening substantially free of fluorine containing residue.

Abstract: To determine an optimum addition ratio of ethyl alcohol in the etching gas in a plasma etching unit, an ethyl alcohol addition ratio at which the isotropic etching rate of the etching mask is obtained, and on the basis of the obtained ethyl alcohol addition ratio, the optimum addition ratio is determined, by performing an etching process using an etching gas containing ethyl alcohol in the optimum addition ratio, the portions of the bottom antireflective coating which are not covered with the etching mask are removed. Thus, it is possible to provide a novel etching method capable of appropriately removing unnecessary portions of the bottom antireflective coating which are not covered by photoresist without causing much damage to the photoresist used as the etching mask.

Abstract: The degradation of deposited low dielectric constant interlayer dielectrics and gap fill layers, such as HSQ layers, during formation of contacts/vias is significantly reduced or prevented by employing a plasma containing CF4+H2O to remove the photoresist mask and cleaning the contact/via opening after anisotropic etching. The CF4+H2O plasma also enables rapid photoresist stripping at a rate of about 10 to about 20 KÅ/min. Embodiments include photoresist stripping and cleaning the contact/via opening with a CF4+H2O plasma to prevent reduction of the number of Si—H bonds of an as-deposited HSQ layer below about 70%.

Abstract: A method to form a semiconductor taper without etching the taper surfaces. In one embodiment, a semiconductor waveguide is formed on a workpiece having an unetched top surface; e.g., using a silicon insulator (SOI) wafer. A protective layer is formed on the waveguide. The protective layer is patterned and etched to form a mask that exposes a portion of the waveguide in the shape of the taper's footprint. In one embodiment, selective silicon epitaxy is used to grow the taper on the exposed portion of the waveguide so that the taper is formed without etched surfaces. Micro-loading effects can cause the upper surface of the taper to slope toward the termination end of the taper.

Abstract: Methods and apparatus for etching substrates such as silicon wafers are provided. In one specific approach, a surface of the substrate assembly is covered with a resist that is patterned to define features to be etched. In this approach, the surface is then exposed to a plasma in a plasma etcher so that surface areas not covered with the resist are etched, while the thickness of the resist increases or etches at a rate that is at least ten times slower than that of the exposed areas of the surface. This etching process can be followed with a conventional plasma etch. By combining the etching that increases the resist thickness with the conventional etching of resist in which the resist thins during etching, features having high aspect ratios can be etched.

Abstract: A method for manufacturing an electronic device is provided. In one example of the method, the method prevents deformation of a resist mask caused by the irradiation of exposure light. The resist mask has a resist as an opaque element, and can afford mask patterns undergoing little change even with an increase in the number of wafers subjected to exposure processing. The resist mask maintains a high dimensional accuracy. A photomask pattern is formed using as an opaque element a resist comprising a base resin and Si incorporated therein or a resist with a metal such as Si incorporated thereby by a silylation process, to improve the resistance to active oxygen. The deformation of a resist opaque pattern in a photomask is prevented. The dimensional accuracy of patterns transferred onto a Si wafer is improved in repeated use of the photomask.

Abstract: A modulated bias power etching method for etching a substrate is disclosed. The method alternatively deposits and etches material from a low aspect area of an integrated circuit device to form a static area while etching material from a high aspect area. The modulation pulse period and repetition rate are adjusted to permit deposition at low aspect ratio and very little or no deposition at high aspect ratio during the deposition cycle and to permit etching of the material deposited on the low aspect ratio area and etching of the material in the high aspect ratio area during the etching cycle.

Abstract: This invention relates to a method for reducing halogen gasses and byproducts in post-etch applications. The method consists of exposing the substrate to O2/N2 plasma and water vapor in a process chamber.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A method of manufacturing a contact of a semiconductor device includes a series of pretreatment processes each performed in a plasma pretreatment module. A semiconductor substrate has an interlayer formed on an underlayer of a material containing silicon. A contact hole is formed in the interlayer to expose a surface of the underlayer. Subsequently, the semiconductor substrate is loaded into a plasma pretreatment module. The photoresist pattern is removed by ashing in the plasma pretreatment module. A damaged layer at the surface exposed by the contact hole is then removed in the plasma pretreatment module. Subsequently, the semiconductor substrate is pre-cleaned in the plasma pretreatment module. The semiconductor substrate is then transferred, while in a vacuum, to a deposition module. There, an upper layer is formed on the substrate to fill the contact hole.

Abstract: A semiconductor fabrication method that includes forming a film (109) comprising an imaging layer (112) and an under layer (110) over a semiconductor substrate (102). The imaging layer (112) is patterned to produce a printed feature (116) having a printed dimension (124). The under layer (110) is then processed to produce a sloped sidewall void (120) in the under layer (110) wherein the void (120) has a finished dimension (126) in proximity to the underlying substrate that is less than the printed dimension. Processing the under layer (110) may include exposing the wafer to high density low pressure N2 plasma.

Abstract: A plasma etching method is performed by plasma etching an SiN layer through a mask layer to form a first wiring portion and a second wiring portion, the first and the second wiring portions having different wiring densities in the etched SiN layer, the mask having two pattern portions respectively corresponding to the first and the second wiring portions. In the plasma etching step, by using an etching gas including fluorocarbon and C2H2F4, the line width variation between the first and the second wiring portions is restrained.

Abstract: A method of forming a narrow feature, such as a gate electrode (14) in an integrated circuit is disclosed. A gate layer (14) such as polycrystalline silicon is disposed near a surface of a substrate (12), and a hardmask layer (16) is formed over the gate layer (14). The hardmask layer (16) includes one or more dielectric layers (16a, 16b, 16c) such as silicon-rich silicon nitride, silicon oxynitride, and oxide. Photoresist (18) sensitive to 193 nm UV light is patterned over the hardmask layer (16) to define a feature of a first width (CD) that is reliably patterned at that wavelength. The hardmask layer (16) is then etched to clear from the surface of the gate layer (14). A timed overetch of the hardmask layer (16) reduces hardmask CD and that of the overlying photoresist (18) to the desired feature size. Etch of the gate layer is then carried out to form the desired feature.

Abstract: A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and removing the post-RIE polymer material by-product with a wet clean.

Abstract: Disclosed herein is a method for forming a silicon epitaxial layer. The method comprises the steps of cleaning the surface of a silicon substrate having dopant of predetermined concentration doped therein with mixed plasma comprising an etching gas containing fluorine and hydrogen or deuterium, and forming a silicon epitaxial layer on the cleaned surface of the silicon substrate. The doped concentration of the silicon substrate is preferably 1018 to 1021 atoms/cm3. According to the present invention, a new preliminary cleaning step is adopted, whereby a silicon epitaxial layer of good quality is formed on a highly doped silicon substrate at a low temperature of 700° C. or less.

Abstract: One aspect of the present invention relates to a system and method for monitoring in-situ a chemical composition at or near a surface of a wafer during plasma etch to detect defects The method involves the steps of providing a semiconductor substrate comprising at least one top layer, wherein the semiconductor substrate comprises at least one chemical-containing contaminant; subjecting the semiconductor substrate to a plasma etch process, whereby at least a portion of the top layer is removed; during the plasma etch process, detecting for a presence of the chemical-containing contaminant using one of an Auger Electron Spectroscopy system or Energy Dispersive X-ray Analysis system; and if present, determining whether the presence of the chemical-containing contaminant exceeds a threshold limit.

Abstract: In a method for photo-electrochemical etching of a semiconductor sample, the semiconductor sample is brought in contact with an electrolyte liquid. The contact area formed thereby is illuminated through the electrolyte liquid with UV light. The photo-current created by UV light irradiation at the contact area is measured. To increase the etching quality, a jet of fresh electrolyte liquid is repeatedly applied to the contact area. A device for carrying out the method includes a container to be filled with an electrolyte liquid, a UV source for illuminating the semiconductor sample with UV light through the electrolyte liquid, and a measuring instrument for measuring the photo-current created during UV light irradiation of the contact area. Further provided are an inlet for supplying fresh electrolyte liquid, directed towards the semiconductor sample, and a device attached to the inlet for repeated production of electrolyte fluid jets, directed towards the semiconductor sample.

Abstract: A method of making a semiconductor structure, comprises etching a nitride layer with a plasma to form a patterned nitride layer. The nitride layer is on a semiconductor substrate, a photoresist layer is on the nitride layer, and the plasma is prepared from a gas mixture comprising CF4 and CHF3 at a pressure of at least 10 mtorr.

Abstract: A Si etching method etches a Si wafer held on a susceptor placed in a processing vessel by a plasma-assisted etching process. A mixed etching gas prepared by mixing fluorosulfur gas, such as SF6 gas, or fluorocarbon gas, O2 gas and fluorosilicon gas, such as SiF4 gas is supplied into the processing vessel. RF power of 40 MHz or above is applied to the mixed etching gas to generate a plasma. The Si wafer is etched with radicals and ions contained in the plasma.

Abstract: The invention relates to a gas for removing deposits by a gas-solid reaction. This gas includes a hypofluorite that is defined as being a compound having at least one OF group in the molecule. Various deposits can be removed by the gas, and the gas can easily be made unharmful on the global environment after the removal of the deposits, due to the use of a hypofluorite. The gas may be a cleaning gas for cleaning, for example, the inside of an apparatus for producing semiconductor devices. This cleaning gas comprises 1-100 volume % of the hypofluorite. Alternatively, the gas of the invention may be an etching gas for removing an unwanted portion of a film deposited on a substrate. The unwanted portion can be removed by this etching gas as precisely as originally designed, due to the use of a hypofluorite. The invention further relates to a method for removing a deposit by the gas.

Abstract: A method and apparatus to remove contamination and control electrostatic discharge in-situ in a semiconductor device manufacture process. In an embodiment, the method includes providing a reticle having first and second planar surfaces into a chamber. A circuit pattern of opaque material may be disposed on the first planar surface of the reticle. The method further includes irradiating the reticle using an ultraviolet light radiation beam to remove contamination disposed on the first and second planar surfaces of the reticle and to neutralize static electricity accumulated by the reticle.

Abstract: In a method for dry-etching a coating by use of reactive gas which is activated, a second insulating layer containing carbon atoms which is formed on a first insulating layer containing carbon atoms is ashed by use of a gas containing carbon atoms and at least one of oxygen atoms, nitrogen atoms and hydrogen atoms. By using the above gas, the second insulating layer containing carbon atoms which is formed on the first insulating layer which is an underlying layer can be efficiently ashed and removed without removing carbon atoms in the side surface of the grooves formed in the first insulating layer and etching the side surface thereof. Thus, the side surface of the groove formed in the first insulating layer will not be modified or deformed.

Abstract: A method is provided for determining the end point during cleaning etching of processing chambers by means of plasma etching, which is used for carrying out coating or etching processes during the manufacture of semiconductor components. The invention provides a method for effectively and reliably determining the end point during cleaning etching of processing chambers. The end point is determined by monitoring the DC bias voltage on the plasma generator which is used for the plasma cleaning etching in the processing chamber in an evaluation unit. The plasma cleaning etching process is terminated by stopping the supply of the process gases in the gas supply unit and by switching off the plasma generator upon reaching a predetermined DC bias voltage value which corresponds to completion of the cleaning etching process.

Abstract: A method for dynamically maintaining compatible contamination levels of equipment, wafer Lots and FOUP's used for automated processing of a Split Lot of wafers. Processing of the test Lot and the production Lot continue as a single Lot along the production processing path up to a split condition process. Processing of the production Lot is put on hold and its designated contamination level is saved until the alternate processing or test Lot processing is completed. The contamination level of the Split Lot is reevaluated based on the completed process(es) and will be designated at the same level it carried at the Split or a higher contamination level if appropriate. The two Lots are then merged and given the highest contamination level of either the saved level or the Split Lot. The two Lots are then processed according to the original predefined process steps and at the redefined contamination level.

Abstract: A method for plasma treatment etches an SiC layer with an increased etching rate and enhanced selectivities of SiC with respect to SiO2 and an organic layer. An etching gas is converted into plasma to etch SiC. The etching gas may include CHF3; CHF3 and N2, for example, a mixed gas of CHF3, N2 and Ar; or a material having C, H and F and a material having N but without any material having O.

Abstract: A method for manufacturing a semiconductor device wherein phenomenon called the skirting and dispersion in reliability of a TFT among lots can be reduced is provided by using a method for cleaning a plasma etching apparatus, a method for plasma etching, and a method for manufacturing a semiconductor device using the plasma etching method. Concretely, the plasma density may be kept constant by exciting plasma using a gas capable of etching quartz, for example, Cl2, or a mixed gas of Cl2 with a fluorine-based gas such as CF4 after using an etching gas such as BCl3 with which BOx adheres to the quartz surface and thus removing the BOx adhering to the quartz surface inside the chamber (that is, cleaning is performed).

Abstract: It is an object of the present invention to provide a process for a fluorine containing carbon film (a CF film), which can put an interlayer insulator film of a fluorine containing carbon film into practice. A conductive film, e.g., a TiN film 41, is formed on a CF film 4. After a pattern of a resist film 42 is formed thereon, the TiN film 41 is etched with, e.g., BCl3 gas. Thereafter, when the surface of the wafer is irradiated with O2 plasma, the CF film is chemically etched, and the resist film 42 is also etched. However, since the TiN film 41 functions as a mask, a predetermined hole can be formed. Although an interconnection layer of aluminum or the like is formed on the surface of the CF film 4, the TiN film 41 functions as an adhesion layer for adhering the interconnection layer to the CF film 4 and serves as a part of the interconnection layer. As the mask, an insulator film of SiO2 or the like may be substituted for the film.

Abstract: A process for removal of a photoresist mask used to etch openings in low k carbon-doped silicon oxide dielectric material of an integrated circuit structure, and for removing etch residues remaining from either the etching of the openings or removal of the resist mask, while inhibiting damage to the low k dielectric material comprises. The structure is exposed to a reducing plasma to remove a portion of the photoresist mask, and to remove a portion of the residues remaining from formation of the openings in the layer of low k dielectric material. The structure is then exposed to an oxidizing plasma to remove any remaining etch residues from the openings in the layer of low k dielectric material or removal of the resist mask.

Abstract: A method of manufacturing a TFT array panel according to the present invention forms a gate wire on an insulating substrate. The gate wire includes a plurality of gate lines and a plurality of gate electrodes connected to the gate lines. A semiconductor layer and a gate insulating layer are sequentially formed and a data wire is formed thereon. The data wire includes a plurality of data lines intersecting the gate lines, a plurality of source electrodes connected to the data lines and placed close to the gate electrodes, and a plurality of drain electrodes opposite the source electrodes with respect to the gate electrodes. A passivation layer is deposited and patterned to form a plurality of contact holes exposing the drain electrodes at least.

Abstract: A process is described for trimming photoresist patterns during the fabrication of integrated circuits for semiconductor devices and MEMS devices. A combination of a low temperature (<20° C.), high density oxygen and argon plasma and intense UV radiation is used to simultaneously trim and harden a photoresist linewidth in an ICP chamber. As an alternative, a UV hardening step can be performed in a flood exposure tool prior to the ICP plasma etch. Another option is to perform the argon plasma treatment first to harden the resist and then in a second step apply an oxygen plasma to trim the photoresist. Vertical and horizontal etch rates are decreased in a controllable manner which is useful for producing gate lengths in MOS transistors of less than 100 nm. The process can also be used to controllably increase a space width in a photoresist feature.

Abstract: A resist pattern is formed on a film to be processed using a lithography technique. The line width of the resist pattern is narrowed using a slimming technique. Thereafter, the pattern of a first film to be processed is formed in the space that has been widened by slimming, utilizing the phenomenon in which anisotropic etching under a reduced pressure accelerates the etching rate in the vicinity of the side of the line of the pattern compared to other areas. An underlying second film to be processed is etched using the first film to be processed as a mask. Thereby the pattern of the second film to be processed that has a pitch ½ the lithography pattern is formed.

Abstract: After formation of Cu interconnections 46a to 46e each to be embedded in an interconnection groove 40 of a silicon oxide film 39 by CMP and then washing, the surface of each of the silicon oxide film 39 and Cu interconnections 46a to 46e is treated with a reducing plasma (ammonia plasma). Then, without vacuum break, a cap film (silicon nitride film) is formed continuously. This process makes it possible to improve the dielectric breakdown resistance (reliability) of a copper interconnection formed by the damascene method.

Abstract: In power supply and a semiconductor making apparatus and a semiconductor fabricating method using the same, an abnormality can be detected when an offset occurs in a part constituting a closed-loop system of high-frequency power supply or dc power supply for a semiconductor making apparatus. Power supply for receiving a power value setting signal to set strength of power and a power on/off instruction to set on or off of outputting of the power interrupts the supply of the power even in a state in which a subsequent power on/off instruction is on if a power sense signal according to a value obtained by sensing the power exceeds a predetermined value when the power on/off instruction is off.

Abstract: In a process for etching poly Si gate stacks with raised STI structure where the thickness of poly Si gates at the M and STI are different, the improvement comprising:

Abstract: A method for polishing front and back surfaces of a semiconductor wafer includes the step of providing a polishing apparatus having a wafer carrier generally disposed between a first polishing pad and a second polishing pad. The first pad has a hardness significantly greater than a hardness of the second pad. The wafer is placed in the wafer carrier so that the front surface faces the first pad and so that the back surface faces the second pad. A polishing slurry is applied to at least one of the pads and the carrier, first pad and second pad are rotated. The front surface is brought into contact with the first pad and the back surface is brought into contact with the second pad for polishing the front and back surfaces of the wafer whereby less wafer material is removed from the back surface engaged by the second pad and the back surface has less gloss than the front surface after polishing so that the front surface and back surface are visually distinguishable.

Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilicon compound and an oxidizing gas at a constant RF power level from about 10W to about 200W or a pulsed RF power level from about 20W to about 500W. Dissociation of the oxidizing gas can be increased prior to mixing with the organosilicon compound, preferably within a separate microwave chamber, to assist in controlling the carbon content of the deposited film. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop and an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers.

Abstract: A method of etching high aspect ratio, anisotropic deep trench openings in a silicon substrate coated with a multilayer mask comprising in sequence a pad oxide layer, a silicon nitride layer, a doped or undoped silicon oxide hard mask layer, a polysilicon hard mask layer, an antireflection coating and a patterned photoresist layer in a single chamber comprising patterning the antireflection coating and hard mask layer, removing the photoresist and antireflection layers with oxygen, using the patterned polysilicon as a hard mask layer etching an opening in the silicon oxide hard mask layer, the silicon nitride layer and the pad oxide layer, removing the polysilicon hard mask layer with CF4/CHF3, and etching an anisotropic deep trench in the silicon substrate using the patterned silicon oxide hard mask layer as a mask and an etchant mixture including nitrogen trifluoride that self-cleans the chamber.

Abstract: A method for forming within a dielectric layer upon a substrate within a microelectronics fabrication a series of contact via holes etched through the dielectric layer to multi-level contact layers employing reactive plasma etching methods to form the series of contact via holes. The first plasma etch method employs fluorine containing gases to form the etched via holes, and then the second plasma etch method employs oxygen and a fluorocarbon gas to complete the etching of the via holes and remove residual materials. The etched via holes access multi-level contact layers formed upon the substrate at differing heights with respect to the substrate, penetrating through at least one contact layer. This permits formation of a series of electrical contacts, between the series of contact layers and patterned conductor layers through the series of via holes, with low electrical resistances.

Abstract: A method for cleaning a contact area of a metal line wherein a nitride barrier layer is formed on a sidewall of an insulating interlayer within the contact area by introducing the nitrogen-based radical to the contact area, whereby it is possible to prevent a low dielectric insulating interlayer from becoming deteriorated by the redeposition of metal ions and by hydrogen radical activated during reactive cleaning, thereby maintaining a low dielectric characteristic of the insulating interlayer.

Abstract: A method of removing ALF defects on a device after pad etching process, comprising the steps of: (a) applying EKC solution substantially comprising hydroxylamine (HDA) to the device for about 30 min; (b) applying an intermediate rinse chemical, such as Isopropyl alcohol (IPA) or N-methyl pyrrolidone (NMP), to the device for about 0.5 min to 3 min; and (c) applying water to the device. The ALF defects are effectively removed in the method of the invention, and the bad wafers can be turned to the good ones. Consequently, the primary cost during the manufacture is greatly decreased.

Abstract: A rapid thermal processor, having a process chamber, including a stable heat source in the form of a heatable mass. Heat is provided to the heatable mass using a series of heating devices. The temperature of the heatable mass establishes the temperature of a semiconductor wafer placed in contact or in close proximity to the heatable mass. To reduce thermal gradients, the heatable mass can be included in an insulative compartment made of an insulating material, such as opaque quartz and the like. The top of the insulative compartment can include an access portion to allow the semiconductor wafer to be placed on the heatable mass disposed therein. During processing, the wafer may be further exposed to a high intensity radiation energy source for a short duration of time.

Abstract: One embodiment of the present invention is a method used to fabricate an integrated circuit device on a wafer or substrate at a stage where a gate oxide is disposed over the wafer or substrate, a polysilicon layer is disposed thereover, a patterned hardmask is disposed thereover, a patterned antireflective coating is disposed thereover, and a patterned photoresist is disposed thereover, the method including steps of: (a) before stripping the photoresist, etching the polysilicon utilizing a first etch chemistry for a first period of time; and (b) etching the polysilicon utilizing a second etch chemistry for a second period of time.

Abstract: An RF coil for a plasma etch chamber is provided in which the RF coil is substantially flat over a portion of at least one turn of the coil. In one embodiment, each turn of the coil is substantially flat over a majority of each turn. In one embodiment of the present inventions, each turn of the coil is substantially flat over approximately 300 degrees of the turn. In the final approximate 60 degrees of the turn, the coil is sloped down to the next turn. Each turn thus comprises a substantially flat portion in combination with a sloped portion interconnecting the turn to the next adjacent turn. In one embodiment, the RF coil having turns with substantially flat portions is generally cylindrical. Other shapes are contemplated such as a dome shape. In some applications such as an RF plasma etch reactor, it is believed that providing an RF coil having turns comprising flat portions with sloped portions interconnecting the flat portions can improve uniformity of the etch process.