Abstract: A method for selectively etching a substrate is described. The method includes disposing a substrate comprising a silicon nitride (SiNy) layer overlying silicon in a plasma etching system, and transferring a pattern to the silicon nitride layer using a plasma etch process, wherein the plasma etch process utilizes a process composition having as incipient ingredients a process gas containing C, H and F, and an additive gas including CO2. The method further includes: selecting an amount of the additive gas in the plasma etch process to achieve: (1) a silicon recess formed in the silicon having a depth less than 10 nanometers (nm), and (2) a sidewall profile in the pattern having an angular deviation from 90 degrees less than 2 degrees.

Abstract: Disclosed is a semiconductor device fabricating method. A substrate is provided thereon with: an inorganic insulating film; a first inorganic sacrifice film stacked on the inorganic insulating film and having components different from those of the inorganic insulating film; a second sacrifice film formed of an inorganic insulative film stacked on the first sacrifice film, wherein a pattern for forming grooves for wiring embedment is formed in the second sacrifice film; and an organic layer including a photoresist film, wherein a pattern for forming holes for wiring embedment is formed in the organic film. According to the present invention, the thickness of the organic layer is set to be greater than the sum of the thicknesses of etch target films, i.e., the insulating film, the first sacrifice film and the second sacrifice film; the etch target films are etched in a selectivity-less manner by using plasma generated from a mixed gas of CF4 gas and CHF3 gas.

Abstract: A plasma etching method includes disposing first electrode and second electrodes; preparing a part in a processing chamber; supporting a substrate by the second electrode to face the first electrode; vacuum-evacuating the processing chamber; supplying a first processing gas containing an etchant gas into a processing space between the first electrode and the second electrode; generating a plasma of the first processing gas in the processing space by applying a radio frequency power to the first electrode or the second electrode; and etching a film on the substrate by using the plasma. Further, a resist modification process includes vacuum-evacuating the processing chamber; supplying a second processing gas into the processing space; generating a plasma; and applying a negative DC voltage to the part, the part being disposed away from the substrate in the processing chamber and injecting electrons discharged from the part into the resist pattern on the substrate.

Abstract: Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.

Abstract: A technique for increasing productivity by simplified steps in a manufacturing process of TFTs, electronic circuits using TFTs, and semiconductor devices formed of TFTs is provided. A method for manufacturing a semiconductor device includes forming a light absorbing layer, forming a light-transmitting layer on the light absorbing layer emitting a linear laser beam with a homogenized energy onto a mask and thereby splitting the linear laser beam into a plurality of laser beams and emitting the plurality of laser beams onto the light-transmitting layer on the light absorbing layer, and thereby forming a plurality of openings in the light-transmitting layer and the light absorbing layer.

Abstract: In a method of forming a hole, an insulation layer is formed on a substrate, and a preliminary hole exposing the substrate is formed through the insulation layer. A photosensitive layer pattern including an organic polymer is then formed on the substrate to fill the preliminary hole. An etching gas including hydrogen fluoride (HF) or fluorine (F2) is then provided onto the photosensitive layer pattern to etch the insulation layer so that width of the preliminary hole is increased.

Abstract: A plasma processing apparatus in which consumption of expensive krypton and xenon gases is suppressed as much as possible while reducing damage on a workpiece during plasma processing. In plasma processing of a substrate using a rare gas, two or more kinds of different rare gases are employed, and an inexpensive argon gas is used as one rare gas and any one or both of krypton and xenon gases having a larger collision cross-sectional area against electron than that of the argon gas is used as the other gas. Consequently, consumption of expensive krypton and xenon gases is suppressed as much as possible and damage on a workpiece is reduced during plasma processing.

Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.

Abstract: The plasma etching method includes: an etching step of placing, on a stage in a chamber, a substrate in which a prescribed mask pattern is formed by a protective film on a surface of a material to be etched, generating a plasma in the chamber while supplying processing gas to the chamber, and etching a portion of the material corresponding to an opening portion in the mask pattern; a voltage measurement step of, during the etching in the etching step, measuring a voltage at the surface of the material on a side where the mask pattern is formed, through a conductive member that is placed in contact with the surface of the material on the side where the mask pattern is formed; and a control step of controlling an etching condition in the etching step in accordance with a measurement result obtained in the voltage measurement step.

Abstract: A method and apparatus are provided to form spacer materials adjacent substrate structures. In one embodiment, a method is provided for processing a substrate including placing a substrate having a substrate structure adjacent a substrate surface in a deposition chamber, depositing a spacer layer on the substrate structure and substrate surface, and etching the spacer layer to expose the substrate structure and a portion of the substrate surface, wherein the spacer layer is disposed adjacent the substrate structure. The spacer layer may comprise a boron nitride material. The spacer layer may comprise a base spacer layer and a liner layer, and the spacer layer may be etched in a two-step etching process.

Abstract: A method and apparatus that may comprise an EUV light producing mechanism utilizing an EUV plasma source material comprising a material that will form an etching compound, which plasma source material produces EUV light in a band around a selected center wavelength comprising: an EUV plasma generation chamber; an EUV light collector contained within the chamber having a reflective surface containing at least one layer comprising a material that does not form an etching compound and/or forms a compound layer that does not significantly reduce the reflectivity of the reflective surface in the band; an etchant source gas contained within the chamber comprising an etchant source material with which the plasma source material forms an etching compound, which etching compound has a vapor pressure that will allow etching of the etching compound from the reflective surface. The etchant source material may comprises a halogen or halogen compound.

Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. A two frequency plasma source is used to form a plasma in a plasma reactor. In various embodiments, different quantities of power are supplied to a power source operating at the first frequency and a power source operating at the second frequency over time.

Abstract: A method for fabricating a semiconductor device includes stacking a spin on carbon (SOC) layer and an multifunction hard mask (MFHM) layer on a substrate, forming a photoresist pattern over the MFHM layer, first etching the MFHM layer using a first amount of a fluorine-based gas, second etching the MFHM layer using a second amount of a fluorine-based gas, wherein the second amount is less than the first amount, etching the SOC layer using the MFHM layer as an etch barrier, and etching the substrate using the SOC layer and the MFHM layer as an etch barrier.

Abstract: A substrate processing method capable of preventing a substrate rear surface from being scratched when attracted onto an electrostatic chuck. In a coater/developer (11), a photocurable resin is coated onto a rear surface of a wafer (W), the resin is cured to form a resin protective film, and a resist is coated onto a front surface of the wafer. An exposing apparatus (12) subjects the resist to light exposure processing, irradiating ultraviolet light onto a resist portion of a pattern reversed with respect to a mask pattern. The coater/developer uses a washing liquid to remove the resist, thereby forming a resist film. In an etching apparatus (13), the front surface of the wafer is electrostatically attracted onto an electrostatic chuck (49) is subjected to RIE processing. In a washing apparatus (14), the resin protective film is dissolved and removed.

Abstract: A process is provided for removing polymer from a backside of a workpiece and/or photoresist from a front side of the workpiece. For backside polymer removal, the wafer is positioned near the ceiling to above a localized or remote plasma source having a side outlet through the sidewall of the chamber, and backside polymer is removed by rotating the workpiece while flowing plasma by-products from the side outlet to the wafer backside. For front side photoresist removal, the wafer is positioned away from the ceiling and below the side outlet of the localized plasma source, and front side photoresist is remove by rotating the workpiece while flowing plasma by-products from the side outlet to the wafer front side.

Abstract: A method and apparatus for controlling characteristics of a plasma in a semiconductor substrate processing chamber using a dual frequency RF source is provided. The method comprises supplying a first RF signal to a first electrode disposed in a processing chamber, and supplying a second RF signal to the first electrode, wherein an interaction between the first and second RF signals is used to control at least one characteristic of a plasma formed in the processing chamber.

Abstract: Method for manufacturing a semiconductor device including a semiconductor substrate, an element formed on the substrate, and an insulating film formed on the element, includes: (a) forming a first conductive layer (b) forming a first insulating film on the upper portion of the first conductive layer; (c) forming a second insulating film with a porous structure on the first insulating film; (d) forming a third insulating film different from the second insulating film on the second insulating film; (e) forming a via hole in the second and third insulating film by dry etching of the third insulating films; (f) removing a part of the first insulating film such that the surface of the first conductive layer is exposed at the bottom of the via hole and (g) forming a second conductive material film layer so as to fill the via hole.

Abstract: A micro electro-mechanical system (MEMS) device package and a method of manufacturing the same are provided.

Abstract: A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid thermal annealing of a large-diameter wafer.

Abstract: A method for fabricating a TFT is provided. First, a poly-silicon layer is formed over a substrate. A photoresist layer is formed on the poly-silicon layer, wherein the photoresist layer has a pattern for exposing parts of the poly-silicon layer, and the pattern has a varied thickness. The poly-silicon layer is patterned by using the photoresist layer as an etching mask to define a poly-silicon island. Thereafter, a part of the thickness of the photoresist layer is removed for exposing a part of the poly-silicon island. Then, a first ion implanting is performed on the exposed part of the poly-silicon island to form a source and a drain thereby. After removing the residue photoresist layer; a gate insulating layer, a gate, a patterned dielectric layer and a conductive layer are formed on the substrate sequentially.

Abstract: A process for forming an interconnect structure in a low-k dielectric layer includes etching to form trenches in the dielectric layer, removal of photoresist, and further etching to remove damaged portions of the dielectric layer in sidewalls of the trenches. An interconnect structure includes a low-k dielectric layer formed on a substrate, and a conductor embedded in the dielectric layer, the conductor having an edge portion with an inwardly rounded shape.

Abstract: A method and apparatus for local beam processing using a beam activated gas to etch material are described. Compounds are disclosed that are suitable for beam-induced etching. The invention is particularly suitable for electron beam induced etching of chromium materials on lithography masks. In one embodiment, a polar compound, such as ClNO2 gas, is activated by the electron beam to selectively etch a chromium material on a quartz substrate. By using an electron beam in place of an ion beam, many problems associated with ion beam mask repair, such as staining and riverbedding, are eliminated. Endpoint detection is not critical because the electron beam and gas will not etch significantly the substrate.

Abstract: A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film and a film treatment process for improving film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is being maintained by a high-density plasma radiation treatment based upon ion and radical reactions and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film which is excellent in film quality can be manufactured inexpensively by a low-temperature treatment.

Abstract: Methods for monitoring and detecting optical emissions while performing photoresist stripping and removal of residues from a substrate or a film stack on a substrate are provided herein. In one embodiment, a method is provided that includes positioning a substrate comprising a photoresist layer into a processing chamber; processing the photoresist layer using a multiple step plasma process; and monitoring the plasma for a hydrogen optical emission during the multiple step plasma process; wherein the multiple step plasma process includes removing a bulk of the photoresist layer using a bulk removal step; and switching to an overetch step in response to the monitored hydrogen optical emission.

Abstract: A process for selectively removing photoresist, organic overlayers, and/or polymers/residues from a substrate without altering the surface chemistry and adhesion properties of the underlying substrate layers is provided. Generally, the process includes pretreating the substrate with hydrogen (e.g., by way of a hydrogen-based plasma) prior to deposition of a photoresist layer, and then ashing the substrate with a hydrogen-based plasma to selectively remove the photoresist, organic overlayers, and/or polymers/residues from the substrate during etching, post-etch, rework, etc. The hydrogen-based ashing process of the invention may be used post-etch to remove the residue photoresist, or may be used in a rework stripping process to remove misaligned patterns. The hydrogen-based ashing process following the initial hydrogen surface pretreatment substantially reduces surface chemistry poisoning, while retaining adequate adhesion properties following ashing.

Abstract: A method of pre-treating a mask layer prior to etching an underlying thin film is described. A thin film, such as a dielectric film, is etched using plasma that is enhanced with a ballistic electron beam. In order to reduce the loss of pattern definition, such as line edge roughness effects, the mask layer is treated with an oxygen-containing plasma or halogen-containing plasma or a noble gas plasma or a combination of two or more thereof prior to proceeding with the etching process.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A method of manufacturing an electronic device is provided wherein an interconnect is made using 193 nm lithography. No deformation of the desired linewidth takes place in that during a plasma gas is used which dissociates in low-weight ions. The electronic device is particularly an integrated circuit.

Abstract: A method and an apparatus for plasma processing which can accurately monitor an ion current applied to the surface of a sample. Predetermined gas is exhausted via an exhaust port by a turbo-molecular pump while introducing the gas within the vacuum chamber from a gas supply device, and the pressure within the vacuum chamber is kept at a predetermined value by a pressure regulating valve. A high-frequency power supply for a plasma source supplies a high-frequency power to a coil provided near a dielectric window to generate inductively coupled plasma within the vacuum chamber. A high-frequency power supply for the sample electrode for supplying the high-frequency power to the sample electrode is provided. A matching circuit for the sample electrode and a high-frequency sensor are provided between the sample electrode high-frequency power supply and the sample electrode. An ion current applied to the surface of a sample can be accurately monitored buy using the high-frequency sensor and an arithmetic device.

Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.

Abstract: Embodiments relate to an image sensor and a method for manufacturing an image sensor. According to embodiments, an interlayer insulating layer including a metal line may be formed on and/or over a semiconductor substrate. A lower electrode layer connected with the metal line may be formed on and/or over the interlayer insulating layer. A photoresist pattern may be formed on and/or over the lower electrode layer and may form lower electrodes separated from each other. The photoresist pattern may be removed. A polymer with Cl group that may be generated when removing the photoresist pattern may be removed. According to embodiments, by removing the polymer, photons that may be generated in a photo diode may be more easily gathered, which may enhance an image quality of an image sensor.

Abstract: Process and apparatus provide reactive radicals generated from a remote plasma source which contact a portion of a substrate surface simultaneous with a contact of the same substrate surface with a light source which locally activates the portion of the substrate surface in contact with said radicals.

Abstract: A dry etching method is provided, in which dry etching is performed in such a manner that a conductor to which an insulative substrate is attached is brought in electric, intimate contact with an electrode. In the dry etching method, the insulative substrate is attached to the conductor by means of a conductive grease. A diffractive optical element manufactured with the dry etching method is also provided.

Abstract: The invention provides a chemical-mechanical polishing composition comprising silica, a compound in an amount sufficient to provide about 0.2 mM to about 10 mM of a metal cation selected from the group consisting of gallium (III), chromium (II), and chromium (III), and water, wherein the polishing composition has a pH of about 1 to about 6. The invention further provides a method of chemically-mechanically polishing a substrate with the aforementioned polishing composition.

Abstract: The present invention, in one embodiment, provides a method of forming a gate structure including providing a substrate including a semiconducting device region, a high-k dielectric material present atop the semiconducting device region, and a metal gate conductor atop the high-k dielectric material, applying a photoresist layer atop the metal gate conductor; patterning the photoresist layer to provide an etch mask overlying a portion of the metal gate conductor corresponding to a gate stack; etching the metal gate conductor and the high-k dielectric material selective to the etch mask; and removing the etch mask with a substantially oxygen free nitrogen based plasma.

Abstract: The invention provides a method for producing a quartz glass jig for use in semiconductor industries, which enables increasing the surface layer cleanliness simply and surely at low cost; it also provides a quartz glass jig improved in surface layer cleanliness. The inventive means for resolution are a method comprising processing a quartz glass raw material into a desired shape by a treatment inclusive of fire working, annealing for stress removal, and cleaning treatment to obtain the final product, the method is characterized by that it comprises performing gas phase etching step and gas phase purification step on the surface layer of the quartz glass jig after applying the annealing treatment for stress removal but before the cleaning treatment, wherein the gas phase purification step is carried out continuously after the gas phase etching step.

Abstract: A metal wiring suitable for a substrate of large size is provided. The present invention is characterized in that at least one layer of conductive film is formed on an insulating surface, a resist pattern is formed on the conductive film, and the conductive film having the resist pattern is etched to form a metal wiring while controlling its taper angle ? in accordance with the bias power density, the ICP power density, the temperature of lower electrode, the pressure, the total flow rate of etching gas, or the ratio of oxygen or chlorine in etching gas. The thus formed metal wiring has less fluctuation in width or length and can satisfactorily deal with an increase in size of substrate.

Abstract: Atomic oxygen generated in oxygen stripping plasmas reacts with and damages low-k dielectric materials during stripping of dielectric post etch residues. While damage of low-k dielectric materials during stripping of dielectric post etch residues is lower with hydrogen stripping plasmas, hydrogen stripping plasmas exhibit lower strip rates. Inclusion of oxygen in a hydrogen stripping plasma improves both photoresist strip rate and uniformity, while maintaining a hydrogen to oxygen ratio avoids low-k dielectric material damage.

Abstract: A method of electrostatically chucking a wafer while removing heat from the wafer in a plasma reactor includes providing a polished generally continuous surface on a puck, placing the wafer on the polished surface of the puck and cooling the puck. A chucking voltage is applied to an electrode within the puck to electrostatically pull the wafer onto the surface of the puck with sufficient force to attain a selected heat transfer coefficient between contacting surfaces of the puck and wafer.

Abstract: A method of dividing and separating a wafer having a plurality of devices formed on its front surface, which are separated by streets. The method includes applying a resist film coating to a portion of the back surface of the wafer other than an area corresponding to the streets, and plasma etching the area of the back surface corresponding to the streets to divide the wafer into a plurality of individual devices. The thickness of the resist film coating is adjusted in the coating operation to allow the resist film to be completely removed during the plasma etching.

Abstract: An etching apparatus of the present invention comprises a reaction chamber, a lower electrode placed on the bottom surface of the reaction chamber, an upper electrode placed at the ceiling of the reaction chamber to face the lower electrode, and a focus ring placed on the lower electrode and having a cavity for holding a to-be-processed substrate. The lower surface of the upper electrode is provided, at its middle part, with a recess having a smaller inside diameter than the diameter of the to-be-processed substrate. Thus, in the generation of plasma, the amount of further incident radicals can be reduced in a middle part of the to-be-processed substrate. Therefore, a hole or the like located in the middle part of the to-be-processed substrate can be formed to have a desired shape without having a tapered shape.

Abstract: A plasma etch process with in-situ backside polymer removal begins with a workpiece having a porous or non-porous carbon-doped silicon oxide dielectric layer and a photoresist mask on a surface of the workpiece. The workpiece is clamped onto an electrostatic chuck in an etch reactor chamber. The process includes introducing a fluoro-carbon based process gas and applying RF bias power to the electrostatic chuck and RF source power to an overhead electrode to etch exposed portions of the dielectric layer while depositing protective fluoro-carbon polymer on the photoresist mask. The process further includes removing the fluoro-carbon based process gas and introducing a hydrogen-based process gas and applying RF source power to the overhead electrode.

Abstract: Methods of forming arrays of small, densely spaced holes or pillars for use in integrated circuits are disclosed. Various pattern transfer and etching steps can be used, in combination with pitch-reduction techniques, to create densely-packed features. Conventional photolithography steps can be used in combination with pitch-reduction techniques to form sumperimposed, pitch-reduced patterns of crossing elongate features that can be consolidated into a single layer.

Abstract: A method of detecting an end point of a plasma etching process for etching a first layer on a second layer is described, the first layer producing a first etching product and the second layer a second etching product. Time-dependent intensity [Ij=1 to m(t)] of a number “m” (m?1) of spectral line(s) of the first etching product in emission spectrum of the plasma and that [Ii=1 to n(t)] of a number “n” (n?1) of spectral line(s) of the second etching product in the emission spectrum are collected, wherein “m+n?3” is satisfied. One index of Lm ? ( t ) ? [ = ? i = 1 , j = 1 n , m ? ? I i ? ( t ) I j ? ( t ) ] , Ls ? ( t ) ? [ = ? i = 1 , j = 1 n , m ? ? I i ? ( t ) I j ? ( t ) ] , Lm?(t) {=d[Lm(t)]/dt} and Ls?(t) {=d[Ls(t)]/dt} is calculated in real time and plotted with the time. An etching end-point is identified from the plot of the one index with the time.

Abstract: A method for patterning a low dielectric insulating layer of a semiconductor device improves adhesion between a photoresist and the low dielectric (Low-K) insulating layer by removing at least one hydroxyl group from a surface of the Low-K insulating layer with a beam. Reliability of the device is thereby improved. The method includes forming a Low-K insulating layer on a semiconductor substrate, irradiating the Low-K insulating layer with a beam to make the Low-K insulating layer hydrophobic, forming a photoresist pattern on the Low-K insulating layer, and ashing the photoresist pattern.

Abstract: A method of forming a floating gate electrode in a flash memory device. The method includes forming an isolation film in an inactive region so that a step with a predetermined thickness can be generated between an active region and the inactive region, which are defined in a semiconductor substrate, sequentially forming a tunnel oxide film, a polysilicon film for floating gate electrode and an anti-reflection film on the entire surface in which the isolation film is formed, and then forming photoresist patterns in predetermined regions of the anti-reflection film.

Abstract: A plasma processing method, which enables the etching controllability for a high-dielectric-constant insulating film to be improved. A substrate having a high-dielectric-constant gate insulating film and a hard mask formed thereon is subjected to etching processing using a plasma of a processing gas containing a noble gas and a reducing gas.

Abstract: A method of forming a feature in a low-k (k<3.0) dielectric layer is provided. A low-k dielectric layer is placed over a substrate. A patterned photoresist mask is placed over the low-k dielectric layer. At least one feature is etched into the low-k dielectric layer. A stripping gas comprising CO2 is provided. A plasma is formed from the stripping gas comprising CO2. The plasma from the stripping gas comprising CO2 is used to strip the patterned photoresist mask.

Abstract: A method of manufacturing a semiconductor device includes forming an insulating layer, a first conductive layer, a dielectric layer and a capping conductive layer over a semiconductor substrate in which a cell region is defined. The capping conductive layer and the dielectric layer is etched to form contact holes in a first region of a drain select line and a source select line region of the cell region. A second conductive layer, a tungsten silicide layer and a hard mask layer are formed over the semiconductor substrate including the contact holes. The hard mask layer, the tungsten silicide layer, the second conductive layer, the capping conductive layer, the dielectric layer and the first conductive layer are etched to form a cell gate. The hard mask layer, the tungsten silicide layer, the second conductive layer and the first conductive layer of the first region are etched to form a drain select line and a source select line.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.