Abstract: A carbon hard mask layer is applied to a substrate to be patterned by means of a plasma-enhanced deposition process in such a manner that it has a hardness comparable to that of diamond in at least one layer thickness section. During the production of this diamond-like layer thickness section, the parameters used in the deposition are set in such a manner that growth regions which are produced in a form other than diamond-like are removed again in situ by means of subsequent etching processes and that diamond-like regions which are formed are retained.

Abstract: A method for etching a multi-layer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the multi-layer resist into the etch chamber. SO2 gas flows into the etch chamber and a plasma is struck in the etch chamber while flowing the SO2 gas. The multi-layer resist is then etched.

Abstract: A method of forming a metal line is provided. A first metal layer and a second metal layer protecting the first metal layer are formed on a base substrate. The first metal layer includes aluminum or aluminum alloy. A photoresist pattern having a linear shape is formed on the second metal layer. The first and second metal layers are dry-etched using etching gas and the photoresist pattern as an etching mask. An etching material is removed from the base substrate, to prevent corrosion of the dry-etched first metal layer. Therefore, the source metal pattern without corrosion may be formed through a dry-etching process so that a manufacturing cost is decreased.

Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an insulation layer over a substrate; forming a hard mask layer over the insulation layer; forming a photoresist pattern over the hard mask layer; forming a polymer over the photoresist pattern to increase a thickness of the photoresist pattern; patterning the hard mask layer by using the photoresist pattern having the increased thickness; and selectively removing the insulation layer by using the photoresist pattern having the increased thickness and the hard mask layer as an etch mask to form a contact hole.

Abstract: The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.

Abstract: A method for forming a feature in a layer with reduced line edge roughening is provided. A photoresist layer is formed over the layer. The photoresist layer is patterned to form photoresist features with photoresist sidewalls. A sidewall layer with a thickness less than 100 nm is formed over the sidewalls of the photoresist features by performing for a plurality of cycles. Each cycle comprises depositing a layer on the photoresist layer wherein the deposited layer has a thickness between a monolayer to 20 nm. Features are etched into the layer through the photoresist features. The photoresist layer and sidewall layer are stripped.

Abstract: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting a process condition, including the flow rate of CH2F2 and the power coupled to the dry plasma etching system, such that a proper balance of active etching radicals and polymer forming radicals are formed within the etching plasma.

Abstract: A method for fabricating a semiconductor device is provided. The method includes: forming an inter-layer insulation layer on a substrate; forming a hard mask layer on the inter-layer insulation layer; etching the hard mask layer using a contact mask; and etching the inter-layer insulation layer using the hard mask layer as an etch barrier, thereby obtaining an opening wherein the etching of the hard mask layer and the etching of the inter-layer insulation layer are performed in one etch chamber.

Abstract: Via hole and trench structures and fabrication methods are disclosed. The structure comprises a conductive layer in a dielectric layer, and a via hole in the dielectric layer for exposing a portion of a surface of the conductive layer. A conductive liner covers the exposed surface of the first conductive layer. A trench is formed on the via hole in the dielectric without the conductive liner layer in the trench. Dual damascene structures and fabrications methods are also disclosed. Following the fabrication methods of the via hole and trench structures, a conductive layer is further formed in the via hole and trench structures.

Abstract: An edge protection process for semiconductor device fabrication includes forming a protective layer on the circumferential edge region of a semiconductor substrate. The semiconductor substrate is placed in a plasma atmosphere and trench structures, such as deep trenches and shallow trench isolation structures are etched in the substrate. The protective layer substantially prevents the etching of the circumferential edge region, such that the formation of black silicon is substantially minimized during the etching process.

Abstract: Precision in an etching process is to be improved. A detecting unit 404 detects a variation of plasma emission intensity at a plurality of wavelengths (an emission band having an intensity peak in the proximity of 358 nm and an emission band having an intensity peak in the proximity of 387 nm) during a dry etching process being performed on either of a nitrogen-containing film formed on a semiconductor substrate or a non-nitrogen film provided in direct contact with the nitrogen-containing film in an etching apparatus 402. An arithmetic processing unit 406 performs calculation based on detected variation. A control unit 410 determines an endpoint of the dry etching process in consideration of the calculation result.

Abstract: A method of selectively etching organosilicate layers in integrated circuit fabrication processes is disclosed. The organosilicate layers are selectively etched using a hydrogen-containing fluorocarbon gas. The hydrogen-containing fluorocarbon gas may be used to selectively etch an organosilicate layer formed on a silicon oxide stop etch layer when fabricating a damascene structure.

Abstract: Provided is a method for forming a fine pattern of a semiconductor device by controlling the amount of flow of a resist pattern, including forming a resist pattern having a predetermined pattern distance on a material layer to be etched, forming a flow control barrier layer on the resist pattern to control the amount of flow during a subsequent resist flow process and to make the profile of the flowed pattern be vertical, optionally forming the flow control barrier layer by coating a material including a water-soluble high-molecular material and a crosslinking agent on the resist pattern, mixing and baking the coated material layer, and processing the resultant structure using deionized water, carrying out the flow resist process to form a hyperfine pattern and etching the lower material layer, and thereby forming fine patterns having the shape of contact holes or lines and spaces to have a critical dimension of about 100 nm or less, even with use of a KrF resist.

Abstract: Methods and structures are provided for increasing alignment margins when contacting pitch multiplied interconnect lines with other conductive features in memory devices. The portions of the lines at the periphery of the memory device are formed at an angle and are widened relative to the portions of the lines in the array region of the memory device. The widened lines allow for an increased margin of error when overlaying other features, such as landing pads, on the lines. The possibility of contacting and causing electrical shorts with adjacent lines is thus minimized. In addition, forming the portions of the lines in the periphery at an angle relative to the portions of the lines in the array regions allows the peripheral portions to be widened while also allowing multiple landing pads to be densely packed at the periphery.

Abstract: A method for etching a bilayer resist defined over a substrate in a plasma etch chamber is provided. The method initiates with introducing the substrate having a pattern defined on a first layer of the bilayer resist into the etch chamber. Then SiCl4 gas flows into the etch chamber. Next, a plasma is struck in the etch chamber while flowing the SiCl4 gas. Then the bilayer resist is etched.

Abstract: Different sized features in the array and in the periphery of an integrated circuit are patterned on a substrate in a single step. In particular, a mixed pattern, combining two separately formed patterns, is formed on a single mask layer and then transferred to the underlying substrate. The first of the separately formed patterns is formed by pitch multiplication and the second of the separately formed patterns is formed by conventional photolithography. The first of the separately formed patterns includes lines that are below the resolution of the photolithographic process used to form the second of the separately formed patterns. These lines are made by forming a pattern on photoresist and then etching that pattern into an amorphous carbon layer. Sidewall pacers having widths less than the widths of the un-etched parts of the amorphous carbon are formed on the sidewalls of the amorphous carbon. The amorphous carbon is then removed, leaving behind the sidewall spacers as a mask pattern.

Abstract: A method of forming a microelectronic structure and its associated structures is described. That method comprises forming and patterning a deep uv resist layer on a substrate, etching the substrate in a plasma generated from a gas comprising a carbon to fluorine ratio from about 1:1 to about 2:3 to form substantially vertical sidewalls in the deep uv resist layer.

Abstract: A layer-by-layer etching apparatus and an etching method using a neutral beam which enables to control etching depth to an atomic level by controlling the etching of each atom of a material layer to be etched under precise control of the supply of an etching gas and irradiation of the neutral beam and enables to minimize etching damage. In the layer-by-layer etching method, a substrate to be etched, on which a layer to be etched is exposed, is loaded on a stage in a reaction chamber. An etching gas is supplied into the reaction chamber to adsorb the etching gas on the surface of an exposed portion of the layer to be etched. Excessive etching gas remaining after being adsorbed is removed. A neutral beam is irradiated on the layer to be etched on which the etching gas is adsorbed. Etch by-products generated by the irradiation of the neutral beam is removed.

Abstract: The present invention provides method and apparatus for surface treatment which, when employed in process steps of manufacturing semiconductor devices, can result in the final products having enhanced reliability. According to the surface processing method, an object to be processed W is introduced in a processing vessel 10, which is then supplied with ClF3 gas serving as cleaning gas from a supply unit 26. The ClF3 gas is bound to the surface of the object to be processed W, and although the supply of the gas to the processing vessel is interrupted, the ClF3 gas bound to the surface of the object to be processed W serves to clean the surface of the object to be processed. Next, reducing gas is introduced into the processing vessel W to remove chlorine from the object to be processed W, the chlorine being derived from the ClF3 gas. After that, the introduction of the reducing gas is interrupted, and the cleaned object to be processed W is exported from the processing vessel 10.

Abstract: An apparatus and a method for photoreducing copper oxide layers from semiconductor wafers during the processes of forming interconnects in advanced IC manufacturing. The apparatus comprises a reaction chamber with a high intensity UV light source and a wafer holder in the chamber. The UV light source is made of arrays of microdischarge devices fabricated on a semiconductor wafer where each of the microdischarge devices has the structure of a hollow cathode. Multiple arrays of microdischarge devices can be assembled together to make a planar UV lamp so as to provide a sufficient area for the UV illumination. The wafer holder in the chamber is made rotatable for a better uniformity during the photoreduction process. A non-oxidizing gas is flowed into the chamber to prevent instant and subsequent oxidation on the copper surface.

Abstract: A process for removing resist (114) from a CDO dielectric material (110) that uses a non-damaging plasma in a reducing atmosphere under high power and using a structure (150) or other means to limit ions from the plasma from reaching the surface of the CDO material (110).

Abstract: A semiconductor device capable of compatibly suppressing a microloading effect (irregular etching) and over-etching also in formation of a fine contact hole requiring a high aspect ratio is obtained. This semiconductor device comprises a first conductive part, an insulator film having an opening formed on the first conductive part and a second conductive part electrically connected with the first conductive part through the opening. The insulator film includes an upper insulator film and a lower insulator film, stacked/formed at least around a connection part between the first conductive part and the second conductive part, consisting of different materials.

Abstract: The present invention relates to a semiconductor device and a method for fabricating a contact of the semiconductor device, and in particular, to the method for fabricating a semiconductor contact of the device for electrically coupling upper and lower metal wires or coupling an electrode and a metal wire and a method for fabricating the contact. The method includes forming an interlayer insulating layer on a semiconductor substrate; forming a contact hole by selectively removing the interlayer insulating layer; forming a barrier metal layer on a surface of the interlayer insulating layer, increasing roughness of a surface of the barrier layer at an area around an inlet of the contact hole; and forming a contact by filling the contact hole with a conductive material. According to this method, the conductive layer is slowly deposited around the inlet of the contact hole relative to the other areas of the contact bole, such that it is possible to form a void free contact with a high aspect ratio.

Abstract: A multi-layered film on a semiconductor substrate is etched with a multi-step etching process by sequentially providing a plurality of process gases having different compositions in a chamber. A plasma discharge to excite the process gases is continued without an interruption during a switch to a different process gas. A relationship between different process gases desirable for the continuous plasma excitation is also disclosed. An apparatus suitable to practice this continuous plasma excitation process includes a process gas supply system having a gas reservoir. A mixture of at least two component gases is prepared and reserved in the reservoir, and is supplied to the etching chamber when it is needed.

Abstract: A method for creating semiconductor devices by etching a layer over a wafer is provided. A photoresist layer is provided on a wafer. The photoresist layer is patterned. The wafer is placed in a process chamber. The photoresist is hardened by providing a hardening plasma containing high energy electrons in the process chamber to harden the photoresist layer, wherein the high energy electrons have a density. The layer is etched within the process chamber with an etching plasma, where a density of high energy electrons in the etching plasma is less than the density of high energy electrons in the hardening plasma.

Abstract: According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.

Abstract: A dry etching method comprises sequentially laminating a first insulating layer containing carbon and a second insulating layer containing carbon on a substrate, patterning the second insulating layer to form a mask; forming grooves in the first insulating layer by etching the first insulating layer with the second insulating layer used as a mask such that each of the grooves has a side surface and a bottom surface in the first insulating layer; and removing the second insulating layer by use of a reactive gas containing carbon atoms and at least one of oxygen atoms, hydrogen atoms and nitrogen atoms.

Abstract: Disclosed is a method for fabricating a semiconductor device. The method comprises the steps of: sequentially forming a first anti-reflection layer and a first photoresist film on a substrate; forming a first image layer; forming a second anti-reflection layer and a second photoresist film; forming a second image layer which opens wider than the first image layer; supplying oxygen plasma to a resultant in order to transfer a pattern of the second image layer on the second anti-reflection layer and to transfer a pattern of the first image layer on the first anti-reflection layer, thereby forming an opening; forming a metal layer; forming a metal pattern to fill the opening; and removing the second image layer, the second anti-reflection layer, the first image layer, and the first anti-reflection layer.

Abstract: An etching process yields an optimized formation of via holes through the combination of semiconductor material selection and etchant parameters. Over an interlayer dielectric layer is formed a stop layer having a SiON layer over which is a SiC layer. Selective etching will attack the SiC layer while leaving the SiON layer undisturbed. When etching the via hole, a proportion of about 7:90 O2:CO was observed to yield a superior etch.

Abstract: A method of producing a field emission device includes laying a group III-nitride semiconductor layer over a substrate, placing a photoresist mask over the group III-nitride semiconductor layer, patterning a generally circular grid in the photoresist mask and the group III-nitride semiconductor layer, and forming the group III-nitride semiconductor layer into generally pointed tips using an inductively coupled plasma dry etching process, wherein the group III-nitride semiconductor layer comprises a group III-nitride semiconductor material having a low positive electron affinity or a even a negative electron affinity, wherein the inductively coupled plasma dry etching process selectively creates an anisotropic deep etch in the group III-nitride semiconductor layer, and wherein the inductively coupled plasma dry etching process creates an isotropic etch in the group III-nitride semiconductor layer. Preferably, the photoresist layer is approximately 1.

Abstract: A processing system and method for chemically treating a substrate, wherein the processing system comprises a temperature controlled chemical treatment chamber, and an independently temperature controlled substrate holder for supporting a substrate for chemical treatment. The substrate holder is thermally insulated from the chemical treatment chamber. The substrate is exposed to a gaseous chemistry, without plasma, under controlled conditions including wall temperature, surface temperature and gas pressure. The chemical treatment of the substrate chemically alters exposed surfaces on the substrate.

Abstract: A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.

Abstract: A method for forming a dual damascene structure in a semiconductor device manufacturing process including providing a process wafer including a via opening extending through at least one dielectric insulating layer; blanket depositing a negative photoresist layer to include filling the via opening; blanket depositing a positive photoresist layer over and contacting the negative photoresist layer; photolithographically patterning the positive photoresist layer to form a trench opening etching pattern overlying and encompassing the via opening; etching back the negative photoresist layer to form a via plug having a predetermined thickness; and, etching a trench opening according to the trench opening etching pattern.

Abstract: A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film, and a film treatment process for improving the film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is maintained by a high-density plasma radiation treatment based upon ion and radical reactions, and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film, which is excellent in film quality, can be manufactured inexpensively by a low-temperature treatment.

Abstract: A plasma etching method and apparatus in which a processing gas is supplied from a shower plate arranged on an electrode opposed to an electrode for generating a plasma or a sample toward the sample center, and the gas is transformed into a plasma thereby to etch the sample. RF power is applied between a sample stage and the electrode to apply the energy to charged particles in the plasma to thereby etch the sample. In the process, apart from the incidence of the charged particles to the sample, the charged particles enter also the shower plate of the electrode by application of the RF power. The charged particles entering the processing gas supply holes of the shower plate are neutralized to prevent abnormal discharge on the shower plate and consequently suppress the generation of foreign matter.

Abstract: A lithography process for creating patterns in an activating light curable liquid using electric fields followed by curing of the activating light curable liquid is described. The process involves the use of a template that is formed of non-conductive and electrically conductive portions. The template is brought into close proximity to the activating light curable liquid on the substrate. An external electric field is applied to the template-substrate interface while maintaining a uniform, carefully controlled gap between the template and substrate. This causes the activating light curable liquid to be attracted to the raised portions of the template. Activating light is applied to the curable liquid while an electric field is applied to the template to create a patterned layer on the substrate.

Abstract: This invention provides a directional ion etching process for making nano-scaled angled features such as may be used, for example, in liquid crystal displays and or nanoimprinting templates. In a particular embodiment a semiconductor wafer substrate is prepared with at least one layer of material. A photoresist is applied, masked, exposed and developed. Anisotropic ion etching at a high angle relative to the wafer is performed to remove portions of the non protected material layer. The remaining photoresist caps shadow at least a portion of the material layer, and as the ion etching is performed at an angle, the protected portions of the material layer also appear at an angle.

Abstract: A method of fabricating a device having a desired non-planar surface or profile and device produced thereby are provided. A silicon wafer is first coated with silicon nitride, patterned, and DRIE to obtain the desired etch profile. Silicon pillars between trenches are then etched using an isotropic wet etch, resulting in a curved well. The wafer is then oxidized to ?2 ?m to smooth the surface of the well, and to protect the well from an ensuing planarization process. The nitride is then selectively removed, and the wafer surface is planarized by removing the Si left in the field regions using either a maskless DRIE or CMP. Finally, the oxide is etched away to produce a wafer with a curved surface.

Abstract: A method of forming a magnetic tunneling junction (MTJ) layer for an MRAM includes sequentially forming a lower material layer, an insulation layer, and an upper material layer on a substrate, forming a mask pattern on a predetermined region of the upper material layer, sequentially removing the upper material layer, the insulation layer, and the lower material layer from around the mask pattern using plasma generated from an etching gas, wherein the etching gas is a mixture of a main gas and an additive gas having a predetermined mixture ratio and including no chlorine (Cl2) gas, and removing the mask pattern. Accordingly, an MTJ layer formed by the method may incur no thermal damage due to high temperature etching, no material deposits due to by-products of etching, and no step difference or corrosion due to chlorine gas, and may have an excellent profile.

Abstract: A new method for fabricating a borderless interconnection in a semiconductor device is provided. During fabrication, the device includes an interlevel dielectric (ILD) layer, a metal silicide layer, and a stop layer disposed between the ILD and metal silicide layers. The stop layer may be formed of silicon nitride or silicon oxynitride, and the metal silicide layer may be a nickel silicide. The method includes etching the ILD layer to expose at least a portion of the stop layer and then performing a nitrogen plasma treatment on the exposed portion of the stop layer. After the treatment, the exposed portion of the stop layer is removed to provide the interconnection hole. Because of the plasma treatment, damage to the metal silicide underlying the stop layer will be minimized when the stop layer is removed.

Abstract: A thin film transistor array panel is provided, which includes: a substrate; a gate electrode; a gate insulating layer formed on the gate electrode; a polysilicon layer formed on the gate insulating layer and including a pair of ohmic contact areas doped with conductive impurity; source and drain electrodes formed on the ohmic contact areas at least in part; a passivation layer formed on the source and the drain electrodes and having a contact hole exposing the drain electrode at least in part; and a pixel electrode formed on the passivation layer and connected to the drain electrode through the contact hole.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is irradiated with UV light, and the remaining photoresist and polymer are stripped with stripping solvents after UV irradiation.

Abstract: A method of etching a multi-layer magnetic stack (e.g., layers of cobalt-iron alloy (CoFe), ruthenium (Ru), platinum-manganese alloy (PtMn), and the like) of a magneto-resistive random access memory (MRAM) device is disclosed. Each layer of the multi-layer magnetic stack is etched using a process sequence including a plasma etch step followed by a plasma treatment step. The plasma treatment step uses a plasma comprising an inert gas to remove residues formed during the plasma etch step.

Abstract: An apparatus and method for removing photoresist from a substrate, which includes treating the photoresist with a first reactant to cause swelling, cracking or delamination of the photoresist, treating the photoresist with a second reactant to chemically alter the photoresist, and subsequently removing the chemically altered photoresist with a third reactant. In one example, the first reactant is supercritical carbon dioxide (SCCO2), the second reactant is ozone vapor, and the third reactant is deionized water.

Abstract: In one implementation, a plasma etching method comprises forming a GexSey chalcogenide comprising layer over a substrate. A mask comprising an organic masking material is formed over the GexSey chalcogenide comprising layer. The mask comprises a sidewall. At least prior to plasma etching the GexSey comprising layer, the sidewall of the mask is exposed to a fluorine comprising material. After exposing, the GexSey chalcogenide comprising layer is plasma etched using the mask and a hydrogen containing etching gas. The plasma etching forms a substantially vertical sidewall of the GexSey chalcogenide comprising layer which is aligned with a lateral outermost extent of the sidewall of the mask.

Abstract: A plasma etching method for improving an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.

Abstract: Method and apparatus for treating a surface of a substrate plate under irradiation of ultraviolet ray emitted from a dielectric barrier discharge lamp. Upon admission into a treating chamber, oxygen is removed from a treating surface and surrounding atmosphere of a substrate plate in order to suppress energy losses of ultraviolet ray to a minimum.

Abstract: A method and apparatus for etching a magnetic memory cell stack are described. More particularly, HCl is used as a main etchant gas for etching a magnetic memory cell stack. HCl is used in part to reduce corrosion and improve selectivity. Additionally, use of an amorphous carbon or hydrocarbon based polymer resin for a hard mask is described, as well as a post-etch passivation with a water rinse, a water vapor plasma treatment or an ammonia plasma treatment. Moreover, in an embodiment, a diffusion barrier layer dispose most of the magnetic memory cell stack is etched with hydrogen and fluorine containing gas in a separate process chambers.

Abstract: A method of through-etching a substrate that is simplified and by which the flow of ions can be kept to be regular during a plasma dry etching process, is provided. According to this method, a buffer layer is formed on a first plane of the substrate, a metal layer is formed on the buffer layer, an etching mask pattern is formed on a second plane opposite to the first plane, and the substrate is through-etched with the etching mask pattern as an etching mask. Preferably, the substrate is formed of a single-crystal silicon, the buffer layer is formed of silicon dioxide, and the metal layer is formed of aluminum.