Abstract: A method for reducing random bit failures of flash memory fabrication processes with an HTO film. The random bit failures are caused by HF acid penetration. The HTO film, which functions as an interface reinforcement layer, is formed on a sacrificial layer and a PL1 layer. With the aid of the HTO film, the flash memory is free of acid-corroded seams.

Abstract: A method of manufacturing a semiconductor device etches a feature on a substrate in accordance with a photoresist mask. The photoresist mask is removed by plasma etching. Laser thermal annealing is performed to vaporize polymer residue created during the stripping of the photoresist mask, and to repair damage to the substrate.

Abstract: A process of etching openings in a dielectric layer includes supporting a semiconductor substrate in a plasma etch reactor, the substrate having a dielectric layer and a patterned photoresist and/or hardmask layer above the dielectric layer; supplying to the plasma etch reactor an etchant gas comprising (a) a fluorocarbon gas (CxFyHz, where x≧1, y≧1, and z≧0), (b) a silane-containing gas, hydrogen or a hydrocarbon gas (CxHy, where x≧1 and y≧4), (c) an optional oxygen-containing gas, and (d) an optional inert gas, wherein the flow rate ratio of the silane-containing gas to fluorocarbon gas is less than or equal to 0.1, or the flow rate ratio of the hydrogen or hydrocarbon gas to fluorocarbon gas is less than or equal to 0.5; energizing the etchant gas into a plasma; and plasma etching openings in the dielectric layer with enhanced photoresist/hardmask to dielectric layer selectivity and/or minimal photoresist distortion or striation.

Abstract: A plasma photoresist hardening technique is provided to improve the etch resistance of a photoresist mask 26. The technique involves the formation of a thin passivation layer 26b on the photoresist mask 26 which substantially slows down the etching rate of the photoresist material 26a. Advantageously, this technique allows preservation of critical dimension features such as via hole openings and transmission lines. The technique hardens the surface of the photoresist film 26 by both chemically and physically bonding halogenated hydrocarbons with cross linked photoresist polymer. This results in a passivation layer 26b which is highly resistant to harsh plasma etch environments.

Abstract: The invention relates to a method useful in removing etch residue from etcher equipment parts. The compositions used are aqueous, acidic compositions containing flouride and polar, organic solvents. The compositions are free of glycols and hydroxyl amine and have a low surface tension and viscosity.

Abstract: A film deposition process for depositing an amorphous metal oxide film, for example, an amorphous tantalum oxide film and a film treatment process for improving film quality of the amorphous tantalum oxide film in the state in which an amorphous state of the amorphous metal oxide film is being maintained by a high-density plasma radiation treatment based upon ion and radical reactions and which contains at least oxygen at an ion current density higher than 5 mA/cm2 are carried out, whereby a low-temperature treatment in the whole process is made possible. In addition, since the amorphous metal oxide film, which is excellent in film quality, can be deposited, the amorphous metal oxide film can be made high in reliability and can be produced inexpensively. The amorphous tantalum oxide film which is excellent in film quality can be manufactured inexpensively by a low-temperature treatment.

Abstract: A method of etching a magnetic material (e.g., nickel-iron alloy (NiFe), cobalt-iron alloy (CoFe), and the like) using a gas mixture comprising a hydrogen halide gas and a fluorocarbon-containing gas is disclosed. The method provides high etch selectivity for the magnetic materials over non-magnetic dielectric materials, such as aluminum oxide (Al2O3) and the like, as well as to photoresist.

Abstract: A method for fabricating a nano-sized diamond whisker includes the steps of depositing a diamond film on a substrate, forming a nano-sized mask pattern on the deposited diamond film, and etching the diamond film by using the nano-sized pattern as an etching mask. The nano-sized diamond whisker can be used as a new field emission cold cathode device, thereby advancing a practical use of a field emission device having high performance, and can also be applied to various fields such as a new composite material and a mechanical device.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device on a first surface of a silicon carbide substrate and with at least one metal contact for the device on the first surface of the substrate. The opposite, second surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished second surface of the silicon carbide substrate to define a predetermined location for a via that is opposite the device metal contact on the first surface; etching the desired via through the desired masked location until the etch reaches the metal contact on the first surface; and metallizing the via to provide an electrical contact from the second surface of the substrate to the metal contact and to the device on the first surface of the substrate.

Abstract: A method of etching high dielectric constant materials using a halogen gas, a reducing gas and an etch rate control gas chemistry.

Abstract: A method for moving resist stripper across the surface of a semiconductor substrate. The method includes applying a wet chemical resist stripper, such as an organic or oxidizing wet chemical resist stripper, to at least a portion of a photomask positioned over the semiconductor substrate. A carrier fluid, such as a gas, is then directed toward the semiconductor substrate so as to move the resist stripper across the substrate. The carrier fluid may be directed toward the substrate as the resist stripper is being applied thereto or following application of the resist stripper. A system for effecting the method is also disclosed.

Abstract: The invention teaches a new method of applying slurry during the process of chemical mechanical polishing of copper surfaces. By varying the rate of slurry deposition, starting out with a low rate of slurry flow that is increased as the polishing process proceeds, the invention obtains good planarity for copper surfaces while saving on the amount of slurry that is being used for the copper surface polishing process.

Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas.

Abstract: The present invention generally relates to a method of forming a graded junction within a semiconductor substrate. A first masking pattern having a first opening characterized by a first lateral dimension is formed over the semiconductor substrate. The semiconductor substrate is doped with a first dopant, using the first masking pattern as a doping mask, thereby forming a first dopant region in the semiconductor substrate underlying the first opening. The first masking pattern is swelled to decrease the first lateral dimension of the first opening to a second lateral dimension. The semiconductor substrate is then doped with a second dopant, using the swelled first masking pattern as a doping mask, thereby forming a second dopant region in the semiconductor substrate, and furthermore defining a graded junction within the semiconductor substrate.

Abstract: A plasma etching apparatus for processing a sample placed within a processing chamber having a sidewall member which is electrically grounded to earth and constitutes at least a portion of the processing chamber and a removable member which constitutes an inner wall surface of the processing chamber. The removable member is thermally conductive and is held on the sidewall member and movable therefrom for removal from the processing chamber. The sample is processed in the processing chamber while controlling a temperature of the removable member.

Abstract: A thermal physical vapor deposition apparatus includes an elongated vapor distributor disposed in a chamber held at reduced pressure, and spaced from a structure which is to receive an organic layer in forming part of an OLED. One or more detachable organic material vapor sources are disposed outside of the chamber, and a vapor transport device including a valve sealingly connects each attached vapor source to the vapor distributor. During vapor deposition of the organic layer, the structure is moved with respect to the vapor distributor to provide an organic layer of improved uniformity on the structure.

Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

Abstract: A process for plasma etching silicon carbide with selectivity to an overlying and/or underlying dielectric layer of material. The dielectric material can comprise silicon dioxide, silicon oxynitride, silicon nitride or various low-k dielectric materials including organic low-k materials. The etching gas includes a chlorine containing gas such as Cl2, an oxygen containing gas such as O2, and a carrier gas such as Ar. In order to achieve a desired selectivity to such dielectric materials, the plasma etch gas chemistry is selected to achieve a desired etch rate of the silicon carbide while etching the dielectric material at a slower rate. The process can be used to selectively etch a hydrogenated silicon carbide etch stop layer or silicon carbide substrate.

Abstract: A method for plasma etching substrates having high open area patterns is described. The method is useful in microelectrical mechanical system (MEMS) applications, and in the fabrication of integrated circuits and other electronic devices. The method can be used to etch strict profile control trenches with 89° +/−1° sidewalls on silicon substrates with high open area patterns such as patterns between about 50% and about 90%. The novel method plasma etches high open area substrates using a plasma formed from a gaseous mixture that includes an oxygen source gas, a fluorine source gas and a fluorocarbon source gas. In an alternative embodiment, the fluorocarbon source gas is a passivation gas. In another alternative embodiment, the fluorocarbon source gas consists essentially of a fluorocarbon having fluorine and carbon in a 2:1 ratio. In another particular embodiment, the oxygen source gas is O2, the fluorine source gas is SF6 and the fluorocarbon source gas is C4F8.

Abstract: A method of manufacturing a semiconductor device (2) on a substrate (1), the semiconductor device including an active area (5, 6, 16) in the substrate (1) demarcated by spacers (10-13,20-23) and arranged so as to contact an interconnect (29) including TiSi2; the method includes: depositing an oxide layer (26) on the substrate (1); depositing and patterning a resist layer (27) on the oxide (26); reactive ion etching of the oxide (26) to demarcate the active area (5, 6, 16), using the patterned resist layer (27); removing the resist (27) by a dry strip plasma containing at least oxygen; depositing titanium (28) on the oxide (26) and the active area (5, 6, 16); forming the interconnect (29) as self-aligned TiSi2 by a first anneal, a selective wet etch, and a second anneal; the dry strip plasma including, as a second gaseous constituent, at least fluoride.

Abstract: A protection device which is active during the manufacturing process of a semiconductor chip includes a protection transistor and an antenna. The protection transistor is connected between a metal line having devices to be protected electrically connected thereto and a ground supply, where the metal line is connected to devices to be protected. The antenna is formed of the same metal layer as the metal line and controls the operation of the protection transistor during the manufacturing process. The antenna is connected to a gate of the protection transistor. Optically, there is a metal ring around the antenna which is connected to a drain of the protection transistor via the same metal layer as the metal line. During normal operation of the chip, the protection transistor is either active for other purposes or is turned off.

Abstract: A method of removing sidewall polymer fence of the dielectric layer, which is a wet strip process using acidic SC1 and CR solutions, and SC1 solution is applied before CR solution. SC1 solution substantially comprises ammonium hydroxide, sulfuric acid and water for removing sidewall polymer fence, and CR solution substantially comprises sulfuric acid and hydrogen peroxide for removing photo-resist. The key of the wet strip process of the invention is that SC1 solution is applied at a low temperature for reducing the oxide loss. The wet strip process of the invention can completely remove the sidewall polymer fence and reduce the oxide loss of the dielectric layer.

Abstract: The present invention provides a method for fabricating a semiconductor device with use of an ArF light source capable of minimizing deformations of a photoresist pattern for ArF during an etching process. Also, when forming the pattern, C5F8 gas is used at a main etching step to compensate etch tolerance of the photoresist for ArF. By controlling process recipe properly, it is possible to minimize pattern deformations as simultaneously as to form a micronized pattern. To compensate the etch tolerance of the photoresist for ArF weaker than that of a photoresist for KrF, the main etching step is divided into three sub-steps, thereby providing a method for minimizing the pattern deformations when duplicating the pattern.

Abstract: A method and apparatus for processing wafers including a chamber defining a plurality of isolated processing regions. The isolated processing regions have an upper end and a lower end. The chamber further includes a plurality of plasma generation devices each disposed adjacent the upper end of each isolated processing region, and one of a plurality of power supplies connected to each plasma generation device. The output frequency of the plurality of power supplies are phase and/or frequency locked together. Additionally, the chamber includes a plurality of gas distribution assemblies. Each gas distribution assembly is disposed within each isolated processing region. A movable wafer support is disposed within each isolated processing region to support a wafer for plasma processing thereon. The movable wafer support includes a bias electrode coupled to a bias power supply configured to control the bombardment of plasma ions toward the movable wafer support.

Abstract: The polishing composition of this invention is useful for chemical-mechanical polishing of substrates containing noble metals such as platinum and comprises up to about 50% by weight of a adjuvant wherein said adjuvant is s elected from a group consisting of a metal-anion compound, a metal-cation compound or mixtures thereof; abrasive particles at about 0.5% to about 55% by weight of the polishing composition; and water-soluble organic additives up to about 10% by weight of the polishing composition. The abrasive particles are selected from the group consisting of alumina, ceria, silica, diamond, germania, zirconia, silicon carbide, boron nitride, boron carbide or mixtures thereof. The organic additives generally improve dispersion of the abrasive particles and also enhance metal removal rates and selectivity for metal removal by stabilizing the pH of the polishing composition and suppressing the dielectric removal rate.

Abstract: A method for forming a low dielectric constant insulator in a monolithic substrate and the dielectric formed by the method. The method includes formation and patterning of a mask on a silicon substrate followed by anisotropic etching of the silicon to provide a dense array of deep holes. Isotropic etching may be used to form a cavity beneath the dense array of holes and coupling to bottoms of the holes. Sides of the holes are then thermally oxidized. A conventional dielectric is then formed, sealing tops of the holes. The conventional dielectric is optionally densified. Conventional chemical-mechanical polishing then planarizes the dielectric and further conventional processing may be carried out on the wafer to form active circuitry together with passive components such as high Q inductors.

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract: In a microwave plasma processing apparatus that uses a radial line slot antenna, abnormal discharges are suppressed and the excitation efficiency of microwave plasma is improved simultaneously. In the joint between the radial line slot antenna and the coaxial waveguide, the point part of the power supplying line of the coaxial waveguide is separated from the slot plate constructing a radiation face.

Abstract: A process enables plasma etching of materials that do not contain silicon. The process is particularly suitable for the side wall passivation of chromium layers in masks for fabricating semiconductor components. The plasma contains oxygen and/or nitrogen, and at least one silicon-donating compound is introduced into the plasma. This allows efficient passivation of side walls.

Abstract: A composite layer comprising a non-homogenous layer is etched by continuously varying a process parameter, such as the amount of reactive agent in an etchant mixture. Embodiments include etching a silicon oxide film having a varying concentration of carbon through the film with an etchant mixture containing a fluorinated organic, oxygen and an inert gas and continuously increasing and/or decreasing the amount of oxygen in the etchant mixture during etching through the silicon oxide film.

Abstract: To provide a plasma etching method that can suppress discharge of active gases that do not contribute to plasma etching into the atmosphere, a plasma etching apparatus 10 is composed of a vacuum chamber 12, a plasma processing section 14, a helium supply section 16, a PFC supply section 18, a switching device 20, and an exhaust opening 22. In the use of the apparatus 10, first, helium is introduced into the vacuum chamber 12 through the switching device 20. Then, while introducing the helium, helium is also discharged from the exhaust opening 22 to set the interior of the vacuum chamber 12 at a specified pressure. When the pressure within the vacuum chamber 12 is stabilized at the specified pressure, plasma is generated within the vacuum chamber 12, and at the same time, helium is switched to carbon tetrafluoride by the switching device 20. As a result, carbon tetrafluoride that does not contribute to the plasma etching is prevented from being discharged into the atmosphere.

Abstract: A pre-cleaning method of a substrate for a semiconductor device includes preparing a chamber, the chamber including a plasma electrode at an outside of the chamber, a power supplying system connected to the plasma electrode, a susceptor in the chamber, and an injector injecting gases into the chamber, equipping a metallic net in the chamber, the metallic net over the susceptor and grounded, disposing a substrate on the susceptor, and injecting a hydrogen gas into the chamber through the injector and supplying radio frequency power to the plasma electrode, thereby removing an oxide layer on the substrate.

Abstract: There is provided a gas exhaustion pipe which is directly connected to a diffusion member which diffuses a process gas and is formed inside an upper electrode which serves as a shower head. A cleaning gas exhaustion line whose one end is constituted by the gas exhaustion pipe is connected to a gas exhaustion line which is connected to a gas exhaustion port and exhausts gas inside a chamber. A cleaning gas supplied from a cleaning gas line is exhausted from the chamber through the inside of the upper electrode.

Abstract: A method of etching silicon using a plasma generated from a gas comprising fluorine (F), oxygen (O), hydrogen (H) and carbon (C).

Abstract: The present invention provides a semiconductor manufacturing method, a plasma processing method and a plasma processing apparatus for generating a plasma in a processing chamber and carrying out processing on material to be processed by using the plasma, comprising a floating-foreign-particle measuring apparatus including: a light radiating optical system for radiating a light having a desired wavelength and completing intensity modulation at a desired frequency to the processing chamber; a scattered-light detecting optical system for separating a component with the desired wavelength from scattered lights obtained from the processing chamber as a result of radiation of the light by the light radiating optical system, for optically receiving the component and for converting the component into a first signal; and a foreign-particle-signal extracting unit which separates a second signal representing foreign particle floating in the plasma or in an area in proximity to the plasma from a third signal obtained by

Abstract: A process for forming a damascene structure includes depositing a bilayer comprising a first dielectric layer and a second dielectric layer onto a substrate, wherein the first layer has a dielectric constant higher than the second layer, and wherein the second layer is selected from a low k dielectric material comprising Si, C, O and H. The multi-step damascene structure is patterned into the dielectric bilayer using highly selective anisotropic reactive ion etching. Photoresist, polymers and post etch residues are removed from the substrate using a plasma ashing process without damaging the underlying dielectric layers.

Abstract: A method of improving plasma processing of a semiconductor wafer by exposing the wafer or the plasma to photons while the wafer is being processed. One embodiment of the method comprises the steps of etching an aluminum layer and, during the etching, exposing the semiconductor wafer containing the aluminum layer to photons that photodesorb copper chloride from the surface of the layer thus improving the etch process performance.

Abstract: A plasma processing apparatus and a method for improving plasma characteristics by controlling the dissociation and ionization in the plasma are described. The method includes providing a flow of precursor gas into a process chamber, and evacuating excess gas from process chamber, disposing a substrate material on a substrate holder in the process chamber, forming a plasma from the precursor gas in a plasma volume within the process chamber and attenuating the plasma in a space surrounding the substrate with a baffle assembly and the substrate holder. The walls of the baffle assembly surround the outside edges and a portion of a surface of the substrate holder opposed to a surface on which the substrate is disposed.

Abstract: There is provided a dry etching method for forming an insulating layer of SiO2 or the like in a desired shape with a substantially infinite selection property with respect to Si3N4 used as an etching stopper. As an etching gas a gas (HI, or a gas having a constitution of CxHyIz) containing iodine in a molecule is added. Here, a mixing ratio (I/C) of iodine to carbon in the etching gas is 0.3≦(I/C)≦1.5. Alternatively, instead of the iodine-containing gas the gas containing chlorine or bromine as the same halogen element is used. Since iodine, chlorine, or bromine contained in the etching gas generates a low vapor pressure material on Si3N4, Si3N4 etching is completely prohibited. Since no low vapor pressure material is generated on SiO2 or SiOF as a material to be etched, a high etching rate can be obtained.

Abstract: We have discovered a method of detecting the approach of an endpoint during the etching of a material within a recess such as a trench or a contact via. The method provides a clear and distinct inflection endpoint signal, even for areas of a substrate containing isolated features. The method includes etching the material in the recess and using thin film interferometric endpoint detection to detect an endpoint of the etch process, where the interferometric incident light beam wavelength is tailored to the material being etched; the spot size of the substrate illuminated by the light beam is sufficient to provide adequate signal intensity from the material being etched; and the refractive index of the material being etched is sufficiently different from the refractive index of other materials contributing to reflected light from the substrate, that the combination of the light beam wavelength, the spot size, and the difference in refractive index provides a clear and distinct endpoint signal.

Abstract: A method of bi-layer top surface imaging, comprising the following steps. A structure having a lower layer formed thereover is provided. An upper silicon-containing photoresist layer is formed upon the lower layer. The upper silicon-containing photoresist layer is selectively exposed to form upper silicon-containing photoresist layer exposed portions. The upper silicon-containing photoresist layer exposed portions and the portions of the lower layer below the upper silicon-containing photoresist layer exposed portions are removed using an O2-free N2/H2 plasma etch.

Abstract: The invention includes methods of forming magnetoresistive devices. In one method, a construction is formed which includes a first magnetic layer, a non-magnetic layer over the first magnetic layer, and a second magnetic layer over the non-magnetic layer. A first pattern is extended through the second magnetic layer and to the non-magnetic layer with an etch selective for the material of the second magnetic layer relative to the material of the non-magnetic layer. A dielectric material is formed over the patterned second magnetic layer, and subsequently a second etch is utilized to extend a second pattern through the non-magnetic layer and at least partway into the first magnetic layer.

Abstract: The invented method involves separately etching the P and N gate features in a dual-poly gate using dual masks, thereby permitting the etching recipes to be tuned to the differentially responsive P and N materials that form the gate.

Abstract: A method of forming a self-aligned contact hole suitable for a semiconductor substrate having a pair of gate electrodes. First, a nitride etching stop layer is formed over the gate electrodes and the semiconductor substrate. Then, an oxide insulating layer is formed on the nitride etching stop layer, Next, the oxide insulating layer is plasma-etched by an etching gas containing C5F8 and CHF3 or C4F6 and CHF3 so as to form a self-aligned contact hole between the pair of gate electrode.

Abstract: A patterned organic masking layer is formed outwardly of a feature layer to be etched. It has at least one feature pattern having a minimum feature dimension of less than or equal to 0.3 micron. The feature layer has a thickness which is to be etched to form the one feature pattern in the feature layer. The feature pattern is plasma etched into the feature layer using the masking layer as a mask. The plasma etching comprises at least one etching segment where at least 30% of said thickness of the feature layer is etched using an etching gas comprising one gas compound comprising carbon, hydrogen and at least one halogen present at greater than or equal to 70% concentration by volume as compared to all carbon, hydrogen and halogen containing gas compounds in the etching gas.

Abstract: A composite layer of dielectric material is first formed over the integrated circuit structure, comprising a thin barrier layer of dielectric material, a layer of low k dielectric material over the barrier layer, and a thin capping layer of dielectric material over the layer of low k dielectric material. A photoresist mask, formed over the capping layer, is baked in the presence of UV light to cross-link the mask material. The composite layer is then etched through the resist mask using an etchant gas mixture including CO, but not oxygen. Newly exposed surfaces of low k dielectric material are then optionally densified to harden them. The resist mask is then removed using a plasma of a neutral or reducing gas. Exposed surfaces of low k dielectric material are then passivated by a low power oxygen plasma. Preferably, optional densification, mask removal, and passivation are all done in the same vacuum apparatus.

Abstract: An etching process for manufacturing deep trenches in silicon layers of semiconductor devices and the resulting structures is described. The etching process makes the trenches using a chlorine-based chemical as the primary etchant, while employing various additives to obtain the desired trench surface conditions, geometry, shape, and uniformity. The etching process obtains the trenches in a single step, decreasing the cost and time for manufacturing. In the future, as requirements for IC components (i.e., capacitors and deep isolation trenches) using trenches become more restrictive, the method and structures of present invention could become an integral part of trench technology.

Abstract: Electrical damage to semiconductor elements in the plasma etching thereof is suppressed. In processing of a fine pattern by plasma etching, the high frequency power supply to be applied to the specimen is turned off before the charge potential at a portion of the pattern reaches the breakdown voltage of the gate oxide film which is interconnected to said fine pattern, and then the high frequency power supply is turned on when the charge potential at the portion of the pattern drops substantially. This on and off control is effected in a repetitive mode of operation.

Abstract: A structure of an amorphous-silicon thin film transistor array comprises a substrate, a gate electrode, a gate insulating layer, an amorphous-silicon active layer, an n+ amorphous-silicon layer and a metal layer. The metal layer defines a source electrode and a drain electrode. The structure simplifies the photolithography process by using a less number of masks to manufacture thin film transistors. It also reduces the occurrence of open circuits in the first metal (MI) layer or short circuits between the MI layer and the second metal (MII) layer caused by the photoresist residue or particle contamination. The manufacturing method combines a conventional back-channel-etched (BCE) reduced mask process and a two-step exposure technology. The two-step exposure technology uses two photoresist pattern masks. One is a pattern mask for complete exposure with higher light intensity and the other is a pattern mask for incomplete exposure with lower light intensity.

Abstract: A method of fabricating integrated circuit wafers, in accordance with this invention comprises the following steps. Provide an integrated circuit wafer having devices formed therein covered with a metal layer and a photoresist layer over the metal layer which is selectively exposed and developed forming a photoresist mask. Introduce the wafer into a multi-chamber system, patterning the metal layer by etching and then exposing the mask to light in a cooled chamber wherein the light is derived from a source selected from a mercury lamp and a laser filtered to remove red and infrared light therefrom before exposure of the wafer thereto. The chamber is cooled by a refrigerant selected from water and liquefied gas? Then remove the wafer, and load it into a photoresist stripping tank to remove the photoresist mask with a wet photoresist stripper. Place the wafer in a batch type plasma chamber after removing the photoresist mask.