Abstract: An etching method comprises etching an oxide layer with a first dc bias of a plasma chamber, removing a photoresist layer with a second dc bias of the plasma chamber and etching through a liner film with a third dc bias of the plasma chamber. In order to reduce the copper deposition on the wall of the plasma chamber, the third dc bias is set to be less than the first and second dc bias.

Abstract: A method of etching an aluminum-containing layer on a substrate is described. The method includes forming plasma from a process composition containing a halogen element, and exposing the substrate to the plasma to etch the aluminum-containing layer. The method may additionally include exposing the substrate to an oxygen-containing environment to oxidize a surface of the aluminum-containing layer and control an etch rate of the aluminum-containing layer. The method may further include forming first plasma from a process composition containing HBr and an additive gas having the chemical formula CxHyRz (wherein R is a halogen element, x and y are equal to unity or greater, and z is equal to zero or greater), forming second plasma from a process composition containing HBr, and exposing the substrate to the first plasma and the second plasma to etch the aluminum-containing layer.

Abstract: A plasma processing method includes modifying a resist pattern of the substrate; and trimming the modified resist pattern through a plasma etching. The modifying includes: supplying the processing gas for modification from the processing gas supply unit to the inside of the processing chamber while the substrate having a surface on which the resist pattern is formed is mounted on the lower electrode; supplying the high frequency power from the high frequency power supply to generate a plasma of the processing gas for modification; and supplying the negative DC voltage from the DC power supply to the upper electrode.

Abstract: A method of etching a substrate is described. In one embodiment, the method includes preparing a mask layer having a pattern formed therein on or above at least a portion of a substrate, etching a feature pattern into the substrate from the pattern in the mask layer using a gas cluster ion beam (GCIB), and controlling a sidewall profile of the feature pattern etched into the substrate by adjusting a beam divergence of the GCIB.

Abstract: A method for performing a selective etching process is described. The method includes preparing a substrate having a silicon layer (Si) and a silicon-germanium (SiGex) layer, and selectively etching the silicon layer relative to the silicon-germanium layer using a dry plasma etching process.

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract: A method of forming an amorphous carbon layer on a substrate in a substrate processing chamber, includes introducing a hydrocarbon source into the processing chamber, introducing argon, alone or in combination with helium, hydrogen, nitrogen, and combinations thereof, into the processing chamber, wherein the argon has a volumetric flow rate to hydrocarbon source volumetric flow rate ratio of about 10:1 to about 20:1, generating a plasma in the processing chamber at a substantially lower pressure of about 2 Torr to 10 Torr, and forming a conformal amorphous carbon layer on the substrate.

Abstract: A processing system having a chamber for in-situ optical interrogation of plasma emission to quantitatively measure normalized optical emission spectra is provided. The processing chamber includes a confinement ring assembly, a flash lamp, and a set of quartz windows. The processing chamber also includes a plurality of collimated optical assemblies, the plurality of collimated optical assemblies are optically coupled to the set of quartz windows. The processing chamber also includes a plurality of fiber optic bundles. The processing chamber also includes a multi-channel spectrometer, the multi-channel spectrometer is configured with at least a signal channel and a reference channel, the signal channel is optically coupled to at least the flash lamp, the set of quartz windows, the set of collimated optical assemblies, the illuminated fiber optic bundle, and the collection fiber optic bundle to measure a first signal.

Abstract: Methods for bevel edge etching are provided. One example method is for etching a film on a bevel edge of a substrate in a plasma etching chamber. The method includes providing the substrate on a substrate support in the plasma etching chamber. The plasma etching chamber has a top edge electrode and a bottom edge electrode disposed to surround the substrate support. Then flowing an etching process gas through a plurality of edge gas feeds disposed along a periphery of the gas delivery plate. The periphery of the gas deliver plate is oriented above the substrate support and the bevel edge of the substrate, and the flowing is further directed to a space between the top edge electrode and bottom edge electrode. And, flowing a tuning gas through a center gas feed of the gas delivery plate.

Abstract: A wafer is mounted on the top surface of the stage having an electrostatic chuck function, and the wafer at 50° C. or more is cooled to a temperature lower than 50° C. In this step, the voltage to be applied to the internal electrode provided in the stage is raised stepwise to gradually increase the contact area between the back surface of the wafer and the top surface of the stage. Finally, a chuck voltage is applied to the internal electrode, so that the entire back surface of the wafer is uniformly attracted to the top surface of the stage. This reduces damage occurring in the top surface of the stage due to rubbing between the back surface of the wafer and the top surface of the stage.

Abstract: A method of forming a line/space pattern includes forming a plurality of first pattern structures on a layer of hard mask material disposed on a substrate, forming a plurality of second pattern structures along sidewalls of the first pattern structures, removing the first pattern structures such that the second pattern structures stand alone on the layer of hard mask material, forming a first mask that exposes a location where a space of the line/space pattern to be formed is to have a width greater than the distance between adjacent ones of the second pattern structures, removing those of the second pattern structures which are exposed by the first mask such that others of the second pattern structures remain on the layer of hard mask material, forming a second mask that covers a location where a line of the line/space pattern to be formed is to have a width that is greater than the widths of the second pattern structures, forming a hard mask by etching the hard mask material layer using the second mask and

Abstract: A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench.

Abstract: A substrate can be appropriately oxidized, while oxidation of the substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen(O2) or oxygen/containing gas supplied to a processing chamber to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the processing chamber to form a plasma discharge, and processing the substrate by the hydrogen plasma.

Abstract: Disclosed is a means for stabilizing quality of a semiconductor device by preventing projections from being formed in the bottom of a through hole. A method of manufacturing a semiconductor device includes a process of forming a through hole reaching a metal nitride layer through an interlayer insulating layer on a semiconductor wafer on which the wiring layer, the metal nitride layer formed on the wiring layer, and the interlayer insulating layer covering the wiring layer and the metal nitride layer are formed. The through hole forming process includes: a first etching step of etching the interlayer insulating layer by an anisotropic etching method with the semiconductor wafer set to a first temperature; and a second etching step of etching an upper surface of metal nitride layer by an anisotropic etching method with the semiconductor wafer set to a second temperature higher than the first temperature.

Abstract: A method of processing a workpiece in a plasma reactor having an electrostatic chuck for supporting the workpiece within a reactor chamber, the method including circulating a coolant through a refrigeration loop that includes an evaporator inside the electrostatic chuck, while pressurizing a workpiece-to-chuck interface with a thermally conductive gas, sensing conditions in the chamber including temperature near the workpiece and simulating heat flow through the electrostatic chuck in a thermal model of the chuck based upon the conditions.

Abstract: A plasma etching apparatus includes a vacuum processing chamber; a lower electrode, i.e., a mounting table for mounting the substrate, provided in the vacuum processing chamber; an upper electrode provided to face the lower electrode; a gas supply unit for supplying a processing gas to the vacuum processing chamber; a high frequency power supply unit for supplying a high frequency power to the lower electrode; and a focus ring provided on the lower electrode to surround a periphery of the substrate. In a method for performing a plasma etching on a substrate by using the plasma etching apparatus, a plasma is generated in the vacuum processing chamber to perform the plasma etching on the substrate by using the plasma after the focus ring is heated by supplying a high frequency power from the high frequency power supply unit to the lower electrode under a condition that no plasma is generated.

Abstract: A method for fabricating a semiconductor structure is disclosed. The method includes the steps of: providing a substrate; depositing a material layer on the substrate; forming at least one dielectric layer on the material layer; forming a patterned resist on the dielectric layer; performing a first trimming process on at least the patterned resist; performing a second trimming process on at least the dielectric layer; and using the dielectric layer as mask for etching the material layer.

Abstract: A plasma etching method that can increase the selection ratio of a stop layer to an interlayer insulation film. The plasma etching method is carried out on a substrate that has the interlayer insulation film formed of CwFx (x and w are predetermined natural numbers) and a stop layer that stops etching and is exposed at the bottom of a hole or a trench formed in the interlayer insulation film. The interlayer insulation film and the stop layer are exposed at the same time to plasma generated from CyFz (y and z are predetermined natural numbers) gas and hydrogen-containing gas.

Abstract: The invention can provide apparatus and methods of processing a substrate using plasma generation by gravity-induced gas-diffusion separation techniques. By adding or using gases including inert and process gases with different gravities (i.e., ratio between the molecular weight of a gaseous constituent and a reference molecular weight), a two-zone or multiple-zone plasma can be formed, in which one kind of gas can be highly constrained near a plasma generation region and another kind of gas can be largely separated from the aforementioned gas due to differential gravity induced diffusion and is constrained more closer to a wafer process region than the aforementioned gas.

Abstract: A significantly improved low-k dielectric patterning method is described herein using plasma comprising an oxygen radical source and a silicon source to remove the photo-resist layer.

Abstract: A semiconductor substrate processing system includes a chamber that includes a processing region and a substrate support. The system includes a top plate assembly disposed within the chamber above the substrate support. The top plate assembly includes first and second sets of plasma microchambers each formed into the lower surface of the top plate assembly. A first network of gas supply channels are formed through the top plate assembly to flow a first process gas to the first set of plasma microchambers to be transformed into a first plasma. A set of exhaust channels are formed through the top plate assembly. The second set of plasma microchambers are formed inside the set of exhaust channels. A second network of gas supply channels are formed through the top plate assembly to flow a second process gas to the second set of plasma microchambers to be transformed into a second plasma.

Abstract: A method of actuating a semiconductor device includes providing a transistor. The transistor includes a substrate. A first electrically conductive material layer is positioned on the substrate. A second electrically conductive material layer is in contact with and positioned on the first electrically conductive material layer. The second electrically conductive material layer includes a reentrant profile. The second electrically conductive material layer also overhangs the first electrically conductive material layer. An electrically insulating material layer is conformally positioned over the second electrically conductive material layer, the first electrically conductive material layer, and at least a portion of the substrate. A semiconductor material layer conforms to and is in contact with the electrically insulating material layer. A third electrically conductive material layer is nonconformally positioned over and in contact with a first portion of the semiconductor material layer.

Abstract: The present disclosure provides a method for making metal gate stacks of a semiconductor device. The method includes applying a first dry etching process to a semiconductor substrate in an etch chamber through openings of a patterned mask layer defining gate regions, removing a polysilicon layer and a metal gate layer on the semiconductor substrate; applying a H2O steam to the semiconductor substrate in the etch chamber, removing a capping layer on the semiconductor substrate; applying a second dry etching process to the semiconductor substrate in the etch chamber, removing a high k dielectric material layer; and applying a wet etching process to the semiconductor substrate to remove polymeric residue.

Abstract: The present invention is a plasma etching method comprising: a cleaning step (a) in which a cleaning gas is supplied into a processing vessel and the cleaning gas is made plasma, so that a deposit adhering to an inside of the processing vessel is removed by means of the plasma; a film depositing step (b), succeeding the cleaning step (a), in which a film depositing gas containing carbon and fluorine is supplied into the processing vessel and the film depositing gas is made plasma, so that a film containing carbon and fluorine is deposited on the inside of the processing vessel by means of the plasma; an etching step (c), succeeding the film depositing step (b), in which a substrate is placed on a stage inside the processing vessel, and an etching gas is supplied into the processing vessel and the etching gas is made plasma, so that the substrate is etched by means of the plasma; and an unloading step (d), succeeding the etching step (c), in which the substrate is unloaded from the processing vessel; wherein,

Abstract: Embodiments of the invention relate to a substrate etching method and apparatus. In one embodiment, a method for etching a substrate in a plasma etch reactor is provided that includes a) depositing a polymer on a substrate in an etch reactor, b) etching the substrate using a gas mixture including a fluorine-containing gas and oxygen in the etch reactor, c) etching a silicon-containing layer the substrate using a fluorine-containing gas without mixing oxygen in the etch reactor, and d) repeating a), b) and c) until an endpoint of a feature etched into the silicon-containing layer is reached.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing an etcher having an electrostatic chuck (ESC); and placing the wafer on the ESC. The wafer includes a conductive feature and a dielectric layer over the conductive feature. The method further includes forming and patterning a photo resist over the wafer; and etching the dielectric layer to form a via opening in the wafer using the etcher. An ashing is performed to the photo resist to remove the photo resist. An oxygen neutralization is performed to the wafer. A de-chuck step is performed to release the wafer from the ESC.

Abstract: In a dry etching method, a silicon substrate is mounted on an electrode arranged in a processing chamber; a plasma is generated by discharging an etching gas in the processing chamber; a radio frequency power for attracting ions from the plasma is supplied to the electrode; and the silicon substrate is etched by the plasma. A pressure inside the processing chamber is set as 1 mTorr to 100 mTorr, and the etching is carried out while satisfying the following equation: yM?2.84*10?3x+0.28, where yM is a power density of the radio frequency power per unit area of the electrode and x is the pressure inside the processing chamber.

Abstract: A selective self-aligned dual patterning method. The method includes performing a single lithography operation to form a patterned mask having a narrow feature in a region of a substrate that is to a have pitch-reduced feature and a wide feature in a region of the substrate that is to have a non-pitch-reduced feature. Using the patterned mask, a template mask is formed with a first etch and the patterned mask is then removed from the narrow feature while being retained over the wide feature. The template mask is then thinned with a second etch to introduce a thickness delta in the template mask between the narrow and wide features. A spacer mask is then formed and the thinned narrow template mask is removed to leave a pitch double spacer mask while the thick wide template mask feature is retained to leave a non-pitch reduced mask.

Abstract: A main etching step is effected in a state shown in FIG. 1A under a first pressure using a gas containing at least HBr, e.g., a mixture gas of HBr and Cl2 as an etching gas. The main etching is ended before a silicon oxide film 102, as shown in FIG. 1B, is exposed. An over-etching process is effected under a second pressure higher than the first pressure using a gas containing at least HBr, e.g., an HBr single gas so as to completely expose the silicon oxide film 102 as shown in FIG. 1C. In such a way, the selectivity of a silicon-containing conductive layer with respect to the silicon oxide film is improved compared to conventional methods. Without etching the silicon oxide film layer, which is an underlying layer, and without marring the shape of the silicon-containing conductive film layer formed by etching, only the desired silicon-containing conductive film layer is removed by etching reliably.

Abstract: In a plasma processing chamber, a method and an arrangement to stabilize pressure are provided. The method includes providing coarse pressure adjustments in an open-loop manner and thereafter providing fine pressure adjustments in a closed-loop manner. The coarse pressure adjustments are performed by rapidly re-position confinement rings employing an assumed linear relationship between the conductance and the confinement rings position to bring the pressure in the plasma generating region quickly to roughly a desired set point. The fine pressure adjustments are performed by at least employing mechanical vacuum pump(s), turbo pump(s), confinement ring positioning and/or combinations thereof to achieve a derive pressure set point.

Abstract: Gas mixtures which comprise acids like HF, HCl or HBr and other constituents, especially gas mixtures which comprise or consist of carboxylic acid fluorides, C(O)F2 or phosphorous pentafluoride and HCl and optionally HF, can be separated by ionic liquids. The process is performed reversibly. Ionic liquids are applied the anion of which corresponds to a stronger acid than the acid to be removed. Highly purified products, for example, highly purified carbonyl fluoride can be obtained.

Abstract: A method for etching features in a silicon layer is provided. A hard mask layer is formed over the silicon layer. A photoresist layer is formed over the hard mask layer. The hard mask layer is opened. The photoresist layer is stripped by providing a stripping gas; forming a plasma with the stripping gas by providing a high frequency RF power and a low frequency RF power, wherein the low frequency RF power has a power less than 50 watts; and stopping the stripping gas when the photoresist layer is stripped. The opening the hard mask layer and the stripping the photoresist layer are performed in a same chamber.

Abstract: A method for forming a hole pattern includes forming a hard mask layer for a hole pattern over an etch target layer, forming pillar patterns having a gap therebetween over the hard mask layer for a hole pattern, forming spacer patterns on sidewalls of the pillar patterns, removing the pillar patterns between the spacer patterns, and etching the hard mask layer for a hole pattern by using the spacer patterns as etch barriers.

Abstract: Plasma confinement ring assemblies are provided that include confinement rings adapted to reach sufficiently high temperatures on plasma-exposed surfaces of the rings to avoid polymer deposition on those surfaces. The plasma confinement rings include thermal chokes adapted to localize heating at selected portions of the rings that include the plasma exposed surfaces. The thermal chokes reduce heat conduction from those portions to other portions of the rings, which causes selected portions of the rings to reach desired temperatures during plasma processing.

Abstract: A method of forming an integrated circuit structure on a wafer includes providing a first etcher comprising a first electrostatic chuck (ESC); placing the wafer on the first ESC; and forming a via opening in the wafer using the first etcher. After the step of forming the via opening, a first reverse de-chuck voltage is applied to the first ESC to release the wafer. The method further includes placing the wafer on a second ESC of a second etcher; and performing an etching step to form an additional opening in the wafer using the second etcher. After the step of forming the additional opening, a second reverse de-chuck voltage is applied to the second ESC to release the wafer. The second reverse de-chuck voltage is different from the first reverse de-chuck voltage.

Abstract: There is provided a plasma etching method for forming a hole in a silicon oxide film formed on an etching stopper layer. The plasma etching method includes a main etching process for etching the silicon oxide film; and an etching process that is performed when at least a part of the etching stopper layer is exposed after the main etching process. The etching process includes a first etching process using a gaseous mixture of a C4F6 gas, an Ar gas and an O2 gas as the processing gas; and a second etching process using a gaseous mixture of a C4F8 gas, an Ar gas and an O2 gas or a gaseous mixture of a C3F8 gas, an Ar gas and an O2 gas as the processing gas. The first etching process and the second etching process are alternately performed plural times.

Abstract: A substrate plasma processing apparatus includes a chamber of which an interior is evacuated under a predetermined vacuum condition; an RF electrode which is disposed in the chamber and configured so as to hold a substrate to be processed on a main surface thereof; an opposing electrode which is disposed opposite to the RF electrode in the chamber; an RF voltage applying device for applying an RF voltage with a predetermined frequency to the RF electrode; and a pulsed voltage applying device for applying a pulsed voltage to the RF electrode so as to be superimposed with the RF voltage and which includes a controller for controlling a timing in application of the pulsed voltage and defining a pause period of the pulsed voltage.

Abstract: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.

Abstract: A method of forming a seed layer of an interconnect structure includes forming a dielectric layer; forming an opening in the dielectric layer; performing a first deposition step to form the seed layer; and in-situ performing a first etch step to remove a portion of the seed layer. The method may further includes additional deposition and etch steps for forming the seed layer.

Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.

Abstract: A processing method is provided for plasma etching features in a silicon nitride (SiN) film covered by a mask pattern.

Abstract: A plasma etching method includes disposing a first electrode and a second electrode to face each other; preparing a part in the processing chamber; supporting a substrate; vacuum-evacuating the processing chamber; supplying an etching gas into a processing space between the first electrode and the second electrode; generating a plasma of the etching gas in the processing space by applying a radio wave power to the first electrode or the second electrode; and etching a film to be processed on a surface of the substrate by using the plasma. Further, a DC voltage is applied to the part during the etching process, the part being disposed away from the substrate and being etched by reaction with reactant species in the plasma.

Abstract: A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.

Abstract: A gas distribution assembly for the ceiling of a plasma reactor includes a center fed hub and an equal path length distribution gas manifold underlying the center fed hub.

Abstract: A semiconductor substrate having an etch stop layer and at least a dielectric layer disposed from bottom to top is provided. The dielectric layer and the etching stop layer is then patterned to form a plurality of openings exposing the semiconductor substrate. A dielectric thin film is subsequently formed to cover the dielectric layer, the sidewalls of the openings, and the semiconductor substrate. The dielectric thin film disposed on the dielectric layer and the semiconductor substrate is then removed while the dielectric thin film disposed on the sidewalls remains.

Abstract: A method of pattern etching a Si-containing anti-reflective coating (ARC) layer is described. The method comprises etching a feature pattern into the silicon-containing ARC layer using plasma formed from a process gas containing SF6 and a hydrocarbon gas. The method further comprises adjusting a flow rate of the hydrocarbon gas relative to a flow rate of the SF6 to reduce a CD bias between a final CD for nested structures in the feature pattern and a final CD for isolated structures in the feature pattern.

Abstract: In a substrate processing method of processing a substrate that includes an oxide layer as a mask layer and a silicon layer as a target layer to be processed, the silicon layer is etched while depositing a deposit on a surface of the oxide layer by a plasma generated from a mixed gas of a fluorine-based gas, a bromine-based gas, O2 gas, and SiCl4 gas to secure a thickness of the mask layer.

Abstract: Methods and arrangements for controlling the electron loss to the upper electrode, including techniques and apparatus for biasing the upper electrode more negatively to allow charged species to be trapped within the plasma chamber for a longer period of time, thereby increasing the plasma density may be increased. The induced RF signal on the upper electrode is rectified, thus biasing the upper electrode more negatively. The rectified RF signal may also be amplified, thus driving the upper electrode even more negatively, if desired.

Abstract: A method in a plasma processing system for etching a feature through a given layer on a semiconductor substrate. The method includes placing the substrate in a plasma processing chamber of the plasma processing system. The method also includes flowing an etchant gas mixture into the plasma processing chamber, the etchant gas mixture being configured to etch the given layer. The method additionally includes striking a plasma from the etchant source gas. Furthermore, the method includes etching the feature at least partially through the given layer while applying a bias RF signal to the substrate, the bias RF signal having a bias RF frequency of between about 45 MHz and about 75 MHz. The bias RF signal further has a bias RF power component that is configured to cause the etch feature to be etched with an etch selectivity to a second layer of the substrate that is higher than a predefined selectivity threshold.

Abstract: A method for patterning a multilayered conductor/substrate structure includes the steps of: providing a multilayered conductor/substrate structure which includes a plastic substrate and at least one conductive layer overlying the plastic substrate; and irradiating the multilayered conductor/substrate structure with ultraviolet radiation such that portions of the at least one conductive layer are ablated therefrom. In a preferred embodiment, a projection-type excimer laser system is employed to rapidly and precisely ablate a pattern from a mask into the at least one conductive layer. Preferably, the excimer laser is controlled in consideration of how well the at least one conductive layer absorbs radiation at particular wavelengths. Preferably, a fluence of the excimer laser is controlled in consideration of an ablation threshold level of at least one conductive layer.