With Substrate Heating Or Cooling Patents (Class 438/715)
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Patent number: 12087593Abstract: The present disclosure provides a method of plasma etching including the following operations. A wafer and a nitride layer disposed on the wafer are received. An annular conduit is disposed above an edge portion of the nitride layer, in which the annular conduit has a plurality of holes facing the edge portion of the nitride layer. A plasma is sprayed onto an upper surface of the nitride layer. An unsaturated fluorocarbon is sprayed from the holes of the annular conduit to the edge portion of the nitride layer.Type: GrantFiled: June 15, 2022Date of Patent: September 10, 2024Assignee: NANYA TECHNOLOGY CORPORATIONInventor: Shih Pin Kuo
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Patent number: 12020948Abstract: Provided are methods of manufacturing integrated circuit that include a polysilicon etch process in which the wafer having an etch poly pattern is loaded into a reactor chamber and exposed to an activated etchant and, during the etch process, adjusting the temperature conditions within the reactor chamber to increase polymeric deposition on an upper surface of the wafer.Type: GrantFiled: July 16, 2021Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yun-Jui He, Chih-Teng Liao
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Patent number: 11926893Abstract: Described herein is a technique capable of suppressing generation of particles by removing by-products in a groove of a high aspect ratio. According to one aspect of the technique, there is provided a substrate processing apparatus including: a process chamber in which a substrate is processed; and a substrate support provided in the process chamber and including a plurality of supports where the substrate is placed, wherein the process chamber includes a process region where a process gas is supplied to the substrate and a purge region where the process gas above the substrate is purged, and the purge region includes a first pressure purge region to be purged at a first pressure and a second pressure purge region to be purged at a second pressure higher than the first pressure.Type: GrantFiled: September 9, 2022Date of Patent: March 12, 2024Assignee: Kokusai Electric CorporationInventors: Naofumi Ohashi, Tetsuaki Inada
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Patent number: 11894228Abstract: Exemplary methods of semiconductor processing may include forming a plasma of a carbon-containing precursor in a processing region of a semiconductor processing chamber. The methods may include depositing a carbon-containing material on a substrate housed in the processing region of the semiconductor processing chamber. The methods may include halting a flow of the carbon-containing precursor into the processing region of the semiconductor processing chamber. The methods may include contacting the carbon-containing material with plasma effluents of an oxidizing material. The methods may include forming volatile materials from a surface of the carbon-containing material.Type: GrantFiled: August 26, 2021Date of Patent: February 6, 2024Assignee: Applied Materials, Inc.Inventors: Sudha S. Rathi, Ganesh Balasubramanian, Nagarajan Rajagopalan, Abdul Aziz Khaja, Prashanthi Para, Hiral D. Tailor
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Patent number: 11869795Abstract: Exemplary substrate support assemblies may include a chuck body defining a substrate support surface. The substrate support surface may define a plurality of protrusions that extend upward from the substrate support surface. The substrate support surface may define an annular groove and/or ridge. A subset of the plurality of protrusions may be disposed within the annular groove and/or ridge. The substrate support assemblies may include a support stem coupled with the chuck body.Type: GrantFiled: July 9, 2021Date of Patent: January 9, 2024Assignee: Applied Materials, Inc.Inventors: Saketh Pemmasani, Akshay Dhanakshirur, Mayur Govind Kulkarni, Madhu Santosh Kumar Mutyala, Hang Yu, Deenesh Padhi
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Patent number: 11827975Abstract: The present invention provides a photoplasma etching device and a method of manufacturing the same, and more particularly to a member for a plasma etching device, which is improved in plasma resistance through deposition of a rare-earth metal thin film and surface heat treatment and the optical transmittance of which is maintained, thus being useful as a member for analyzing the end point of an etching process, and a method of manufacturing the same.Type: GrantFiled: July 17, 2018Date of Patent: November 28, 2023Assignee: KOMICO LTD.Inventors: Hyunchul Ko, Suntae Kim, Donghun Jeong
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Patent number: 11380554Abstract: A method and system for the dry removal of a material on a microelectronic workpiece are described. The method includes receiving a workpiece having a surface exposing a target layer to be at least partially removed, placing the workpiece on a workpiece holder in a dry, non-plasma etch chamber, and selectively removing at least a portion of the target layer from the workpiece. The selective removal includes operating the dry, non-plasma etch chamber to perform the following: exposing the surface of the workpiece to a chemical environment at a first setpoint temperature in the range of 35 degrees C. to 100 degrees C. to chemically alter a surface region of the target layer, and then, elevating the temperature of the workpiece to a second setpoint temperature at or above 100 degrees C. to remove the chemically treated surface region of the target layer.Type: GrantFiled: February 11, 2020Date of Patent: July 5, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Subhadeep Kal, Nihar Mohanty, Angelique D. Raley, Aelan Mosden, Scott W. Lefevre
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Patent number: 11162174Abstract: The present disclosure relates to an apparatus and a method of delivering a liquid to a downstream process. The apparatus can include a vessel configured to retain a liquid, a bellow in fluid communication with the vessel to receive the liquid from the vessel and in fluid communication with the downstream process to deliver the liquid. The bellow can be exposed to a constant external pressure and configured to deliver the liquid under the constant external pressure when the bellow stops receiving the liquid from the vessel. In some embodiments, the constant external pressure is atmospheric pressure. The bellow can include a pressure deformable material. The apparatus can further include a vaporizer configured to receive the liquid and to produce a vapor, one or more chemical vapor deposition chambers configured to receive the vapor and to hold a substrate for deposition of a component of the vapor on a substrate.Type: GrantFiled: September 20, 2018Date of Patent: November 2, 2021Assignee: Taiwan Semiconductor Manufacturing Co, Ltd.Inventors: Hsin-Lung Yang, Chui-Ya Peng, Chih-Ta Kuan
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Patent number: 10914005Abstract: A technique that improves a quality of substrate processing. A substrate processing apparatus includes: a plurality of processing chambers and transfer chambers; a vacuum transfer chamber; a plurality of gate valves; a plurality of first gas supply units to supply an inert gas to a substrate; a transfer robot; and a control unit to control the plurality of first gas supply units and the transfer robot to: supply the inert gas to the substrate at a first flow rate when a distance between a gas supply port and the substrate passing through the plurality of gate valves is a first distance; and supply the inert gas to the substrate at a second flow rate greater than the first flow rate when the distance between the gas supply port and the substrate is a second distance greater than the first distance when the substrate passes through the plurality of gate valves.Type: GrantFiled: September 25, 2018Date of Patent: February 9, 2021Assignee: KOKUSAI ELECTRIC CORPORATIONInventor: Takashi Yahata
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Patent number: 10866516Abstract: A photoresist layer is coated over a wafer. The photoresist layer includes a metal-containing material. An extreme ultraviolet (EUV) lithography process is performed to the photoresist layer to form a patterned photoresist. The wafer is cleaned with a cleaning fluid to remove the metal-containing material. The cleaning fluid includes a solvent having Hansen solubility parameters of delta D in a range between 13 and 25, delta P in a range between 3 and 25, and delta H in a range between 4 and 30. The solvent contains an acid with an acid dissociation constant less than 4 or a base with an acid dissociation constant greater than 9.Type: GrantFiled: November 15, 2016Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: An-Ren Zi, Joy Cheng, Ching-Yu Chang
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Patent number: 10734243Abstract: In an etching method for removing a processing target layer formed on a substrate for manufacturing electronic devices, a first break-through process of removing an oxide film formed on a surface of the processing target layer is performed, and a first main etching process of etching the processing target layer is performed after the first break-through process. Then, a second break-through process of removing the oxide film exposed after the first main etching process is performed, and a second main etching process of etching the processing target layer is performed after the second break-through process.Type: GrantFiled: December 13, 2017Date of Patent: August 4, 2020Assignee: TOKYO ELECTRON LIMITEDInventors: Tsuhung Huang, Jun Lin, Takehiko Orii
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Patent number: 10683867Abstract: A vacuum valve connected to a vacuum pump, comprises: a valve plate to be openably/closably driven; a drive section configured to openably/closably drive the valve plate; a signal input section to which a pump information signal indicating an operation state of the vacuum pump is input; and a valve control section configured to control operation of the valve plate based on the input pump information signal.Type: GrantFiled: January 6, 2018Date of Patent: June 16, 2020Assignee: Shimadzu CorporationInventors: Masaya Nakamura, Junichiro Kozaki, Atsuo Nakatani, Nobuyuki Hirata
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Patent number: 10622205Abstract: There is provided a substrate processing method for removing an oxide film formed on a surface of a substrate. The method includes (a) transforming the oxide film into a reaction by-product by supplying a halogen element-containing gas and a basic gas to the substrate accommodated in a processing chamber; and (b) sublimating the reaction by-product to remove the reaction by-product from the substrate by stopping the supply of the halogen element-containing gas into the processing chamber and supplying an inert gas into the processing chamber. The steps (a) and (b) are repeated a plurality of times.Type: GrantFiled: February 16, 2016Date of Patent: April 14, 2020Assignee: Tokyo Electron LimitedInventors: Hiroyuki Takahashi, Tomoaki Ogiwara, Takuya Abe, Masahiko Tomita, Jiro Katsuki
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Patent number: 10573518Abstract: A method of performing a film formation on target substrates in a state where a substrate holder for holding the target substrates in a shelf shape is loaded into a vertical reaction container from a lower opening thereof and the lower opening is closed by a lid. The method includes: performing the film formation on the target substrates by supplying a processing gas into the reaction container; opening the lid and unloading the substrate holder from the reaction container; performing the film formation on a bottom portion of the reaction container including an inner surface of the lid by closing the lower opening with the lid and supplying a coating gas different from the processing gas into the reaction container; and performing the film formation on the target substrates by opening the lid, loading the substrate holder into the reaction container, and supplying the processing gas into the reaction container.Type: GrantFiled: March 23, 2018Date of Patent: February 25, 2020Assignee: TOKYO ELECTRON LIMITEDInventor: Yoshikazu Furusawa
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Patent number: 10428441Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.Type: GrantFiled: June 19, 2017Date of Patent: October 1, 2019Assignee: APPLIED MATERIALS, INC.Inventors: Christopher S. Olsen, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
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Patent number: 10400775Abstract: A vacuum valve attached to a vacuum pump configured to generate regenerative power to perform a stop operation upon blackout, comprises: a first power input section to which power is input from a commercial power source; a second power input section to which the regenerative power generated at the vacuum pump is input; and a valve source circuit to which the power input to each of the first and second power input sections is supplied. When the power from the commercial power source is supplied to the first power input section, the vacuum valve is operated by the supplied power, and when the power from the commercial power source is stopped, the vacuum valve is operated by the regenerative power.Type: GrantFiled: January 6, 2018Date of Patent: September 3, 2019Assignee: Shimadzu CorporationInventors: Masaya Nakamura, Junichiro Kozaki, Atsuo Nakatani, Nobuyuki Hirata
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Patent number: 10395944Abstract: Methods and apparatuses for filling features with metal materials such as tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a metal such as a tungsten-containing material followed by removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ratio feature. The portion may be removed by exposing the tungsten-containing material to a plasma generated from a fluorine-containing nitrogen-containing gas and pulsing and/or ramping the plasma during the exposure.Type: GrantFiled: May 1, 2018Date of Patent: August 27, 2019Assignee: Lam Research CorporationInventors: Waikit Fung, Liang Meng, Anand Chandrashekar
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Patent number: 10381237Abstract: An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is ?35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process.Type: GrantFiled: May 11, 2018Date of Patent: August 13, 2019Assignee: Tokyo Electron LimitedInventors: Ryohei Takeda, Sho Tominaga, Yoshinobu Ooya
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Patent number: 10325781Abstract: A method for etching a titanium nitride film includes a first process of supplying reactive species, which include hydrogen and fluorine, to a base material including a titanium nitride film on at least a part of a surface, and a second process of vacuum-heating the base material to remove the surface reaction layer that is generated on the surface of the titanium nitride film in the first process.Type: GrantFiled: September 8, 2017Date of Patent: June 18, 2019Assignee: Hitachi High-Technologies CorporationInventors: Kazunori Shinoda, Satoshi Sakai, Masaru Izawa, Nobuya Miyoshi, Hiroyuki Kobayashi, Yutaka Kouzuma, Kenji Ishikawa, Masaru Hori
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Patent number: 10297458Abstract: Embodiments of the present technology may include a method of etching. The method may include mixing plasma effluents with a gas in a first section of a chamber to form a first mixture. The method may also include flowing the first mixture to a substrate in a second section of the chamber. The first section and the second section may include nickel plated material. The method may further include reacting the first mixture with the substrate to etch a first layer selectively over a second layer. In addition, the method may include forming a second mixture including products from reacting the first mixture with the substrate.Type: GrantFiled: August 7, 2017Date of Patent: May 21, 2019Assignee: Applied Materials, Inc.Inventors: Dongqing Yang, Tien Fak Tan, Peter Hillman, Lala Zhu, Nitin K. Ingle, Dmitry Lubomirsky, Christopher Snedigar, Ming Xia
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Patent number: 9997374Abstract: An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is ?35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process.Type: GrantFiled: December 12, 2016Date of Patent: June 12, 2018Assignee: Tokyo Electron LimitedInventors: Ryohei Takeda, Sho Tominaga, Yoshinobu Ooya
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Patent number: 9666446Abstract: An etching method includes generating a plasma from a hydrogen-containing gas and a fluorine-containing gas with high-frequency electric power for plasma generation. A first film including a silicon oxide film and a silicon nitride film is etched with the generated plasma in an environment at a temperature lower than or equal to ?30° C. The first etch rate of first etching that etches the first film and the second etch rate of second etching that etches a second film having a structure different from the structure of the first film are controlled, so that the difference between the first etch rate and the second etch rate is within ±20% of the first etch rate.Type: GrantFiled: April 18, 2016Date of Patent: May 30, 2017Assignee: Tokyo Electron LimitedInventors: Sho Tominaga, Wataru Takayama, Yoshiki Igarashi
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Patent number: 9653316Abstract: Disclosed is a plasma processing method which includes a gas supplying process, a power supplying process, and an etching process. In the gas supplying process, a processing gas is supplied into a processing container in which an object to be processed is disposed. In the power supplying process, a plasma generating power of a frequency ranging from about 100 MHz to about 150 MHz as a power for generating plasma of the processing gas supplied into the processing container, and a biasing power which is a power having a frequency lower than that of the plasma generating power are supplied. In the etching process, the object to be processed is etched by the plasma of the processing gas while the biasing power is pulse-modulated so that the duty ratio ranges from about 10% to about 70% and the frequency ranges from about 5 kHz to about 20 kHz.Type: GrantFiled: February 18, 2014Date of Patent: May 16, 2017Assignee: TOKYO ELECTRON LIMITEDInventor: Masafumi Urakawa
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Patent number: 9390937Abstract: A method of etching exposed silicon-nitrogen-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-nitrogen-and-carbon-containing material. The plasma effluents react with the patterned heterogeneous structures to selectively remove silicon-nitrogen-and-carbon-containing material from the exposed silicon-nitrogen-and-carbon-containing material regions while very slowly removing selected other exposed materials. The silicon-nitrogen-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element controls the number of ionically-charged species that reach the substrate.Type: GrantFiled: March 15, 2013Date of Patent: July 12, 2016Assignee: Applied Materials, Inc.Inventors: Zhijun Chen, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
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Patent number: 9355886Abstract: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.Type: GrantFiled: November 7, 2013Date of Patent: May 31, 2016Assignee: Novellus Systems, Inc.Inventors: Shankar Swaminathan, Bart van Schravendijk, Adrien LaVoie, Sesha Varadarajan, Jason Daejin Park, Michal Danek, Naohiro Shoda
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Patent number: 9305839Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.Type: GrantFiled: December 19, 2013Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
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Patent number: 9245752Abstract: This present disclosure relates to an atomic layer etching method for graphene, including adsorbing reactive radicals onto a surface of the graphene and irradiating an energy source to the graphene on which the reactive radicals are adsorbed.Type: GrantFiled: January 22, 2014Date of Patent: January 26, 2016Assignee: Research & Business Foundation Sungkyunkwan UniversityInventors: Geun Young Yeom, Woong Sun Lim, Kyung Seok Min, Yi Yeon Kim, Jong Sik Oh
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Patent number: 9165776Abstract: There is provided according to the present invention a dry etching method for a laminated film, the laminated film being formed on a substrate and having a laminated structure in which silicon layers and insulating layers are laminated together with a hole or groove defined therein in a direction perpendicular to a surface of the substrate, the dry etching method comprising etching, with an etching gas, parts of the silicon layers appearing on an inner surface of the hole or groove, characterized in that the etching gas comprises: at least one kind of gas selected from the group consisting of ClF3, BrF5, BrF3, IF7 and IF5; and F2. It is possible by such a dry etching method to prevent non-uniformity of etching depth between the silicon layers.Type: GrantFiled: August 8, 2012Date of Patent: October 20, 2015Assignee: Central Glass Company, LimitedInventors: Tomonori Umezaki, Isamu Mori
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Publication number: 20150132969Abstract: A substrate processing apparatus includes an electrostatic chuck that includes a chuck electrode and electrostatically attracts a substrate; a direct voltage source that is connected to the chuck electrode and applies a voltage to the chuck electrode; and an evacuation unit that includes a rotor and discharges, via a heat transfer gas discharge pipe, a heat transfer gas supplied to a back surface of the substrate electrostatically-attracted by the electrostatic chuck. The evacuation unit is connected via a power supply line to the direct voltage source, generates regenerative power, and supplies the regenerative power to the direct voltage source.Type: ApplicationFiled: November 6, 2014Publication date: May 14, 2015Inventor: Shingo KOIWA
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Publication number: 20150126038Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. A electrode unit of a stage includes an electrostatic chuck. An area of an upper surface of the electrostatic chuck onto which the wafer is placed via the holding sheet is a flat portion and is not subject to backside gas cooling. A first groove structure is formed in the area onto which the wafer is placed via the holding sheet as well as in an area onto which a holding sheet between the wafer and the frame. To a minute space defined by the first groove structure and the carrier, a heat transfer gas is supplied from a first heat transfer gas supply section through heat transfer gas supply hole (backside gas cooling). Both of plasma processing performance and cooling performance are improved.Type: ApplicationFiled: October 28, 2014Publication date: May 7, 2015Inventor: Shogo OKITA
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Publication number: 20150118857Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.Type: ApplicationFiled: December 29, 2014Publication date: April 30, 2015Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
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Publication number: 20150118856Abstract: A microwave induced plasma decapsulation system and method for decapsulation a packaged semiconductor device applies a microwave induced plasma effluent along with etchant gases electrons, ions and free radicals that are chemically reactive to remove the epoxy molding compound encapsulating the semiconductor device. In one embodiment, the decapsulation system utilizes a microwave generator and a coaxial plasma source. In another embodiment, the decapsulation system utilizes a microwave generator, an electromagnetic surface wave plasma source, and a dielectric plasma discharge tube.Type: ApplicationFiled: October 15, 2014Publication date: April 30, 2015Inventors: Alan M. Wagner, Ravin Krishnan
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Publication number: 20150118855Abstract: A microwave induced plasma decapsulation system and method for decapsulation a packaged semiconductor device applies a microwave induced plasma effluent along with etchant gases electrons, ions and free radicals that are chemically reactive to remove the epoxy molding compound encapsulating the semiconductor device. In one embodiment, the decapsulation system utilizes a microwave generator and a coaxial plasma source. In another embodiment, the decapsulation system utilizes a microwave generator, an electromagnetic surface wave plasma source, and a dielectric plasma discharge tube.Type: ApplicationFiled: October 15, 2014Publication date: April 30, 2015Inventors: Alan M. Wagner, Ravin Krishnan
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Publication number: 20150099367Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.Type: ApplicationFiled: October 2, 2014Publication date: April 9, 2015Inventors: Jong Mun KIM, Jairaj J. PAYYAPILLY
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Publication number: 20150079801Abstract: An oxide etching method includes loading an object to be processed, on a surface of which a patterned silicon oxide film is formed, in a chamber, supplying HF gas and NH3 gas as reactant gases and a diluent gas to the chamber to conduct a reaction treatment in which the HF gas and the NH3 gas are reacted with the silicon oxide film. Thereafter, a heating process is performed to remove a reaction product generated by the reaction treatment. In the reaction treatment, a pressure in the chamber is increased to a predetermined value by increasing a flow rate of the diluent gas so that no etching residue remains and an etching shape has high verticality after the heating process.Type: ApplicationFiled: November 21, 2014Publication date: March 19, 2015Inventor: Tomoki SUEMASA
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Publication number: 20150064921Abstract: Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius.Type: ApplicationFiled: August 30, 2013Publication date: March 5, 2015Inventors: Srinivas D. NEMANI, Sean S. KANG, Jeremiah T. P. PENDER, Chia-Ling KAO, Sergey G. BELOSTOTSKIY, Lina ZHU
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Publication number: 20150064922Abstract: Provided is a method of selectively removing a first region from a workpiece which includes the first region formed of silicon oxide and a second region formed of silicon. The method performs a plurality of sequences. Each sequence includes: forming a denatured region by generating plasma of a processing gas that contains hydrogen, nitrogen, and fluorine within a processing container that accommodates the workpiece so as to denature a portion of the first region, and removing the denatured region within the processing container. In addition, a sequence subsequent to a predetermined number of sequences after a first sequence among the plurality of sequences further includes exposing the workpiece to plasma of a reducing gas which is generated within the processing container, prior to the forming of the denatured region.Type: ApplicationFiled: August 27, 2014Publication date: March 5, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Akinori KITAMURA, Hiroto OHTAKE, Eiji SUZUKI
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Patent number: 8963052Abstract: A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second.Type: GrantFiled: May 6, 2009Date of Patent: February 24, 2015Assignee: Lam Research CorporationInventors: Neil Benjamin, Robert Steger
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Patent number: 8955579Abstract: There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased.Type: GrantFiled: April 21, 2011Date of Patent: February 17, 2015Assignee: Hitachi High-Technologies CorporationInventors: Takumi Tandou, Kenetsu Yokogawa, Masaru Izawa
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Patent number: 8956978Abstract: Nanotube devices and approaches therefore involve the formation and/or implementation of substantially semiconducting single-walled nanotubes. According to an example embodiment of the present invention, substantially semiconducting single-walled nanotubes couple circuit nodes in an electrical device. In some applications, semiconducting and metallic nanotubes having a diameter in a threshold range are exposed to an etch gas that selectively etches the metallic nanotubes, leaving substantially semiconducting nanotubes coupling the circuit nodes.Type: GrantFiled: July 30, 2007Date of Patent: February 17, 2015Assignee: The Board of Trustees of the Leland Stanford Junior UniverityInventors: Hongjie Dai, Guangyu Zhang, Pengfei Qi
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Publication number: 20150044879Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.Type: ApplicationFiled: August 9, 2013Publication date: February 12, 2015Applicant: United Microelectronics Corp.Inventors: Chin-I Liao, Yu-Cheng Tung
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Publication number: 20150037982Abstract: In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing chamber of a plasma processing apparatus. The multilayer film is formed by alternately stacking a silicon oxide film and a silicon nitride film. The multilayer film is etched by supplying a processing gas containing hydrogen gas, hydrogen bromide gas, nitrogen trifluoride gas and at least one of hydrocarbon gas, fluorohydrocarbon gas and fluorocarbon gas into the processing chamber of the plasma processing apparatus and generating a plasma of the processing gas in the processing chamber.Type: ApplicationFiled: July 31, 2014Publication date: February 5, 2015Applicant: TOKYO ELECTRON LIMITEDInventors: Kazuto OGAWA, Kazuki NARISHIGE, Takanori SATO
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Patent number: 8927435Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.Type: GrantFiled: May 8, 2013Date of Patent: January 6, 2015Assignee: ASM America, Inc.Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
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Patent number: 8916052Abstract: The present disclosure provides various methods for removing a resist layer from a wafer. An exemplary method includes performing an etching process to remove a resist layer from a wafer. During the etching process, a first heating process is performed to effect a first graded thermal profile in the resist layer, the first graded thermal profile having a temperature that increases along a direction perpendicular to the wafer. Further during the etching process, and after performing the first heating process, a second heating process is performed to effect a second graded thermal profile in the resist layer, the second graded thermal profile having a temperature that decreases along the direction perpendicular to the wafer. In an example, the method further includes, before performing the etching process, performing an ion implantation process to the wafer using the resist layer as a mask.Type: GrantFiled: February 1, 2013Date of Patent: December 23, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jung-Jui Li, Buh-Kuan Fang
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Patent number: 8916477Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.Type: GrantFiled: June 12, 2013Date of Patent: December 23, 2014Assignee: Novellus Systems, Inc.Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
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Publication number: 20140370716Abstract: There is disclosed a method of preserving the integrity of a growth substrate in a epitaxial lift-off method, the method comprising providing a structure comprising a growth substrate, one or more protective layers, a sacrificial layer, and at least one epilayer, wherein the sacrificial layer and the one or more protective layers are positioned between the growth substrate and the at least one epilayer; releasing the at least one epilayer by etching the sacrificial layer with an etchant; and heat treating the growth substrate and/or at least one of the protective layers.Type: ApplicationFiled: February 7, 2013Publication date: December 18, 2014Inventors: Kyusang Lee, Jeramy Zimmerman, Stephen R. Forrest
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Patent number: 8906810Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.Type: GrantFiled: May 7, 2013Date of Patent: December 9, 2014Assignee: Lam Research CorporationInventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
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Patent number: 8895452Abstract: A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support arm is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber.Type: GrantFiled: May 31, 2012Date of Patent: November 25, 2014Assignee: Lam Research CorporationInventors: Jerrel Kent Antolik, Yen-kun Victor Wang, John Holland
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Patent number: 8883650Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.Type: GrantFiled: January 24, 2008Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
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Patent number: 8877553Abstract: The present invention generally comprises a floating slit valve for interfacing with a chamber. A floating slit valve moves or “floats” relative to another object such as a chamber. The slit valve may be coupled between two chambers. When a chamber coupled with the slit valve is heated, the slit valve may also be heated by conduction. As the slit valve is heated, it may thermally expand. When a vacuum is drawn in a chamber, the slit valve may deform due to vacuum deflection. By disposing a low friction material spacer between the chamber and the slit valve, the slit valve may not rub against the chamber during thermal expansion/contraction and/or vacuum deflection and thus, may not generate undesirable particle contaminants. Additionally, slots drilled through the chamber for coupling the slit valve to the chamber may be sized to accommodate thermal expansion/contraction and vacuum deflection of the slit valve.Type: GrantFiled: August 1, 2011Date of Patent: November 4, 2014Assignee: Applied Materials, Inc.Inventors: John M. White, Shinichi Kurita, Takayuki Matsumoto