With Substrate Heating Or Cooling Patents (Class 438/715)
  • Patent number: 10573518
    Abstract: A method of performing a film formation on target substrates in a state where a substrate holder for holding the target substrates in a shelf shape is loaded into a vertical reaction container from a lower opening thereof and the lower opening is closed by a lid. The method includes: performing the film formation on the target substrates by supplying a processing gas into the reaction container; opening the lid and unloading the substrate holder from the reaction container; performing the film formation on a bottom portion of the reaction container including an inner surface of the lid by closing the lower opening with the lid and supplying a coating gas different from the processing gas into the reaction container; and performing the film formation on the target substrates by opening the lid, loading the substrate holder into the reaction container, and supplying the processing gas into the reaction container.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: February 25, 2020
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Yoshikazu Furusawa
  • Patent number: 10428441
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Olsen, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
  • Patent number: 10400775
    Abstract: A vacuum valve attached to a vacuum pump configured to generate regenerative power to perform a stop operation upon blackout, comprises: a first power input section to which power is input from a commercial power source; a second power input section to which the regenerative power generated at the vacuum pump is input; and a valve source circuit to which the power input to each of the first and second power input sections is supplied. When the power from the commercial power source is supplied to the first power input section, the vacuum valve is operated by the supplied power, and when the power from the commercial power source is stopped, the vacuum valve is operated by the regenerative power.
    Type: Grant
    Filed: January 6, 2018
    Date of Patent: September 3, 2019
    Assignee: Shimadzu Corporation
    Inventors: Masaya Nakamura, Junichiro Kozaki, Atsuo Nakatani, Nobuyuki Hirata
  • Patent number: 10395944
    Abstract: Methods and apparatuses for filling features with metal materials such as tungsten-containing materials in a substantially void-free manner are provided. In certain embodiments, the method involves depositing an initial layer of a metal such as a tungsten-containing material followed by removing a portion of the initial layer to form a remaining layer, which is differentially passivated along the depth of the high-aspect ratio feature. The portion may be removed by exposing the tungsten-containing material to a plasma generated from a fluorine-containing nitrogen-containing gas and pulsing and/or ramping the plasma during the exposure.
    Type: Grant
    Filed: May 1, 2018
    Date of Patent: August 27, 2019
    Assignee: Lam Research Corporation
    Inventors: Waikit Fung, Liang Meng, Anand Chandrashekar
  • Patent number: 10381237
    Abstract: An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is ?35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process.
    Type: Grant
    Filed: May 11, 2018
    Date of Patent: August 13, 2019
    Assignee: Tokyo Electron Limited
    Inventors: Ryohei Takeda, Sho Tominaga, Yoshinobu Ooya
  • Patent number: 10325781
    Abstract: A method for etching a titanium nitride film includes a first process of supplying reactive species, which include hydrogen and fluorine, to a base material including a titanium nitride film on at least a part of a surface, and a second process of vacuum-heating the base material to remove the surface reaction layer that is generated on the surface of the titanium nitride film in the first process.
    Type: Grant
    Filed: September 8, 2017
    Date of Patent: June 18, 2019
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Kazunori Shinoda, Satoshi Sakai, Masaru Izawa, Nobuya Miyoshi, Hiroyuki Kobayashi, Yutaka Kouzuma, Kenji Ishikawa, Masaru Hori
  • Patent number: 10297458
    Abstract: Embodiments of the present technology may include a method of etching. The method may include mixing plasma effluents with a gas in a first section of a chamber to form a first mixture. The method may also include flowing the first mixture to a substrate in a second section of the chamber. The first section and the second section may include nickel plated material. The method may further include reacting the first mixture with the substrate to etch a first layer selectively over a second layer. In addition, the method may include forming a second mixture including products from reacting the first mixture with the substrate.
    Type: Grant
    Filed: August 7, 2017
    Date of Patent: May 21, 2019
    Assignee: Applied Materials, Inc.
    Inventors: Dongqing Yang, Tien Fak Tan, Peter Hillman, Lala Zhu, Nitin K. Ingle, Dmitry Lubomirsky, Christopher Snedigar, Ming Xia
  • Patent number: 9997374
    Abstract: An etching method performed by an etching apparatus includes a first process of causing a first high-frequency power supply to output a first high-frequency power with a first frequency and causing a second high-frequency power supply to output a second high-frequency power with a second frequency lower than the first frequency in a cryogenic environment where the temperature of a wafer is ?35° C. or lower, to generate plasma from a hydrogen-containing gas and a fluorine-containing gas and to etch, with the plasma, a multi-layer film of silicon dioxide and silicon nitride and a single-layer film of silicon dioxide that are formed on the wafer; and a second process of stopping the output of the second high-frequency power supply. The first process and the second process are repeated multiple times, and the first process is shorter in time than the second process.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: June 12, 2018
    Assignee: Tokyo Electron Limited
    Inventors: Ryohei Takeda, Sho Tominaga, Yoshinobu Ooya
  • Patent number: 9666446
    Abstract: An etching method includes generating a plasma from a hydrogen-containing gas and a fluorine-containing gas with high-frequency electric power for plasma generation. A first film including a silicon oxide film and a silicon nitride film is etched with the generated plasma in an environment at a temperature lower than or equal to ?30° C. The first etch rate of first etching that etches the first film and the second etch rate of second etching that etches a second film having a structure different from the structure of the first film are controlled, so that the difference between the first etch rate and the second etch rate is within ±20% of the first etch rate.
    Type: Grant
    Filed: April 18, 2016
    Date of Patent: May 30, 2017
    Assignee: Tokyo Electron Limited
    Inventors: Sho Tominaga, Wataru Takayama, Yoshiki Igarashi
  • Patent number: 9653316
    Abstract: Disclosed is a plasma processing method which includes a gas supplying process, a power supplying process, and an etching process. In the gas supplying process, a processing gas is supplied into a processing container in which an object to be processed is disposed. In the power supplying process, a plasma generating power of a frequency ranging from about 100 MHz to about 150 MHz as a power for generating plasma of the processing gas supplied into the processing container, and a biasing power which is a power having a frequency lower than that of the plasma generating power are supplied. In the etching process, the object to be processed is etched by the plasma of the processing gas while the biasing power is pulse-modulated so that the duty ratio ranges from about 10% to about 70% and the frequency ranges from about 5 kHz to about 20 kHz.
    Type: Grant
    Filed: February 18, 2014
    Date of Patent: May 16, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventor: Masafumi Urakawa
  • Patent number: 9390937
    Abstract: A method of etching exposed silicon-nitrogen-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-nitrogen-and-carbon-containing material. The plasma effluents react with the patterned heterogeneous structures to selectively remove silicon-nitrogen-and-carbon-containing material from the exposed silicon-nitrogen-and-carbon-containing material regions while very slowly removing selected other exposed materials. The silicon-nitrogen-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element controls the number of ionically-charged species that reach the substrate.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: July 12, 2016
    Assignee: Applied Materials, Inc.
    Inventors: Zhijun Chen, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle
  • Patent number: 9355886
    Abstract: A method and apparatus for conformally depositing a dielectric oxide in high aspect ratio gaps in a substrate is disclosed. A substrate is provided with one or more gaps into a reaction chamber where each gap has a depth to width aspect ratio of greater than about 5:1. A first dielectric oxide layer is deposited in the one or more gaps by CFD. A portion of the first dielectric oxide layer is etched using a plasma etch, where etching the portion of the first dielectric oxide layer occurs at a faster rate near a top surface than near a bottom surface of each gap so that the first dielectric oxide layer has a tapered profile from the top surface to the bottom surface of each gap. A second dielectric oxide layer is deposited in the one or more gaps over the first dielectric oxide layer via CFD.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: May 31, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Shankar Swaminathan, Bart van Schravendijk, Adrien LaVoie, Sesha Varadarajan, Jason Daejin Park, Michal Danek, Naohiro Shoda
  • Patent number: 9305839
    Abstract: A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: April 5, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Kuo Hsieh, Tsung-Hung Chu, Ming-Chung Liang
  • Patent number: 9245752
    Abstract: This present disclosure relates to an atomic layer etching method for graphene, including adsorbing reactive radicals onto a surface of the graphene and irradiating an energy source to the graphene on which the reactive radicals are adsorbed.
    Type: Grant
    Filed: January 22, 2014
    Date of Patent: January 26, 2016
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Geun Young Yeom, Woong Sun Lim, Kyung Seok Min, Yi Yeon Kim, Jong Sik Oh
  • Patent number: 9165776
    Abstract: There is provided according to the present invention a dry etching method for a laminated film, the laminated film being formed on a substrate and having a laminated structure in which silicon layers and insulating layers are laminated together with a hole or groove defined therein in a direction perpendicular to a surface of the substrate, the dry etching method comprising etching, with an etching gas, parts of the silicon layers appearing on an inner surface of the hole or groove, characterized in that the etching gas comprises: at least one kind of gas selected from the group consisting of ClF3, BrF5, BrF3, IF7 and IF5; and F2. It is possible by such a dry etching method to prevent non-uniformity of etching depth between the silicon layers.
    Type: Grant
    Filed: August 8, 2012
    Date of Patent: October 20, 2015
    Assignee: Central Glass Company, Limited
    Inventors: Tomonori Umezaki, Isamu Mori
  • Publication number: 20150132969
    Abstract: A substrate processing apparatus includes an electrostatic chuck that includes a chuck electrode and electrostatically attracts a substrate; a direct voltage source that is connected to the chuck electrode and applies a voltage to the chuck electrode; and an evacuation unit that includes a rotor and discharges, via a heat transfer gas discharge pipe, a heat transfer gas supplied to a back surface of the substrate electrostatically-attracted by the electrostatic chuck. The evacuation unit is connected via a power supply line to the direct voltage source, generates regenerative power, and supplies the regenerative power to the direct voltage source.
    Type: Application
    Filed: November 6, 2014
    Publication date: May 14, 2015
    Inventor: Shingo KOIWA
  • Publication number: 20150126038
    Abstract: A dry etching apparatus plasma processes a wafer held by a carrier having a frame and an holding sheet. A electrode unit of a stage includes an electrostatic chuck. An area of an upper surface of the electrostatic chuck onto which the wafer is placed via the holding sheet is a flat portion and is not subject to backside gas cooling. A first groove structure is formed in the area onto which the wafer is placed via the holding sheet as well as in an area onto which a holding sheet between the wafer and the frame. To a minute space defined by the first groove structure and the carrier, a heat transfer gas is supplied from a first heat transfer gas supply section through heat transfer gas supply hole (backside gas cooling). Both of plasma processing performance and cooling performance are improved.
    Type: Application
    Filed: October 28, 2014
    Publication date: May 7, 2015
    Inventor: Shogo OKITA
  • Publication number: 20150118856
    Abstract: A microwave induced plasma decapsulation system and method for decapsulation a packaged semiconductor device applies a microwave induced plasma effluent along with etchant gases electrons, ions and free radicals that are chemically reactive to remove the epoxy molding compound encapsulating the semiconductor device. In one embodiment, the decapsulation system utilizes a microwave generator and a coaxial plasma source. In another embodiment, the decapsulation system utilizes a microwave generator, an electromagnetic surface wave plasma source, and a dielectric plasma discharge tube.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 30, 2015
    Inventors: Alan M. Wagner, Ravin Krishnan
  • Publication number: 20150118855
    Abstract: A microwave induced plasma decapsulation system and method for decapsulation a packaged semiconductor device applies a microwave induced plasma effluent along with etchant gases electrons, ions and free radicals that are chemically reactive to remove the epoxy molding compound encapsulating the semiconductor device. In one embodiment, the decapsulation system utilizes a microwave generator and a coaxial plasma source. In another embodiment, the decapsulation system utilizes a microwave generator, an electromagnetic surface wave plasma source, and a dielectric plasma discharge tube.
    Type: Application
    Filed: October 15, 2014
    Publication date: April 30, 2015
    Inventors: Alan M. Wagner, Ravin Krishnan
  • Publication number: 20150118857
    Abstract: Methods of etching exposed titanium nitride with respect to other materials on patterned heterogeneous structures are described, and may include a remote plasma etch formed from a fluorine-containing precursor. Precursor combinations including plasma effluents from the remote plasma are flowed into a substrate processing region to etch the patterned structures with high titanium nitride selectivity under a variety of operating conditions. The methods may be used to remove titanium nitride at faster rates than a variety of metal, nitride, and oxide compounds.
    Type: Application
    Filed: December 29, 2014
    Publication date: April 30, 2015
    Inventors: Jie Liu, Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Seung Park, Zhijun Chen, Ching-Mei Hsu
  • Publication number: 20150099367
    Abstract: Implementations described herein generally relate to semiconductor manufacturing and more particularly to the process of plasma etching an amorphous carbon layer. In one implementation, a method of etching a feature in an amorphous carbon layer is provided. The method comprises transferring a substrate including a patterned photoresist layer disposed above the amorphous carbon layer into an etching chamber, exposing the amorphous carbon layer to a fluorine-free etchant gas mixture including a fluorine-free halogen source gas and a passivation source gas and etching the amorphous carbon layer with a plasma of the fluorine-free etchant gas mixture. It has been found that plasma etching with a fluorine-free halogen based gas mixture reduces the formation of top critical dimension clogging oxides.
    Type: Application
    Filed: October 2, 2014
    Publication date: April 9, 2015
    Inventors: Jong Mun KIM, Jairaj J. PAYYAPILLY
  • Publication number: 20150079801
    Abstract: An oxide etching method includes loading an object to be processed, on a surface of which a patterned silicon oxide film is formed, in a chamber, supplying HF gas and NH3 gas as reactant gases and a diluent gas to the chamber to conduct a reaction treatment in which the HF gas and the NH3 gas are reacted with the silicon oxide film. Thereafter, a heating process is performed to remove a reaction product generated by the reaction treatment. In the reaction treatment, a pressure in the chamber is increased to a predetermined value by increasing a flow rate of the diluent gas so that no etching residue remains and an etching shape has high verticality after the heating process.
    Type: Application
    Filed: November 21, 2014
    Publication date: March 19, 2015
    Inventor: Tomoki SUEMASA
  • Publication number: 20150064922
    Abstract: Provided is a method of selectively removing a first region from a workpiece which includes the first region formed of silicon oxide and a second region formed of silicon. The method performs a plurality of sequences. Each sequence includes: forming a denatured region by generating plasma of a processing gas that contains hydrogen, nitrogen, and fluorine within a processing container that accommodates the workpiece so as to denature a portion of the first region, and removing the denatured region within the processing container. In addition, a sequence subsequent to a predetermined number of sequences after a first sequence among the plurality of sequences further includes exposing the workpiece to plasma of a reducing gas which is generated within the processing container, prior to the forming of the denatured region.
    Type: Application
    Filed: August 27, 2014
    Publication date: March 5, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akinori KITAMURA, Hiroto OHTAKE, Eiji SUZUKI
  • Publication number: 20150064921
    Abstract: Methods for etching a material layer disposed on the substrate using a low temperature etching process along with a subsequent low temperature plasma annealing process are provided. In one embodiment, a method for etching a material layer disposed on a substrate includes transferring a substrate having a material layer disposed thereon into an etching processing chamber, supplying an etching gas mixture into the processing chamber, remotely generating a plasma in the etching gas mixture to etch the material layer disposed on the substrate, and plasma annealing the material layer at a substrate temperature less than 100 degrees Celsius.
    Type: Application
    Filed: August 30, 2013
    Publication date: March 5, 2015
    Inventors: Srinivas D. NEMANI, Sean S. KANG, Jeremiah T. P. PENDER, Chia-Ling KAO, Sergey G. BELOSTOTSKIY, Lina ZHU
  • Patent number: 8963052
    Abstract: A chuck for a plasma processor comprises a temperature-controlled base, a thermal insulator, a flat support, and a heater. The temperature-controlled base is controlled in operation a temperature below the desired temperature of a workpiece. The thermal insulator is disposed over at least a portion of the temperature-controlled base. The flat support holds a workpiece and is disposed over the thermal insulator. A heater is embedded within the flat support and/or mounted to an underside of the flat support. The heater includes a plurality of heating elements that heat a plurality of corresponding heating zones. The power supplied and/or temperature of each heating element is controlled independently. The heater and flat support have a combined temperature rate change of at least 1° C. per second.
    Type: Grant
    Filed: May 6, 2009
    Date of Patent: February 24, 2015
    Assignee: Lam Research Corporation
    Inventors: Neil Benjamin, Robert Steger
  • Patent number: 8956978
    Abstract: Nanotube devices and approaches therefore involve the formation and/or implementation of substantially semiconducting single-walled nanotubes. According to an example embodiment of the present invention, substantially semiconducting single-walled nanotubes couple circuit nodes in an electrical device. In some applications, semiconducting and metallic nanotubes having a diameter in a threshold range are exposed to an etch gas that selectively etches the metallic nanotubes, leaving substantially semiconducting nanotubes coupling the circuit nodes.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: February 17, 2015
    Assignee: The Board of Trustees of the Leland Stanford Junior Univerity
    Inventors: Hongjie Dai, Guangyu Zhang, Pengfei Qi
  • Patent number: 8955579
    Abstract: There is provided a means for uniformly controlling the in-plane temperature of a semiconductor wafer at high speed in a high heat input etching process. A refrigerant channel structure in a circular shape is formed in a sample stage. Due to a fact that a heat transfer coefficient of a refrigerant is largely changed from a refrigerant supply port to a refrigerant outlet port, the cross sections of the channel structure is structured so as to be increased from a first channel areas towards a second channel areas in order to make the heat transfer coefficient of the refrigerant constant in the refrigerant channel structure. Thereby, the heat transfer coefficient of the refrigerant is prevented from increasing by reducing the flow rate of the refrigerant at a dry degree area where the heat transfer coefficient of the refrigerant is increased.
    Type: Grant
    Filed: April 21, 2011
    Date of Patent: February 17, 2015
    Assignee: Hitachi High-Technologies Corporation
    Inventors: Takumi Tandou, Kenetsu Yokogawa, Masaru Izawa
  • Publication number: 20150044879
    Abstract: A removing method including the following steps. A substrate is transferred into an etching machine, wherein the substrate has a material layer formed thereon. A cycle process is performed. The cycle process includes performing an etching process to remove a portion of the material layer, and performing an annealing process to remove a by-product generated by the etching process. The cycle process is repeated at least one time. The substrate is transferred out of the etching machine. In the removing method of the invention, the cycle process is performed multiple times to effectively remove the undesired thickness of the material layer and reduce the loading effect.
    Type: Application
    Filed: August 9, 2013
    Publication date: February 12, 2015
    Applicant: United Microelectronics Corp.
    Inventors: Chin-I Liao, Yu-Cheng Tung
  • Publication number: 20150037982
    Abstract: In a semiconductor device manufacturing method, a target object including a multilayer film and a mask formed on the multilayer film is prepared in a processing chamber of a plasma processing apparatus. The multilayer film is formed by alternately stacking a silicon oxide film and a silicon nitride film. The multilayer film is etched by supplying a processing gas containing hydrogen gas, hydrogen bromide gas, nitrogen trifluoride gas and at least one of hydrocarbon gas, fluorohydrocarbon gas and fluorocarbon gas into the processing chamber of the plasma processing apparatus and generating a plasma of the processing gas in the processing chamber.
    Type: Application
    Filed: July 31, 2014
    Publication date: February 5, 2015
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Kazuto OGAWA, Kazuki NARISHIGE, Takanori SATO
  • Patent number: 8927435
    Abstract: A load lock includes a chamber including an upper portion, a lower portion, and a partition between the upper portion and the lower portion, the partition including an opening therethrough. The load lock further includes a first port in communication with the upper portion of the chamber and a second port in communication with the lower portion of the chamber. The load lock includes a rack disposed within the chamber and a workpiece holder mounted on a first surface of the rack, wherein the rack and the workpiece holder are movable by an indexer that is capable of selectively moving wafer slots of the rack into communication with the second port. The indexer can also move the rack into an uppermost position, at which the first surface of the boat and the partition sealingly separate the upper portion and the lower portion to define an upper chamber and a lower chamber. Auxiliary processing, such as wafer pre-cleaning, or metrology can be conducted in the upper portion.
    Type: Grant
    Filed: May 8, 2013
    Date of Patent: January 6, 2015
    Assignee: ASM America, Inc.
    Inventors: Ravinder K. Aggarwal, Jeroen Stoutjesdijk, Eric R. Hill, Loring G. Davis, John T. DiSanto
  • Patent number: 8916052
    Abstract: The present disclosure provides various methods for removing a resist layer from a wafer. An exemplary method includes performing an etching process to remove a resist layer from a wafer. During the etching process, a first heating process is performed to effect a first graded thermal profile in the resist layer, the first graded thermal profile having a temperature that increases along a direction perpendicular to the wafer. Further during the etching process, and after performing the first heating process, a second heating process is performed to effect a second graded thermal profile in the resist layer, the second graded thermal profile having a temperature that decreases along the direction perpendicular to the wafer. In an example, the method further includes, before performing the etching process, performing an ion implantation process to the wafer using the resist layer as a mask.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: December 23, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jung-Jui Li, Buh-Kuan Fang
  • Patent number: 8916477
    Abstract: Provided are methods and systems for removing polysilicon on a wafer. A wafer can include a polysilicon layer and an exposed nitride and/or oxide structure. An etchant with a hydrogen-based species, such as hydrogen gas, and a fluorine-based species, such as nitrogen trifluoride, can be introduced. The hydrogen-based species and the fluorine-based species can be activated with a remote plasma source. The layer of polysilicon on the wafer can be removed at a selectivity over the exposed nitride and/or oxide structure that is greater than about 500:1.
    Type: Grant
    Filed: June 12, 2013
    Date of Patent: December 23, 2014
    Assignee: Novellus Systems, Inc.
    Inventors: Bayu Thedjoisworo, Jack Kuo, David Cheung, Joon Park
  • Publication number: 20140370716
    Abstract: There is disclosed a method of preserving the integrity of a growth substrate in a epitaxial lift-off method, the method comprising providing a structure comprising a growth substrate, one or more protective layers, a sacrificial layer, and at least one epilayer, wherein the sacrificial layer and the one or more protective layers are positioned between the growth substrate and the at least one epilayer; releasing the at least one epilayer by etching the sacrificial layer with an etchant; and heat treating the growth substrate and/or at least one of the protective layers.
    Type: Application
    Filed: February 7, 2013
    Publication date: December 18, 2014
    Inventors: Kyusang Lee, Jeramy Zimmerman, Stephen R. Forrest
  • Patent number: 8906810
    Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.
    Type: Grant
    Filed: May 7, 2013
    Date of Patent: December 9, 2014
    Assignee: Lam Research Corporation
    Inventors: Ananth Indrakanti, Bhaskar Nagabhirava, Alan Jensen, Tom Choi
  • Patent number: 8895452
    Abstract: A semiconductor substrate support for use in a plasma processing apparatus comprises a chuck body having a plenum and three radially extending bores extending between the plenum and an outer periphery of the chuck body, wherein the chuck body is sized to support a semiconductor substrate having a diameter of at least 450 mm. The semiconductor substrate support further comprises three tubular support arms which include a first section extending radially outward from the outer periphery of the chuck body, and a second section extending vertically from the first section. The tubular support arms provide a passage therethrough which communicates with a respective bore in the chuck body. The second section of each tubular support arm is configured to engage with a respective actuation mechanism outside the chamber operable to effect vertical translation and planarization of the chuck body in the interior of a plasma processing chamber.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: November 25, 2014
    Assignee: Lam Research Corporation
    Inventors: Jerrel Kent Antolik, Yen-kun Victor Wang, John Holland
  • Patent number: 8883650
    Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: November 11, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Kuo-Chih Lai, Yi-Wei Chen, Nien-Ting Ho, Teng-Chun Tsai
  • Patent number: 8877553
    Abstract: The present invention generally comprises a floating slit valve for interfacing with a chamber. A floating slit valve moves or “floats” relative to another object such as a chamber. The slit valve may be coupled between two chambers. When a chamber coupled with the slit valve is heated, the slit valve may also be heated by conduction. As the slit valve is heated, it may thermally expand. When a vacuum is drawn in a chamber, the slit valve may deform due to vacuum deflection. By disposing a low friction material spacer between the chamber and the slit valve, the slit valve may not rub against the chamber during thermal expansion/contraction and/or vacuum deflection and thus, may not generate undesirable particle contaminants. Additionally, slots drilled through the chamber for coupling the slit valve to the chamber may be sized to accommodate thermal expansion/contraction and vacuum deflection of the slit valve.
    Type: Grant
    Filed: August 1, 2011
    Date of Patent: November 4, 2014
    Assignee: Applied Materials, Inc.
    Inventors: John M. White, Shinichi Kurita, Takayuki Matsumoto
  • Patent number: 8874254
    Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.
    Type: Grant
    Filed: July 11, 2011
    Date of Patent: October 28, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Shuji Iwanaga, Nobuyuki Sata
  • Patent number: 8853089
    Abstract: A manufacturing method of a semiconductor substrate includes: forming a trench in a semiconductor board by a dry etching method; etching a surface portion of an inner wall of the trench by a chemical etching method so that a first damage layer is removed, wherein the surface portion has a thickness equal to or larger than 50 nanometers; and performing a heat treatment at temperature equal to or higher than 1050° C. in non-oxidizing and non-azotizing gas so that crystallinity of a second damage layer is recovered, wherein the second damage layer is disposed under the first damage layer. The crystallinity around the trench is sufficiently recovered.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: October 7, 2014
    Assignee: DENSO CORPORATION
    Inventors: Hiroshi Ohtsuki, Takumi Shibata
  • Publication number: 20140295671
    Abstract: A plasma processing apparatus is provided which includes a processing chamber disposed in a vacuum container, in a decompressed inside of which plasma is formed, a sample stage disposed in a lower part of the processing chamber, on a top surface of which a sample is mounted, a dielectric film made of a dielectric that forms a mounting surface on which the sample is mounted, and electrodes arranged inside the dielectric film and supplied with power for chucking and holding the sample onto the dielectric film, and when the sample is mounted on the sample stage, the sample is kept mounted on the sample stage until a sample temperature becomes a predetermined temperature or until a predetermined time elapses, and power is then supplied to the electrodes to chuck the sample to the sample stage and then start processing on the sample using the plasma.
    Type: Application
    Filed: February 19, 2014
    Publication date: October 2, 2014
    Inventors: Kohei Sato, Yuya Mizobe, Tomohiro Ohashi
  • Patent number: 8841152
    Abstract: Method for making a patterned thin film of an organic semiconductor. The method includes condensing a resist gas into a solid film onto a substrate cooled to a temperature below the condensation point of the resist gas. The condensed solid film is heated selectively with a patterned stamp to cause local direct sublimation from solid to vapor of selected portions of the solid film thereby creating a patterned resist film. An organic semiconductor film is coated on the patterned resist film and the patterned resist film is heated to cause it to sublime away and to lift off because of the phase change.
    Type: Grant
    Filed: May 7, 2012
    Date of Patent: September 23, 2014
    Assignee: Massachusetts Institute of Technology
    Inventors: Matthias Erhard Bahlke, Marc A. Baldo, Hiroshi Antonio Mendoza
  • Publication number: 20140273488
    Abstract: Systems, chambers, and processes are provided for controlling process defects caused by moisture contamination. The systems may provide configurations for chambers to perform multiple operations in a vacuum or controlled environment. The chambers may include configurations to provide additional processing capabilities in combination chamber designs. The methods may provide for the limiting, prevention, and correction of aging defects that may be caused as a result of etching processes performed by system tools.
    Type: Application
    Filed: April 7, 2014
    Publication date: September 18, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Anchuan Wang, Xinglong Chen, Zihui Li, Hiroshi Hamana, Zhijun Chen, Ching-Mei Hsu, Jiayin Huang, Nitin K. Ingle, Dmitry Lubomirsky, Shankar Venkataraman, Randhir Thakur
  • Patent number: 8835327
    Abstract: A method of manufacturing a semiconductor device disclosed herein includes: mounting a substrate on an electrostatic chuck placed inside a chamber, the electrostatic chuck having a first temperature and the substrate being retained in advance in an atmosphere having a second temperature lower than the first temperature; fixing the substrate onto the electrostatic chuck by applying a voltage to the electrostatic chuck; heating the electrostatic chuck to a third temperature higher than the first temperature and the second temperature after mounting the substrate; and processing the substrate after the heating.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: September 16, 2014
    Assignee: Fujitsu Limited
    Inventors: Masanori Terahara, Hikaru Kokura, Akihiro Hasegawa, Atsuo Fushida, Fumihiko Akaboshi
  • Patent number: 8828881
    Abstract: The invention discloses an etch-back method for planarization at the position-near-interface of an interlayer dielectric (ILD), comprising: depositing or growing a thick layer of SiO2 by the chemical vapor deposition or oxidation method on a surface of a wafer; spin-coating a layer of SOG and then performing a heat treatment to obtain a relatively uniform stack structure; perform an etch-back on the SOG using a plasma etching, and stopping when approaching the position-near-interface of SiO2; performing a plasma etch-back on the remaining SOG/SiO2 structure at the position-near-interface until achieving a desired thickness. Since a two-step etching at the position-near-interface is employed, an extremely good smooth surface of the ILD is obtained. That is, a planar and tidy surface of the ILD is obtained not only in the center region, but also even at the edge of the wafer.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: September 9, 2014
    Assignee: Institute of Microelectronics, Chinese Academy of Sciences
    Inventors: Lingkkuan Meng, Huaxiang Yin
  • Patent number: 8828776
    Abstract: Multi-zone, solar cell diffusion furnaces having a plurality of radiant element (SiC) or/and high intensity IR lamp heated process zones, including baffle, ramp-up, firing, soaking and cooling zone(s). The transport of solar cell wafers, e.g., silicon, selenium, germanium or gallium-based solar cell wafers, through the furnace is implemented by use of an ultra low-mass, wafer transport system comprising laterally spaced shielded, synchronously driven, metal bands or chains carrying non-rotating alumina tubes suspended on wires between them. The wafers rest on raised circumferential standoffs spaced laterally along the alumina tubes, which reduces contamination. The high intensity IR flux rapidly photo-radiation conditions the wafers so that diffusion occurs >3× faster than conventional high-mass thermal furnaces. Longitudinal side wall heaters comprising coil heaters in Inconel sheaths inserted in carrier tubes are employed to insure even heating of wafer edges adjacent the side walls.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: September 9, 2014
    Assignee: TP Solar, Inc.
    Inventors: Richard W. Parks, Luis Alejandro Rey Garcia, Peter G. Ragay
  • Patent number: 8822877
    Abstract: Rapid thermal processing systems and associated methods are disclosed herein. In one embodiment, a method for heating a microelectronic substrate include generating a plasma, applying the generated plasma to a surface of the microelectronic substrate, and raising a temperature of the microelectronic substrate with the generated plasma applied to the surface of the microelectronic substrate. The method further includes continuing to apply the generated plasma until the microelectronic substrate reaches a desired temperature.
    Type: Grant
    Filed: April 23, 2013
    Date of Patent: September 2, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Shu Qin
  • Publication number: 20140242802
    Abstract: A semiconductor process includes the following steps. A wafer on a pedestal is provided. The pedestal is lifted to approach a heating source and an etching process is performed on the wafer. An annealing process is performed on the wafer by the heating source. In another way, a wafer on a pedestal, and a heating source on a same side of the wafer as the pedestal are provided. An etching process is performed on the wafer by setting the temperature difference between the heating source and the pedestal larger than 180° C.
    Type: Application
    Filed: February 25, 2013
    Publication date: August 28, 2014
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Chia Chang Hsu, Kuo-Chih Lai, Chun-Ling Lin, Bor-Shyang Liao, Pin-Hong Chen, Shu Min Huang, Min-Chung Cheng, Chi-Mao Hsu
  • Patent number: 8809197
    Abstract: In a control method, a first processing is performed on an object to be processed by controlling a temperature of a base to a first temperature and controlling a temperature of an electrostatic chuck that is disposed on a mounting surface of the base so as to mount thereon the object to be processed and has a heater installed therein to a second temperature. A second processing is performed on the object by controlling a temperature of the base to a third temperature and controlling a temperature of the electrostatic chuck to a fourth temperature by a heater. In the control method, a difference between the first temperature and the second temperature and a difference between the third temperature and the fourth temperature are within a tolerable temperature of the junction layer for bonding the base and the electrostatic chuck.
    Type: Grant
    Filed: August 29, 2013
    Date of Patent: August 19, 2014
    Assignee: Tokyo Electron Limited
    Inventor: Atsuhiko Tabuchi
  • Patent number: 8796153
    Abstract: An electrode assembly for a plasma reaction chamber used in semiconductor substrate processing. The assembly includes an upper showerhead electrode which is mechanically attached to a backing plate by a series of spaced apart cam locks. A guard ring surrounds the backing plate and is movable to positions at which openings in the guard ring align with openings in the backing plate so that the cam locks can be rotated with a tool to release locking pins extending from the upper face of the electrode.
    Type: Grant
    Filed: March 11, 2013
    Date of Patent: August 5, 2014
    Assignee: Lam Research Corporation
    Inventors: Roger Patrick, Gregory R. Bettencourt, Michael C. Kellogg
  • Patent number: 8791025
    Abstract: The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.
    Type: Grant
    Filed: July 27, 2010
    Date of Patent: July 29, 2014
    Assignee: Canon Kabushiki Kaisha
    Inventors: Shoichi Kawashima, Takeshi Kawashima, Yasuhiro Nagatomo, Katsuyuki Hoshino