Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Abstract: Methods and apparatus are provided for processing semiconductor wafers sequentially. Sequential processes employ multi-station processing modules, where particular encompassing wafer processes are divided into sub-processes, each optimized for increasing wafer to wafer uniformity, result quality, and overall wafer throughput. In one example, a copper electroplating module includes separate stations for wetting, initiation, seed layer repair, fill, overburden, reclaim, and rinse.

Abstract: The invention provides a method of assaying at least one element in a material including silicon. The method includes the steps of decomposing a portion of the material with an etching agent to form a solution containing hexafluorosilicic acid and at least one element to be assayed, heating the solution to a temperature sufficient to transform a substantial portion of the hexafluorosilicic acid into silicon tetrafluoride and to cause at least some of the silicon tetrafluoride to evaporate, such that a solution for assaying is obtained in which the silicon content is reduced while and the elements to be assayed are conserved; and assaying at least one element contained in the solution. The invention is applicable to the field of manufacturing substrates or components for optics, electronics, or optoelectronics, and in particular to the field of quality control.

Abstract: Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate.

Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device in epitaxial layers on a surface of a silicon carbide substrate and with at least one metal contact for the device on the uppermost surface of the epitaxial layer. The opposite surface of the substrate is then ground and polished until it is substantially transparent. The method then includes masking the polished surface of the silicon carbide substrate to define a predetermined location for at least one via that is opposite the device metal contact on the uppermost surface of the epitaxial layer and etching the desired via in steps. The first etching step etches through the silicon carbide substrate at the desired masked location until the etch reaches the epitaxial layer. The second etching step etches through the epitaxial layer to the device contacts.

Abstract: Provided herein is a substrate processing system, which comprises a cassette load station; a load lock chamber; a centrally located transfer chamber; and one or more process chambers located about the periphery of the transfer chamber. The load lock chamber comprises double dual slot load locks constructed at same location. Such system may be used for processing substrates for semiconductor manufacturing.

Abstract: The present invention provides method and apparatus for surface treatment which, when employed in process steps of manufacturing semiconductor devices, can result in the final products having enhanced reliability. According to the surface processing method, an object to be processed W is introduced in a processing vessel 10, which is then supplied with ClF3 gas serving as cleaning gas from a supply unit 26. The ClF3 gas is bound to the surface of the object to be processed W, and although the supply of the gas to the processing vessel is interrupted, the ClF3 gas bound to the surface of the object to be processed W serves to clean the surface of the object to be processed. Next, reducing gas is introduced into the processing vessel W to remove chlorine from the object to be processed W, the chlorine being derived from the ClF3 gas. After that, the introduction of the reducing gas is interrupted, and the cleaned object to be processed W is exported from the processing vessel 10.

Abstract: A transfer robot (5) for thin substrate capable of efficiently detecting the stored state of thin substrates and an inspection method for thin substrate capable of accurately detecting the stored state of thin substrates; the robot (5), comprising an inspection camera (1) for detecting the stored state of the thin substrates (3) in a storage cassette (2), wherein the plurality of thin substrates (3) stored in the storage cassette (2) are carried out from the storage cassette (2) by the robot.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: The insulation film etching method according to the present invention prevents the pause of etching an insulation film while ensuring a good anisotropic (vertical) configuration and high selectivity to both the mask and the base film. When the first step plasma etching using CHF3/Ar/N2 mixed gas is ended, Ar gas as a purging gas is fed into a processing vessel from an Ar gas supply source 46 with the plasmas extinguished, whereby residual hydrogen and hydrogen compounds in the processing vessel 10 are whirled by the purging gas to be discharged through an exhaust port 10b and through an exhaust pipe 52. When the purging step is completed, the second step plasma etching is performed with C4F8/Ar/N2 mixed gas.

Abstract: A multi-chamber system of an etching facility for manufacturing semiconductor devices occupies a minimum amount of floor space in a cleanroom by installing a plurality of processing chambers in multi-layers and in parallel along a transfer path situated between the processing chambers. The multi-layers number 2 to 5, and the transfer path can be rectangular in shape and need only be slightly wider than the diameter of a wafer. The total width of the multi-chamber system is the sum of the width of one processing chamber plus the width of the transfer path.

Abstract: A transfer robot (5) for thin substrate capable of efficiently detecting the stored state of thin substrates and an inspection method for thin substrate capable of accurately detecting the stored state of thin substrates; the robot (5), comprising an inspection camera (1) for detecting the stored state of the thin substrates (3) in a storage cassette (2), wherein the plurality of thin substrates (3) stored in the storage cassette (2) are carried out from the storage cassette (2) by the robot.

Abstract: A method of manufacturing a semiconductor device comprising a plurality of single-crystal semiconductor layers formed, for example, in an opening of an insulating film, said semiconductor layers having no or very few crystal defects. The method comprises forming in a first growth chamber a first semiconductor layer of a first conductivity type in an opening of an insulating film and subsequently forming in a second growth chamber a second semiconductor layer of a second conductivity type in an opening of an insulating film, while supplying hydrogen to the surface of the substrate when the substrate is transferred from said first growth chamber to said second growth chamber.

Abstract: A process for the vacuum treatment of workpieces, includes loading the workpieces into a treatment facility, surface treating the workpieces in at least one vacuum station of the facility grouped as a station batch and controlling at least the timing of the process by a freely programmable process controller unit. At least two stations operating each on workpiece batches can be grouped as respective station batches and be different with respect to number of workpieces. The workpieces can be transported to and from the grouped stations. An embodiment of vacuum treatment system for such a process includes at least one vacuum treatment station for workpieces grouped as a station batch. A transport system supplies the vacuum station with workpieces. A process controller unit has an output operationally connected to a drive arrangement for the transport system. The unit controls operating timing of the treatment system and is freely programmable.

Abstract: Prior to etching a poly-II layer during fabrication of an integrated circuit, a hydrofluoric acid (HF) dip is used to remove surface oxides from the poly-silicon layer and an anisotropic descumming operation is used to remove any resist material left over from a patterning operation. Following patterning, a long breakthrough etch (e.g., sufficient to remove 300-1500 ? of oxide) using an anisotropic breakthrough etchant (e.g., a fluorocarbon-based etchant) is performed before the poly-silicon layer is etched. The HF dip may be repeated if a predetermined time between the first dip and the etch is exceeded. The anisotropic descumming operation may be performed using an anisotropic anti-reflective coating (ARC) etch, e.g., a Cl2/O2, HBr/O2, CF4/O2 or another etch having an etch rate of approximately 3000 ?/min for approximately 10-20 seconds. The poly-silicon layer may be annealed following (but not prior to) the etch thereof.

Abstract: In order to prevent dusting from a peripheral end portion of a wafer, a semiconductor film formed is removed from at least the entire surface of the backside of the wafer and from the peripheral portion of the wafer by etching at a high etching rate relative to an insulating film present beneath the semiconductor film, to realize a semiconductor apparatus in which the semiconductor film is formed in an integrated circuit pattern region on the face side of the wafer. Thus, the problem of dusting from the peripheral portion of the wafer is obviated, and a semiconductor apparatus with high reliability is realized.

Abstract: A dry etching step during the manufacturing of a substrate for a liquid crystal display (LCD) device is improved by placing the substrate at a predetermined distance away from the lower electrode to prevent damage of the substrate due to electrostatic formed therebetween. An insulating tape attached on the lower electrode provides electrostatic protection between the substrate and the lower electrode, so that the substrate is properly lifted off the lower electrode via the lifting pins of the lower electrode without electrostatic interference.

Abstract: The present invention provides a semiconductor device manufacturing line for applying a series of processes on a semiconductor substrate, and forming an integrated circuit on the semiconductor substrate by employing a semiconductor wafer having a diameter of 6 inches (150±3 mm: SEAJ specification) or less for the semiconductor substrate. This manufacturing line comprises two sub-lines conforming to the same specifications, each of these sub-lines is composed of a series of processing units including a film forming unit, a pattern exposure unit, an etching unit, and a test unit. In at least one pattern exposure unit and one etching unit, fine processing of 0.3 ?m or less can be performed.

Abstract: A process of dual damascene or damascene. The dual damascene process entails providing an etching apparatus, a DCM machine and a wafer, the wafer having a metal line, a stop layer, a dielectric layer, a contact, and a photoresist layer. The dielectric layer and the contact are etched in the etching apparatus to form a trench. The photoresist and the contact are ashed in the DCM machine. Finally the wafer is wet cleaned.

Abstract: A plasma processing apparatus and a plasma processing method which make it possible to prevent an abnormal discharge from occurring during workpiece removal without having to modify the design or resulting in a reduction in throughput are provided. A wafer W placed on a lower electrode 106 inside a processing chamber 102 at an etching apparatus 100 undergoes the etching process. When the etching process ends, the polarity of the high level DC voltage applied to an electrostatic chuck 108 vacuum holding the wafer W is reversed. A gate valve G is opened to allow N2 inside a delivery chamber 200 in communication with the processing chamber 102 to flow in. The pressure inside the processing chamber 102 is thus raised to allow a gentle self discharge of the residual charge at the wafer W.

Abstract: A fully depleted SOI FET and methods of formation are disclosed. The FET includes a layer of semiconductor material disposed over an insulating layer, the insulating layer disposed over a semiconductor substrate. A source, a drain and a body disposed between the source and the drain are formed from the layer of semiconductor material. The layer of semiconductor material is etched such that a thickness of the body is less than a thickness of the source and the drain and such that a recess is formed in the layer of semiconductor material over the body. A gate is formed at least in part in the recess. The gate defines a channel in the body and includes a gate electrode spaced apart from the body by a high-K gate dielectric.

Abstract: A substrate processing system includes a process chamber having a process station for processing a substrate in an ambience different from an atmosphere, a plurality of load-lock chambers each being connected to the process chamber through an opening/closing device and connected to the atmosphere through an opening/closing device, a first conveying device for conveying the substrate between the process chamber and the load-lock chambers, and a second conveying device for conveying the substrate between a supply station in the atmosphere and the load-lock chambers. Each of the load-lock chambers is arranged so that, prior to replacement of an ambience inside the load-lock chamber, the substrate is conveyed by the first conveying device from the load-lock chamber into the process chamber and then the substrate is conveyed into the load-lock chamber.

Abstract: Methods and apparatus for fabricating and cleaning in-process semi-conductor wafers are provided. An in-process wafer is placed within a closed chamber. A reactant gas is incorporated in a liquid solvent to form a “reactant mixture” that is capable of reacting with photoresist material (or other material) on a wafer surface to facilitate removal of the material from the wafer surface. The reactant mixture is condensed on one or more of the in-process wafer surfaces to form a thin film on the surface(s) of the wafer. The solvent in the reactant mixture acts as a transport medium to place the reactant gas on the wafer surface. The reactant gas is then able to react with the photoresist material (or other material) on the in-process wafer surface to effect removal the material. Following reaction of the reactant gas with the photoresist, the thin film of reactant mixture is removed from the wafer surface by flash heating, rinsing, draining, or other suitable means.

Abstract: A process for etching a substrate and removing etch residue deposited on the surfaces in the etching chamber has two stages. In the first stage, an energized first process gas is provided in the chamber, and in the second stage, an energized second process gas is provided in the chamber. The energized first process gas comprises SF6 and Ar, the volumetric flow ratio of SF6 to other components of the first process gas being from about 5:1 to about 1:10. The energized second process gas comprises CF4 and Ar, the volumetric flow ratio of CF4 to other components of the second process gas being from about 1:0 to about 1:10.

Abstract: The present invention generally provides an improved apparatus and method for removing an edge bead from a substrate. The apparatus includes a processing chamber having an edge bead removal fluid distribution system positioned therein and a substrate support member positioned in the processing chamber proximate the fluid distribution system. The substrate support member generally includes an upper substrate support surface having a plurality of fluid dispensing apertures formed therein, at least three capillary ring support posts radially positioned about a perimeter of the upper substrate support surface, and a annular capillary ring having a planar upper surface rigidly mounted to the capillary ring support posts.

Abstract: A processing chamber having an improved sealing means is disclosed. The processing chamber comprises a lower element, an upper element, and a sealing means that tightly holds the lower element to the upper element to define a processing volume that is maintained using the minimum pressure necessary. The processing chamber comprises a plate having a first face that forms the processing volume and a second, opposing face that forms a seal-energizing cavity. In one embodiment, a surface area of the first face is smaller than a surface area of the second face. When the same pressure is applied against both the first face and the second face, the force on the second face is greater than the force on the first face, resulting in a sealing force exceeding a processing force generated within the processing volume.

Abstract: A process of forming a via through a inter-level dielectric layer and the product. The via is formed by etching a via hole through the inter-level dielectric layer in an area overlying a conductive feature, such a lower copper metallization. Atomic layer deposition (ALD) forms a very thin refractory metal nitride barrier layer over the sidewalls and bottom of the via. Its thickness is less than 1.5 nm, and may be formed with no more than six ALD cycle. A copper seed layer is sputtered onto the barrier including the bottom portion, and copper is electrochemically filled into the hole. The barrier is thin enough to have a low electrical resistance, as may be explained by electronic quantum mechanical tunneling. Further, the crystallography and defects of the underlying copper continue across the thin barrier into the overlying copper.

Abstract: Methods for reducing contamination of semiconductor substrates after processing are provided. The methods include heating the processed substrate to remove adsorbed chemical species from the substrate surface by thermal desorption. Thermal desorption can be performed either in-situ or ex-situ. The substrate can be heated by convection, conduction, and/or radiant heating. The substrate can also be heated by treating the surface of the processed substrate with an inert plasma during which treatment ions in the plasma bombard the substrate surface raising the temperature thereof. Thermal desorption can also be performed ex-situ by applying thermal energy to the substrate during transport of the substrate from the processing chamber and/or by transporting the substrate to a transport module (e.g., a load lock) or to a second processing chamber for heating. Thermal desorption during transport can be enhanced by purging an inert gas over the substrate surface.

Abstract: When etching is performed with respect to a silicon-containing material by using a dry etching apparatus having a dual power source, the application of bias power is initiated before oxidization proceeds at a surface of the silicon-containing material. Specifically, the application of the bias power is initiated before the application of source power is initiated. Alternatively, the source power and the bias power are applied such that the effective value of the source power reaches a second predetermined value after the effective value of the bias power reaches a first predetermined value.

Abstract: To reduce the edge roll off in a semiconductor wafering process, the wafer (110) is subject to a plasma etch with an edge underetch. The edge underetch is achieved by means of a wafer holder (410) that emits gas towards the wafer (e.g. a gas vortex) to draw the wafer towards the holder's body (460). The plasma impinges on the wafer surface (110.1) opposite to the body. Some of the gas emitted by the holder wraps around the wafer edge and dilutes the etchant near the wafer edge. Consequently, the etch proceeds slower near the edge (the edge is underetched). In some embodiments, the wafer is rotated around an axis (440) passing through the wafer to increase the underetch.

Abstract: A thermally zoned substrate holder including a substantially cylindrical base having top and bottom surfaces configured to support a substrate. A plurality of temperature control elements are disposed within the base. An insulator thermally separates the temperature control elements. The insulator is made from an insulting material having a lower coefficient of thermal conductivity than the base (e.g., a gas-or vacuum-filled chamber).

Abstract: A pattern forming method of the present invention for forming a predetermined pattern on a photosensitive resin film by (i) layering the photosensitive resin film on an inorganic thin film with which a plastic substrate is coated and (ii) exposing the photosensitive resin film via a photomask having the predetermined pattern in an exposing step is characterized by including the step of heating the plastic substrate having the inorganic thin film before the exposing step, a time from an end of the heating step to a start of the exposing step being managed to be not less than a predetermined time, in accordance with an asymptotic contracting behavior after the end of the heating step of the plastic substrate having the inorganic thin film. With this, it is possible to provide a pattern forming method capable of forming a plurality of patterns on a plastic substrate with high accuracy of superposition, and a display device manufactured using the same.

Abstract: An apparatus that automatically monitors speed and operating time of a semiconductor fabricating equipment lift that lifts a wafer cassette up/down. The apparatus automatically indicates operational state of the lift including lift speed time, use time after motor replacement and overhaul, and number of wafers processed, for confirmation by a worker.

Abstract: A method is disclosed for improving etch uniformity in deep silicon etching of a monocrystalline silicon wafer. Such method includes forming a pad dielectric layer on a wafer including monocrystalline silicon, forming a silicon layer over the pad dielectric layer, and then applying a clamp to an edge of the wafer. The silicon layer is then removed except in areas protected by the clamp. Thereafter, a hardmask layer is applied and patterned on the wafer; and the wafer is then directionally etched with the patterned hardmask to etch trenches in the monocrystalline silicon.

Abstract: A plasma processing chamber including a slip cast part having a surface thereof exposed to the interior space of the chamber. The slip cast part includes free silicon contained therein and a protective layer on the surface which protects the silicon from being attacked by plasma in the interior space of the chamber. The slip cast part can be made of slip cast silicon carbide coated with CVD silicon carbide. The slip cast part can comprise one or more parts of the chamber such as a wafer passage insert, a monolithic or tiled liner, a plasma screen, a showerhead, dielectric member, or the like. The slip cast part reduces particle contamination and reduces process drift in plasma processes such as plasma etching of dielectric materials such as silicon oxide.

Abstract: A method of reducing an electrical charge imbalance on a wafer process surface including providing a semiconductor wafer having a process surface including an upper most first material layer; cleaning the process surface according to a wafer cleaning process including at least one of spraying and scrubbing to produce an electrical charge imbalance at the process surface; and, subjecting the process surface to a nitrogen containing plasma treatment to at least partially neutralize the electrical charge imbalance.

Abstract: A method for determining the optimum number of conditioning wafers to be run following a wet clean of the walls of an RF plasma chamber 1 is based on an electrical precursor signal. Polymer build up on a plasma chamber wall during normal chamber conditioning is monitored by observing components of the fundamental RF signal. After a pre-determined number of wafers has been run, a predictive model is used to determine the total number of wafers needed to complete the conditioning cycle.

Abstract: A method is described for improving the exposure focus for modern steppers used in the lithography of semiconductor substrates such as wafers. A wafer is sawed from a semiconductor ingot in a particular direction relative to a reference point on the ingot. As a result of the sawing, a series of raised and recessed formations manifest on the surface of the wafer. After various layers have been added to the wafer and the photoresist layer is ready to be removed, the wafer is aligned with the stepper so that a dynamic focus area of the stepper is aligned with the formations and/or the sawing direction. Such alignment improves the critical dimension control and reduces variability in printing small geometry features during lithography, resulting in higher yields.

Abstract: A substrate inspection device for carrying out visual inspection of a front surface and a rear surface of a wafer W is provided with an arm 21 for holding the wafer W on pad mounting sections 21b through suction. The arm 21 is moved by an arm driving mechanism between a substrate conveying position and a substrate inspection position. The arm 21 is a flat plate partially cut away and having a bracelet-shape, while the pad mounting sections 21b are arranged at specified intervals on the surface of the arm 21. Clip members 24 are arranged at specified intervals on the arm 21 so as to prevent the wafer W dropping off from the arm 21. If the arm 21 is moved to the substrate inspection position, the clip members 24 move to a substrate dropping position. If the vacuum suction of the pad mounting sections 21b is impaired, the wafer W would drop off, but instead they come into contact with the clip members 24 and dropping is prevented.

Abstract: A method that includes flowing an inert gas into an interior of a single wafer process chamber to create a pressure in the interior that is greater than an ambient pressure; and maintaining the greater interior pressure during a wafer transfer with the single wafer process chamber.

Abstract: In plasma processing equipment having a vacuum processing chamber, a plasma generation means, a stage for loading a wafer to be processed in the vacuum processing chamber, an opposing electrode having an area almost equal to or wider than the aforementioned wafer which is installed opposite to the stage, and a bias power source for applying a high frequency bias to the wafer, a current path correction means is provided for correcting the current path part in the neighborhood of the outer periphery of the wafer among the high frequency current paths produced by the high frequency bias so as to be directed toward the wafer opposing surface of the opposing electrode.

Abstract: Deposition of ionized material at a beveled or non-flat edge of a semiconductor wafer and the etching by the ionized material at such edge is controlled in a high density plasma processing machine by surrounding the wafer with a conducting ring to affect sheath potential and deflecting the ions of the material in such a way that the deposition and etching rate changes in a controlled way over the region immediately adjacent the wafer edge. The ring may be biased in several ways to control the ion flux to the wafer edge.

Abstract: A semiconductor wafer is processed while being supported without mechanical contact. Instead, the wafer is supported by gas streams emanating from a large number of passages in side sections positioned very close to the upper and lower surface of the wafer. The gas heated by the side sections and the heated side sections themselves quickly heat the wafer to a desired temperature. Process gas directed to the “device side” of the wafer can be kept at a temperature that will not cause deposition on that side section, but yet the desired wafer temperature can be obtained by heating non-process gas from the other side section to the desired temperature. A plurality of passages around the periphery of the wafer on the non-processed side can be employed to provide purge gas flow that prevents process gas from reaching the non-processed side of the wafer and the adjacent area of that side section.

Abstract: A shield for protecting silicon wafers. The shield includes a plurality of single crystal shielding members having a lattice unit cell repeated substantially throughout. The unit cell has a periodic arrangement of atoms defining a set of lattice planes. The shielding members each include a pair of first interface surfaces having an orientation substantially aligned along one of the set of lattice planes. The shield also includes a plurality of single crystal structural members each having substantially the same lattice unit cell as that of the shielding members repeated substantially throughout. The structural members each include a pair of second interface surfaces having an orientation substantially aligned along the same one of the set of lattice planes. The plurality of shielding members and structural members are alternately bonded together at their respective first and second interface surfaces to define an enclosed area sized to receive the silicon wafers therein.

Abstract: A process for etching a substrate 25 in an etching chamber 105, and simultaneously removing etch residue deposited on the surfaces of the walls 110 and components of the etching chamber 105. In one version, a two-stage method of opening a nitride mask layer on the substrate includes a first stage of providing a highly chemically reactive process gas in the chamber 105 to etch the nitride layer 32 and/or an underlying oxide layer 34, and a second stage of providing a less chemically reactive process gas in the chamber to etch the nitride layer 32 and/or the oxide layer 34 at a slower rate than the first stage. The first and second stage process gases may each comprise a fluorine containing gas, with the fluorine ratio of the first gas higher than the fluorine ratio of the second gas.

Abstract: An apparatus for performing contaminant sensitive processing on a substrate. A substrate load chamber receives the substrate from an ambient contaminant laden environment, and isolates the substrate from the ambient contaminant laden environment. The substrate load chamber further forms a first environment of intermediate cleanliness around the substrate. A substrate pass through chamber receives the substrate from the substrate load chamber, and isolates the substrate from the intermediate cleanliness of the first environment of the substrate load chamber. The substrate pass through chamber further forms a second environment of high cleanliness around the substrate. A substrate transfer chamber receives the substrate from the substrate pass through chamber, and isolates the substrate from the high cleanliness of the second environment of the substrate pass through chamber.

Abstract: In a semiconductor device manufacturing method for processing a plurality of substrates by alternately repeating a pretreatment stage and a continuous substrate processing stage, the continuous substrate processing stage comprises the steps of: loading a substrate on a heater unit located at a substrate loading/unloading position, the heater unit supporting and heating the substrate; processing the loaded substrate after transferring the heater unit having thereon the loaded substrate to a substrate processing position; unloading the processed substrate; and repeating the loading step, the processing step and the unloading step until a set of substrates are processed, and wherein the pretreatment stage is carried out by maintaining the heater unit between the substrate loading/unloading position and the substrate processing position.

Abstract: A method is provided for preparing a substrate for processing in a chamber that has a substrate receiving portion. The substrate is positioned within the chamber in a location not on the substrate receiving portion. A gaseous flow is provided to the chamber, from which a plasma is struck to heat the substrate. After the substrate has been heated, it is moved to the substrate receiving portion for processing.

Abstract: A semiconductor processing system having a holding chamber coupled to a mainframe processing system and at least one loadlock chamber coupled to the holding chamber in which unprocessed wafers are transferred from the loadlock chamber to the holding chamber for subsequent processing by the mainframe system.

Abstract: A system and method for detachably securing a locking mechanism to a housing is provided. The locking mechanism comprises a cam ring, a retention ring and a plurality of locking elements. The cam ring and the retention ring are slidably coupled and concentric with respect to each other. The locking elements are movably disposed within the cam ring and the retention ring. When a rotational force is applied to the locking mechanism, the locking elements move between a first position and a second position. The housing is positioned adjacent the locking elements and concentric with the locking mechanism. In the second position, the locking elements engage an engagement mechanism on the housing.