Abstract: A method for fabricating a semiconductor device includes forming a plurality of mandrel cuts from a first set of mandrels of a base structure using lithography, surrounding the first set of mandrels and a second set of mandrels of the base structure with spacer material to form mandrel-spacer structures, forming a flowable material layer on exposed surfaces of the mandrel-spacer structures, and performing additional processing, including forming a plurality of dielectric trenches within the base structure based on patterns formed in the flowable material layer.

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures extending through the alternating stack. Each of the electrically conductive layers includes a stack of a compositionally graded diffusion barrier and a metal fill material portion, and the compositionally graded diffusion barrier includes a substantially amorphous region contacting the interface between the compositionally graded diffusion barrier and a substantially crystalline region that is spaced from the interface by the amorphous region. The substantially crystalline region effectively blocks atomic diffusion, and the amorphous region induces formation of large grains during deposition of the metal fill material portions.

Abstract: An OLED light emitting device includes a substrate, a thin film transistor, an anode, an organic light emitting layer, a cathode, and a smoothing layer. The smoothing layer is disposed between the organic light emitting layer and the cathode. This improves transmittance of the cathode, and further improves light-emitting performance of the OLEO light emitting device.

Abstract: Embodiments are disclosed for processing microelectronic workpieces having patterned structures to improve mandrel pull from spacers for multi-color patterning. The disclosed embodiments form patterned structures on a substrate including mandrels, form spacers adjacent the mandrels that are recessed such that a height of the spacers is less than the height of the mandrels, form protective caps over the spacers while exposing top surfaces of the mandrels, and remove the mandrels to leave a spacer pattern with cap protection. The remaining spacer pattern can then be transferred to underlying layers in additional process steps. The recessing of the spacers and formation of the protective caps tends to reduce or eliminate spacer damage suffered by prior solutions during mandrel pull from spacers for multi-color patterning.

Abstract: A method for fabricating semiconductor device includes the steps of: providing a substrate having a first region and a second region; forming a first fin-shaped structure on the first region and a second fin-shaped structure on the second region; forming a patterned mask on the second region; and performing a process to enlarge the first fin-shaped structure so that the top surfaces of the first fin-shaped structure and the second fin-shaped structure are different.

Abstract: Methods are disclosed herein for forming conductive patterns having small pitches. An exemplary method includes forming a metal line in a first dielectric layer. The metal line has a first dimension along a first direction and a second dimension along a second direction that is different than the first direction. The method includes forming a patterned mask layer having an opening that exposes a portion of the metal line along an entirety of the second dimension and etching the portion of the metal line exposed by the opening of the patterned mask layer until reaching the first dielectric layer. The metal line is thus separated into a first metal feature and a second metal feature. After removing the patterned mask layer, a barrier layer is deposited over exposed surfaces of the first metal feature and the second metal feature and a second dielectric layer is deposited over the barrier layer.

Abstract: A method is provided for manufacturing a field effect transistor that includes a gate insulating layer and an electrode including a first conductive film and a second conductive film successively laminated on a predetermined surface of the gate insulating layer. The method includes forming an oxide film including element A, which is an alkaline earth metal, and element B, which is at least one of Ga, Sc, Y and a lanthanide, as the gate insulating layer; forming a first conductive film that dissolves in an organic alkaline solution on the oxide film; forming a second conductive film on the first conductive film; etching the second conductive film with an etching solution having a higher etch rate for the second conductive film as compared with that for the first conductive film; and etching the first conductive film with the organic alkaline solution using the second conductive film as a mask.

Abstract: Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.

Abstract: Provided is a method of manufacturing a semiconductor device with which a trench shape having vertical, flat, and smooth side wall surfaces can be formed even at room temperature. A semiconductor substrate is placed on a sample stage which is kept at room temperature in a reaction container. A trench is formed in the semiconductor substrate by plasma etching that uses etching gas including oxygen and sulfur hexafluoride, while controlling the gas ratio of oxygen to sulfur hexafluoride so that the gas ratio is from 70% to 100%.

Abstract: An EUV lithographic structure and methods according to embodiments of the invention includes an EUV photosensitive resist layer disposed directly on an oxide hardmask layer, wherein the oxide hardmask layer is doped with dopant ions to form a doped oxide hardmask layer so as to improve adhesion between the EUV lithographic structure and the oxide hardmask. The EUV lithographic structure is free of a separate adhesion layer.

Abstract: A semiconductor device includes a substrate, an epitaxial channel structure and a gate structure. The epitaxial channel structure is located above the substrate. The epitaxial channel structure has a bottom and a top. The bottom is between the substrate and the top, and the bottom has a width less than that of the top.

Abstract: A method for manufacturing a semiconductor device includes providing a substrate structure. The method includes forming a lower sacrificial layer, a lower supporter layer, an upper sacrificial layer, and an upper supporter layer which are sequentially stacked on the substrate structure. The method includes forming a mask pattern on the upper supporter layer; forming an upper supporter pattern by etching the upper supporter layer using the mask pattern as an etch mask. The method includes forming a recess region penetrating the upper supporter pattern, the upper sacrificial layer, the lower supporter layer, and the lower sacrificial layer, and removing the lower sacrificial layer and the upper sacrificial layer. The mask pattern is removed during the process of forming the upper supporter pattern. And, when the process of forming the recess region ends, the upper supporter pattern remains.

Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.

Abstract: Disclosed is a plasma processing method for processing a workpiece that includes: a silicon-containing etching target layer, an organic film provided on the etching target layer, an antireflective film provided on the organic layer, and a first mask provided on the antireflective layer, using a plasma processing apparatus having a processing container. The plasma processing method includes: etching the antireflective film using plasma generated in the processing container and the first mask to form a second mask from the antireflective film; etching the organic film using plasma generated in the processing container and the second mask to form a third mask from the organic film; generating plasma of a mixed gas including the first gas and the second gas in the processing container; and etching the etching target layer using plasma generated in the processing container and the third mask.

Abstract: An embodiment is a FinFET device. The FinFET device comprises a fin, a first source/drain region, a second source/drain region, and a channel region. The fin is raised above a substrate. The first source/drain region and the second source/drain region are in the fin. The channel region is laterally between the first and second source/drain regions. The channel region has facets that are not parallel and not perpendicular to a top surface of the substrate.

Abstract: Methods of fabricating semiconductor devices may include forming a hardmask layer including a photosensitive hardmask material on lower structures. The hardmask layer may include a lower portion and an upper portion thereon. An exposing and developing process may be performed on the hardmask layer to remove the upper portion of the hardmask layer and thereby form a hardmask structure with a substantially flat top surface.

Abstract: A method of forming high density contact array is disclosed. The method includes providing a first dielectric layer and forming a hard mask stack over the first dielectric layer. The hard mask stack includes first, second and third hard mask layers. The first and second hard mask layers are processed to form high density array of hard mask stack structures using a double patterning process. The hard mask stack structures include patterned first and second hard mask layers having a first width F1. The width of the patterned second hard mask layers is reduced to a second width F2 to form high density array of hard mask posts. A fourth hard mask layer is formed over the third hard mask layer and surrounding the hard mask posts. The hard mask posts and portions of the third hard mask layer and first dielectric layer underlying the hard mask posts are removed to form high density contact hole array.

Abstract: An apparatus includes a semiconductor substrate having a plurality of fins, wherein the plurality of fins includes a first group of fins and a second group of fins. The apparatus further includes a high fin density area on the semiconductor substrate including a first dielectric between the first group of fins in the high fin density area, said first dielectric having a first dopant concentration. The apparatus further includes a low fin density area on the semiconductor substrate including a second dielectric between the second group of fins in the low fin density area, said second dielectric having a second dopant concentration. The first dielectric and the second dielectric are a same material as deposited and the first dopant concentration and the second dopant concentration are different.

Abstract: To provide a semiconductor device which occupies a small area and is highly integrated. A first conductive layer is formed; a first insulating layer is formed over the first conductive layer; a second conductive layer is formed over the first insulating layer using the same material as the first conductive layer; a third conductive layer is formed over the second conductive layer; a second insulating layer is formed over the third conductive layer; a resist mask is formed over the second insulating layer; etching is successively performed from the upper layer and an opening is formed in the first conductive layer and the diameter of the opening in the second conductive layer is increased in the same step; and a contact hole where an upper surface of the first conductive layer is exposed is formed by etching the first insulating layer.

Abstract: A method for anisotropically etching a feature in a Cu-containing layer includes providing a substrate having a Cu-containing layer and a patterned etch mask formed on the Cu-containing layer such that on exposed Cu-containing layer is exposed to processing through the patterned etch mask, passivating a first surface of the exposed Cu-containing layer, and inhibiting passivation of a second surface of the Cu-containing layer. A Cu compound is formed on said second surface of the Cu-containing layer, and the Cu compound is removed from the second surface of the Cu-containing layer to anisotropically etch a feature in the Cu-containing layer.

Abstract: A method of forming a buried word line structure is provided. A first mask layer, an interlayer and a second mask layer are sequentially formed on a substrate, wherein the second mask layer has a plurality of mask patterns and a plurality of gaps arranged alternately, and the gaps includes first gaps and second gaps arranged alternately. A dielectric pattern is formed in each first gap and spacers are simultaneously formed on sidewalls of each second gap, wherein a first trench is formed between the adjacent spacers and exposes a portion of the first mask layer. The mask patterns are removed to form second trenches. An etching process is performed by using the dielectric patterns and the spacers as a mask, so that the first trenches are deepened to the substrate and the second trenches are deepened to the first mask layer.

Abstract: A method of making a semiconductor structure includes forming a select gate and a charge storage layer in an NVM region. A control gate is formed by depositing a conformal layer followed by an etch back. A patterned etch results in leaving a portion of the charge storage layer over the select gate and under the control gate and to remove the charge storage layer from the logic region. A logic gate structure formed in a logic region has a metal work function surrounded by an insulating layer.

Abstract: A method of manufacturing a semiconductor device includes: forming a conductive film on a semiconductor substrate; patterning the conductive film in a memory region to form a first gate electrode; after forming the first gate electrode, forming a mask film above each of the conductive film in a logic region and the first gate electrode; removing the mask film in the logic region; forming a first resist film above the mask film left in the memory region and above the conductive film left in the logic region; and forming a second gate electrode in the logic region by etching the conductive film using the first resist film as a mask.

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming fin structures in a selected area of a semiconductor substrate. The method includes covering the fin structures and the semiconductor substrate with a mask and forming a trench in the mask to define no more than two exposed fin structures in the selected area. Further, the method includes removing the exposed fin structures to provide the selected area with a desired number of fin structures.

Abstract: A method for the manufacture of a semiconductor device is provided, including the steps of providing a semiconductor substrate including a first area separated from a second area by a first isolation region, wherein the second area includes an intermediate transistor comprising a gate electrode, forming an oxide layer over the first and second areas, forming an optical planarization layer (OPL) over the oxide layer, forming a mask layer over the OPL in the first area without covering the OPL in the second area, and etching the OPL with the mask layer being present to expose the oxide layer over the gate electrode of the transistor.

Abstract: According to one embodiment, a method of manufacturing a semiconductor device includes forming a first line pattern comprising a first film above an underlying layer, depositing a second film on a sidewall and a top surface of the first line pattern of the first film, etching the second film to eliminate the second film on the top surface of the first line pattern of the first film and leave the second film on the sidewall of the first line pattern of the first film, and removing the first line pattern to form a second line pattern of the second film above the underlying layer. The depositing the second film, etching the second film, and removing the first line pattern are sequentially performed within the same plasma processing device.

Abstract: Narrow word lines are formed in a NAND flash memory array using a double patterning process in which sidewall spacers define word lines. Sidewall spacers also define edges of select gates so that spacing between a select gate and the closest word line is equal to spacing between adjacent word lines.

Abstract: A method of plasma etching a silicon carbide workpiece includes forming a mask on a surface of the silicon carbide workpiece, performing an initial plasma etch on the masked surface using a first set of process conditions, wherein the plasma is produced using an etchant gas mixture which includes i) oxygen and ii) at least one fluorine rich gas which is present in the etchant gas mixture at a volume ratio of less than 50%, and subsequently performing a bulk plasma etch process using a second set of process conditions which differ from the first set of process conditions.

Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.

Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.

Abstract: Embodiments include a method comprising depositing a hard mask layer over a first layer, the hard mask layer including; lower hard mask layer, hard mask stop layer, and upper hard mask. The hard mask layer and the first layer are patterned and a spacer deposited on the patterned sidewall. The upper hard mask layer and top portion of the spacer are removed by selective etching with respect to the hard mask stop layer, the remaining spacer material extending to a first predetermined position on the sidewall. The hard mask stop layer is removed by selective etching with respect to the lower hard mask layer and spacer. The first hard mask layer and top portion of the spacer are removed by selectively etching the lower hard mask layer and the spacer with respect to the first layer, the remaining spacer material extending to a second predetermined position on the sidewall.

Abstract: The disclosure relates generally to a method for fabricating a patterned medium. The method includes providing a substrate with an exterior layer under a lithographically patterned surface layer, the lithographically patterned surface layer comprising a first pattern in a first region and a second pattern in a second region, applying a first masking material over the first region, transferring the second pattern into the exterior layer in the second region, forming self-assembled block copolymer structures over the lithographically patterned surface layer, the self-assembled block copolymer structures aligning with the first pattern in the first region, applying a second masking material over the second region, transferring the polymer block pattern into the exterior layer in the first region, and etching the substrate according to the second pattern transferred to the exterior layer in the second region and the polymer block pattern transferred to the exterior layer in the first region.

Abstract: A method for etching features in a stack is provided. A combination hardmask is formed by forming a first hardmask layer comprising carbon or silicon oxide over the stack, forming a second hardmask layer comprising metal over the first hardmask layer, and patterning the first and second hardmask layers. The stack is etched through the combination hardmask.

Abstract: A lower layer of a microelectronic device may be patterned by forming a first sacrificial layer on the lower layer; patterning a plurality of spaced apart trenches in the first sacrificial layer; forming a second sacrificial layer in the plurality of spaced apart trenches; patterning the second sacrificial layer in the plurality of spaced apart trenches to define upper openings in the plurality of spaced apart trenches; and patterning the lower layer using the first and second sacrificial layers as a mask to form lower openings in the lower layer.

Abstract: A method for forming patterns of dense conductor lines and their contact pads is described. Parallel base line patterns are formed over a substrate. Each of the base line patterns is trimmed. Derivative line patterns and derivative transverse patterns are formed as spaces on the sidewalls of the trimmed base line patterns, wherein the derivative transverse patterns are formed between the ends of the derivative line patterns and adjacent to the ends of the trimmed base line patterns. The trimmed base line patterns are removed. At least end portions of the derivative line patterns are removed, such that the derivative line patterns are separated from each other and all or portions of the derivative transverse patterns become patterns of contact pads each connected with a derivative line pattern.

Abstract: A method of forming a pattern on a substrate comprises forming spaced, upwardly-open, cylinder-like structures projecting longitudinally outward of a base. Sidewall lining is formed over inner and over outer sidewalls of the cylinder-like structures, and that forms interstitial spaces laterally outward of the cylinder-like structures. The interstitial spaces are individually surrounded by longitudinally-contacting sidewall linings that are over outer sidewalls of four of the cylinder-like structures. Other embodiments are disclosed, including structure independent of method.

Abstract: A pattern formation method comprises a process of forming a resist pattern with an opening that exposes a first region of a glass film arranged on a substrate through a base film; a process of forming a neutralization film above the glass film; a process of forming a directed self-assembly material layer containing a first segment and a second segment above the glass film; a process of microphase separating the directed self-assembly material layer to form a directed self-assembly pattern containing a first part that includes the first segment and a second part that includes the second segment; and a process of removing either the first part or the second part and using the other as a mask to process the base film.

Abstract: Methods of fabricating ultra low-k dielectric self-aligned vias are described. In an example, a method of forming a self-aligned via (SAV) in a low-k dielectric film includes forming a trench pattern in a metal nitride hardmask layer formed above a low-k dielectric film formed above a substrate. A via pattern is formed in a masking layer formed above the metal nitride hardmask layer. The via pattern is etched at least partially into the low-k dielectric film, the etching comprising using a plasma etch using a chemistry based on CF4, H2, and a diluent inert gas composition.

Abstract: A multi-patterning method includes: patterning at least two first openings in a hard mask layer over a substrate using a first mask; forming spacers within two of the at least two first openings, each spacer having a spacer opening therein for patterning a respective first circuit pattern over the substrate, wherein each spacer defines a pattern-free region adjacent to a respective one of the at least two first circuit patterns, and patterning a second circuit pattern in the hard mask layer using a second mask. The second circuit pattern is located between and excluded from the pattern free regions adjacent the at least two first circuit patterns.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a film having different filling properties dependent on space width above the patterning film to cover the first line patterns and the second line patterns to form the film on the first line patterns and on the first inter-line pattern space while making a cavity in the first inter-line pattern space and to form the film on at least a bottom portion of the second inter-line pattern space and a side wall of each of the second line patterns. The method includes performing etch-back of the film to remove the film on the first line patterns and on the first inter-line pattern space while causing the film to remain on at least the side wall of the second line patterns.

Abstract: In a method for etching an organic film according to an embodiment, a target object that has an organic film is set in a processing chamber. Then, a processing gas containing COS gas and O2 gas is supplied to the processing chamber and a microwave for plasma excitation is supplied to the inside of the processing chamber to etch the organic film.

Abstract: Methods of fabricating semiconductor devices and semiconductor devices fabricated thereby are provided. Two photolithography processes and two spacer processes are performed to provide final patterns that have a pitch that is smaller than a limitation of photolithography process. Furthermore, since initial patterns are formed to have line and pad portions simultaneously by performing a first photolithography process, there is no necessity to perform an additional photolithography process for forming the pad portion.

Abstract: A method of forming a pattern on a substrate includes forming spaced first features derived from a first lithographic patterning step. Sidewall spacers are formed on opposing sides of the first features. After forming the sidewall spacers, spaced second features derived from a second lithographic patterning step are formed. At least some of individual of the second features are laterally between and laterally spaced from immediately adjacent of the first features in at least one straight-line vertical cross-section that passes through the first and second features. After the second lithographic patterning step, all of only some of the sidewall spacers in said at least one cross-section is removed.

Abstract: A semiconductor device manufacturing method for etching a substrate having a multilayer film formed by alternately stacking a first film and a second film, and a photoresist layer to form a step-shaped structure is provided. The step-shaped structure is formed by repeatedly performing a first step of plasma-etching the first film by using the photoresist layer as a mask, a second step of exposing the photoresist layer formed on the substrate to a plasma generated from a processing gas containing argon gas and hydrogen gas by applying a high frequency power to a lower electrode while applying a negative DC voltage to an upper electrode, a third step of trimming the photoresist layer, and a fourth step of plasma-etching the second film.

Abstract: The present invention is a silicon-containing resist underlayer film-forming composition containing a condensation product and/or a hydrolysis condensation product of a mixture comprising: one or more kinds of a compound (A) selected from the group consisting of an organic boron compound shown by the general formula (1) and a condensation product thereof and one or more kinds of a silicon compound (B) shown by the general formula (2). Thereby, there can be provided a silicon-containing resist underlayer film-forming composition being capable of forming a pattern having a good adhesion, forming a silicon-containing film which can be used as a dry-etching mask between a photoresist film which is the upperlayer film of the silicon-containing film and an organic film which is the underlayer film thereof, and suppressing deformation of the upperlayer resist during the time of dry etching of the silicon-containing film; and a patterning process.

Abstract: An illustrative test structure is disclosed herein that includes a plurality of first line features and a plurality of second line features. In this embodiment, each of the second line features have first and second opposing ends and the first and second line features are arranged in a grating pattern such that the first ends of the first line features are aligned to define a first side of the grating structure and the second ends of the first features are aligned to define a second side of the grating structure that is opposite the first side of the grating structure. The first end of the second line features has a first end that extends beyond the first side of the grating structure while the second end of the second line features has a first end that extends beyond the second side of the grating structure.

Abstract: A groove shape can be improved. A plasma etching method includes plasma-processing a photoresist film that is formed on a mask film and has a preset pattern; exposing an organic film formed under the mask film by etching the mask film with the pattern of the plasma-processed photoresist film; and etching the organic film by plasma of a mixture gas containing O2 (oxygen), COS (carbonyl sulfate) and Cl2 (chlorine).

Abstract: A method for manufacturing a device having a concavo-convex structure includes forming an organic resist film on an n-type semiconductor layer in which a fine concavo-convex structure is to be formed; forming a silicon-containing resist film on the organic resist film; patterning the silicon-containing resist film by nanoimprint; oxidizing the silicon-containing resist film with oxygen-containing plasma to form a silicon oxide film; dry-etching the organic resist film by using the silicon oxide film as an etching mask; dry-etching the n-type semiconductor layer by using the silicon oxide film and the organic resist film as an etching masks; and removing the silicon oxide film and the organic resist film.

Abstract: Some embodiments provide microelectronic fabrication methods in which a sacrificial pattern is formed on a substrate. A spacer formation layer is formed on the substrate, the spacer formation layer covering the sacrificial pattern. The spacer formation layer is etched to expose an upper surface of the sacrificial pattern and to leave at least one spacer on at least one sidewall of the sacrificial pattern. A first portion of the sacrificial pattern having a first width is removed while leaving intact a second portion of the sacrificial pattern having a second width greater than the first width to thereby form a composite mask pattern including the at least one spacer and a portion of the sacrificial layer. An underlying portion of the substrate is etched using the composite mask pattern as an etching mask.

Abstract: An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.