Abstract: The present invention provides a method of forming via holes. First, a substrate is provided. A plurality of first areas is defined on the substrate. A dielectric layer and a blocking layer are formed on the substrate. A patterned photoresist layer is formed on the blocking layer. The patterned photoresist layer includes a plurality of holes arranged in a regular array wherein the area of the hole array is greater than those of the first areas. The blocking layer in the first areas is removed by using the patterned photoresist layer as a mask. Lastly, the dielectric layer is patterned to form at least a via hole in the dielectric layer in the first area.

Abstract: A method of patterning a substrate comprises providing an array of resist features defined by a first pitch and a first gap width between adjacent resist features. Particles are introduced into the array of resist features, wherein the array of resist features becomes hardened. The introduction of particles may cause a reduction in critical dimension of the resist features. Sidewalls are provided on side portions of hardened resist features. Subsequent to the formation of the sidewalls, the hardened resist features are removed, leaving an array of isolated sidewalls disposed on the substrate. The sidewall array provides a mask for double patterning of features in the substrate layers disposed below the sidewalls, wherein an array of features formed in the substrate has a second pitch equal to half that of the first pitch.

Abstract: An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.

Abstract: A gap embedding composition used for embedding a patterned gap formed between photosensitive resin film portions on a semiconductor substrate surface, the gap embedding composition, at least having: a hydrolysis condensate of an aryloxysilane raw material; and an aromatic compound, as a solvent.

Abstract: A method for providing a shrink etch in which the features to be etched in a target layer have major and minor dimensions with the major dimension larger than the minor dimension. In the shrink etch of a mask, the dimensions are reduced from that of a patterned resist of the mask, however, with conventional techniques, the shrink etch undesirably shrinks by a greater amount in the major axis dimension. By treating the resist prior to the shrink etch, the shrinking is made more uniform, and if desired in accordance with processes herein, the amount of shrinkage in the major axis can be the same as or less than that in the minor axis direction.

Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

Abstract: A method for fabricating a semiconductor device includes: forming an interlayer insulating film on a substrate; forming a first hard mask formation film on the interlayer insulating film; altering the first hard mask formation film; after the altering of the first hard mask formation film, transferring an interconnect groove pattern to the altered first hard mask formation film to form a first hard mask made of the altered first hard mask formation film; and etching the interlayer insulating film using the first hard mask to form an interconnect groove in the interlayer insulating film. The first hard mask formation film is made of a metal film or a metallic compound film.

Abstract: A method for forming vias and trenches for an interconnect structure on a substrate includes exposing via pitch reduction patterns in a photoresist layer, developing the patterns to remove the via pitch reduction patterns, etching the photoresist layer partially using a polymer gas to reshape the pattern into small via shapes, and etching the remaining photoresist layer to extend the reshaped pattern. The reshaped small via shape patterns have a smaller pitch than the via pitch reduction patterns in a long direction. For via pitch reduction patterns having two vias each, the pattern has a peanut-shape. During the reshaping etch operation, the polymer gas deposits more in a pinched-in middle section while allowing downward etch in unpinched sections.

Abstract: An improved method of performing sidewall spacer imager transfer is presented. The method includes forming a set of sidewall spacers next to a plurality of mandrels, the set of sidewall spacers being directly on top of a hard-mask layer; transferring image of at least a portion of the set of sidewall spacers to the hard-mask layer to form a device pattern; and transferring the device pattern from the hard-mask layer to a substrate underneath the hard-mask layer.

Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.

Abstract: A method for fabricating a structure in magnetic recording head is described. First and second hard mask layers are provided on the layer(s) for the structure. A BARC layer and photoresist mask having a pattern are provided on the second hard mask layer. The pattern includes a line corresponding to the structure. The pattern is transferred to the BARC layer and the second hard mask layer in a single etch using an etch chemistry. At least the second hard mask layer is trimmed using substantially the same first etch chemistry. A mask including a hard mask line corresponding to the line and less than thirty nanometers wide is thus formed. The pattern of the second hard mask is transferred to the first hard mask layer. The pattern of the first hard mask layer is transferred to the layer(s) such that the structure has substantially the width.

Abstract: A method of forming at least one metal or metal alloy feature in an integrated circuit is provided. In one embodiment, the method includes providing a material stack including at least an etch mask located on a blanker layer of metal or metal alloy. Exposed portions of the blanket layer of metal or metal alloy that are not protected by the etch mask are removed utilizing an etch comprising a plasma that forms a polymeric compound and/or complex which protects a portion of the blanket layer of metal or metal alloy located directly beneath the etch mask during the etch.

Abstract: A mask for use in fabricating one or more semiconductor devices is fabricated by: providing sacrificial spacing structures disposed over a substrate structure, and including protective hard masks at upper surfaces of the spacing structures; disposing a sidewall spacer layer conformally over the sacrificial spacing structures; selectively removing the sidewall spacer layer from above the sacrificial spacing structures to expose the protective hard masks of the spacing structures, the selectively removing including leaving sidewall spacers along sidewalls of the sacrificial spacing structures; providing a protective material over the substrate structure; and removing the exposed protective hard masks from the sacrificial spacing structures, and thereafter, removing remaining sacrificial spacing structures and the protective material, leaving the sidewall spacers over the substrate structure as a mask.

Abstract: Multiple pitch-multiplied spacers are used to form mask patterns having features with exceptionally small critical dimensions. One of each pair of spacers formed mandrels is removed and alternating layers, formed of two mutually selectively etchable materials, are deposited around the remaining spacers. Layers formed of one of the materials are then etched, leaving behind vertically-extending layers formed of the other of the materials, which form a mask pattern. Alternatively, instead of depositing alternating layers, amorphous carbon is deposited around the remaining spacers followed by a plurality of cycles of forming pairs of spacers on the amorphous carbon, removing one of the pairs of spacers and depositing an amorphous carbon layer. The cycles can be repeated to form the desired pattern. Because the critical dimensions of some features in the pattern can be set by controlling the width of the spaces between spacers, exceptionally small mask features can be formed.

Abstract: The disclosure relates to a method for making a grating. The method includes the following steps. First, a substrate is provided. Second, a photoresist film is formed on a surface of the substrate. Third, a nano-pattern is formed on the photoresist film by nano-imprint lithography. Fourth, the photoresist film is etched to form a patterned photoresist layer. Fifth, a mask layer is covered on the patterned photoresist layer and the surface of the substrate exposed to the patterned photoresist layer. Sixth, the patterned photoresist layer and the mask layer thereon are removed to form a patterned mask layer. Seventh, the substrate is etched through the patterned mask layer by reactive ion etching, wherein etching gases includes carbon tetrafluoride (CF4), sulfur hexafluoride (SF6) and argon (Ar2). Finally, the patterned mask layer is removed.

Abstract: Hardmask films having high hardness and low stress are provided. In some embodiments a film has a stress of between about ?600 MPa and 600 MPa and hardness of at least about 12 GPa. In some embodiments, a hardmask film is prepared by depositing multiple sub-layers of doped or undoped silicon carbide using multiple densifying plasma post-treatments in a PECVD process chamber. In some embodiments, a hardmask film includes a high-hardness boron-containing film selected from the group consisting of SixByCz, SixByNz, SixByCzNw, BxCy, and BxNy. In some embodiments, a hardmask film includes a germanium-rich GeNx material comprising at least about 60 atomic % of germanium. These hardmasks can be used in a number of back-end and front-end processing schemes in integrated circuit fabrication.

Abstract: Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

Abstract: Embodiments of the present invention provides methods to etching a mask layer, e.g., an absorber layer, disposed in a film stack for manufacturing a photomask in EUV applications and phase shift and binary photomask applications. In one embodiment, a method of etching an absorber layer disposed on a photomask includes transferring a film stack into an etching chamber, the film stack having a chromium containing layer partially exposed through a patterned photoresist layer, providing an etching gas mixture including Cl2, O2 and at least one hydrocarbon gas in to a processing chamber, wherein the Cl2 and O2 is supplied at a Cl2:O2 ratio greater than about 9, supplying a RF source power to form a plasma from the etching gas mixture, and etching the chromium containing layer through the patterned photoresist layer in the presence of the plasma.

Abstract: Methods for fabricating integrated circuits are provided herein. In an embodiment, a method for fabricating an integrated circuit includes providing a mandrel layer overlying a semiconductor substrate and patterning the mandrel layer into mandrel structures. The method further includes forming a protective layer between the mandrel structures. Spacers are formed around each of the mandrel structures and overlying the protective layer to define exposed regions of the protective layer and covered regions of the protective layer. The exposed regions of the protective layer are etched using the spacers and the mandrel structures as a mask. The spacers are removed from the covered regions of the protective layer. The covered regions of the protective layer form mask segments for etching the semiconductor substrate. The method removes the mandrel structures and etches the semiconductor substrate exposed between mask segments to form semiconductor fin structures.

Abstract: A method of forming a pattern on a substrate includes forming spaced features over a substrate. A polymer is adsorbed to outer lateral surfaces of the spaced features. Either material of the spaced features is removed selectively relative to the adsorbed polymer or material of the adsorbed polymer is removed selectively relative to the spaced features to form a pattern on the substrate. In one embodiment, the polymer is of known chain length and has opposing longitudinal ends. One of the longitudinal ends of the polymer adsorbs to the outer lateral surfaces whereby the adsorbed polymer projects lengthwise from the outer lateral surfaces, with said chain length defining a substantially uniform lateral thickness of the adsorbed polymer on the spaced features. Additional embodiments are contemplated.

Abstract: A method of forming features in a porous low-k dielectric layer disposed below a patterned organic mask is provided. Features are etched into the porous low-k dielectric layer through the patterned organic mask, and then the patterned organic mask is stripped. The stripping of the patterned organic mask includes providing a stripping gas comprising COS, forming a plasma from the stripping gas, and stopping the stripping gas. A cap layer may be provided between the porous low-k dielectric layer and the patterned organic mask. The stripping of the patterned organic mask leaves the cap layer on the porous low-k dielectric layer.

Abstract: A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.

Abstract: A method for profiling a film stack includes receiving a film stack having an insulation layer, a dielectric hard mask layer, and a patterned metal hard mask layer. The pattern in the patterned metal hard mask layer is transferred to the dielectric hard mask layer using a first dry etching process. The pattern in the dielectric hard mask layer is then transferred to the insulation layer using a second dry etching process including one or more halogen-containing gases. The second etching process etches the insulation layer and removes a portion of the patterned metal hard mask layer, which exposes a corner of the underlying dielectric hard mask layer. Portions of the dielectric hard mask layer that overhang the insulation layer are removed using a third dry etching process including a process composition that is more selective to the dielectric hard mask layer relative to the insulation layer.

Abstract: One illustrative method disclosed herein involves creating an overall target pattern that includes an odd-jogged feature with a crossover region that connects first and second line portions, wherein the crossover region has a first dimension in a first direction that is greater than a second dimension that is transverse to the first direction, decomposing the overall target pattern into a first sub-target pattern and a second sub-target pattern, wherein each of the sub-target patterns comprise a line portion and a first portion of the crossover region, and generating first and second sets of mask data corresponding to the first and second sub-target patterns, respectively.

Abstract: A method for manufacturing a magnetic write pole of a magnetic write head that achieves improved write pole definition reduced manufacturing cost and improves ease of photoresist mask re-work. The method includes the use of a novel bi-layer hard mask beneath a photoresist mask. The bi-layer mask includes a layer of silicon dielectric, and a layer of carbon over the layer of silicon dielectric. The carbon layer acts as an anti-reflective coating layer that is unaffected by the photolithographic patterning process used to pattern the write pole and also acts as an adhesion layer for resist patterning. In the event that the photoresist patterning is not within specs and a mask re-work must be performed, the bi-layer mask can remain intact and need not be removed and re-deposited. In addition, the low cost and ease of use silicon dielectric and carbon reduce manufacturing cost and increase throughput.

Abstract: A method for manufacturing a magnetic sensor that allows the sensor to be constructed with a very narrow track width and with smooth, well defined side walls. A tri-layer mask structure is deposited over a series of sensor layers. The tri-layer mask structure includes an under-layer, a Si containing hard mask deposited over the under-layer and a photoresist layer deposited over the Si containing hard mask. The photoresist layer is photolithographically patterned to define a photoresist mask. A first reactive ion etching is performed to transfer the image of the photoresist mask onto the Si containing hard mask. The first reactive ion etching is performed in a chemistry that includes CF4, CHF3, O2, and He. A second reactive ion etching is then performed in an oxygen chemistry to transfer the image of the Si containing hard mask onto the under-layer, and an ion milling is performed to define the sensor.

Abstract: A method of fabricating a substrate includes forming spaced first features over a substrate. An alterable material is deposited over the spaced first features and the alterable material is altered with material from the spaced first features to form altered material on sidewalls of the spaced first features. A first material is deposited over the altered material, and is of some different composition from that of the altered material. The first material is etched to expose the altered material and spaced second features comprising the first material are formed on sidewalls of the altered material. Then, the altered material is etched from between the spaced second features and the spaced first features. The substrate is processed through a mask pattern comprising the spaced first features and the spaced second features. Other embodiments are disclosed.

Abstract: The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.

Abstract: In an etching method of a multilayer film including a first oxide film and a second oxide film, a high frequency power in etching an organic film is set to be higher than those in etching a first and second oxide films, and high frequency bias powers in the etching of the first and second oxide films are set to be higher than that in the etching of the organic film. In the etching of the first and second oxide films and the organic film, a magnetic field is generated such that horizontal magnetic field components in a radial direction with respect to a central axis line of a target object have an intensity distribution having a peak value at a position far from the central axis line, and a position of the peak value in the etching of the organic film is closer to the central axis line.

Abstract: Some embodiments relate to a method for processing a workpiece. In the method, an anti-reflective coating layer is provided over the workpiece. A first patterned photoresist layer, which has a first photoresist tone, is provided over the anti-reflective coating layer. A second patterned photoresist layer, which has a second photoresist tone opposite the first photoresist tone, is provided over the first patterned photoresist layer. An opening extends through the first and second patterned photoresist layers to allow a treatment to be applied to the workpiece through the opening. Other embodiments are also disclosed.

Abstract: According to one embodiment, the invention relates to a method for the anisotropic etching of patterns in at least one layer to be etched through a hard mask comprising carbon in an inductive-coupling plasma etching reactor (ICP), the method being characterized in that the hard mask is made from boron doped with carbon (B:C), and in that, prior to the anisotropic etching of the patterns in said layer to be etched through the hard mask of carbon-doped boron (B:C), the following steps are performed: realization of an intermediate hard mask situated on a layer of carbon-doped boron intended to form the hard mask made from carbon-doped boron (B:C), etching of the layer of carbon-doped boron (B:C) through the intermediate hard mask in order to form the hard mask made from carbon-doped boron (B:C), the realization of the intermediate hard mask and the etching of the hard mask made from carbon-doped boron (B:C) being done in said inductive coupling plasma etching reactor (ICP).

Abstract: A double patterning process is described. A substrate having a first area and a second area is provided. A target layer is formed over the substrate. A patterned first photoresist layer is formed over the target layer, wherein the patterned first photoresist layer has openings and has a first thickness in the first area, and at least a portion of the patterned first photoresist layer in the second area has a second thickness less than the first thickness. A second photoresist layer is then formed covering the patterned first photoresist layer and filling in the openings.

Abstract: According to one embodiment, a method for manufacturing a semiconductor device includes forming a plurality of second core films, the second core film having a first array portion, and a second array portion which is arranged so as to be spaced at a larger second space than the first space in the first direction from the first array portion, the second space being positioned above the loop portion. The method includes processing the second film to be processed below the first array portion into a second line and space pattern which includes a second line pattern extending in the second direction, and removing the second film to be processed below the second space and the loop portion of the first film to be processed, by an etching using the second spacer film as a mask.

Abstract: A method of etching a substrate comprises forming on the substrate, a plurality of double patterning features composed of silicon oxide, silicon nitride, or silicon oxynitride. The substrate having the double patterning features is provided to a process zone. An etching gas comprising nitrogen tri-fluoride, ammonia and hydrogen is energized in a remote chamber. The energized etching gas is introduced into the process zone to etch the double patterning features to form a solid residue on the substrate. The solid residue is sublimated by heating the substrate to a temperature of at least about 100° C.

Abstract: A method for processing a target object includes arranging a first electrode and a second electrode for supporting the target object in parallel to each other in a processing chamber and processing the target object supported by the second electrode by using a plasma of a processing gas supplied into the processing chamber, the plasma being generated between the first electrode and the second electrode by applying a high frequency power between the first electrode and the second electrode. The target object includes an organic film and a photoresist layer formed on the organic film. The processing gas contains H2 gas, and the organic film is etched by a plasma containing H2 by using the photoresist layer as a mask while applying a negative DC voltage to the first electrode.

Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.

Abstract: A patterning method is provided. First, a substrate having an objective material layer thereon is provided. Thereafter, a mask layer is formed on the objective material layer. Afterwards, a patterned layer is formed over the mask layer, wherein a material of the patterned layer includes a metal-containing substance. Then, the mask layer is patterned to form a patterned mask layer. Further, the objective material layer is patterned, using the patterned mask layer as a mask.

Abstract: Some embodiments include a semiconductor construction having a pair of lines extending primarily along a first direction, and having a pair of contacts between the lines. The contacts are spaced from one another by a lithographic dimension, and are spaced from the lines by sub-lithographic dimensions. Some embodiments include a method of forming a semiconductor construction. Features are formed over a base. Each feature has a first type sidewall and a second type sidewall. The features are spaced from one another by gaps. Some of the gaps are first type gaps between first type sidewalls, and others of the gaps are second type gaps between second type sidewalls. Masking material is formed to selectively fill the first type gaps relative to the second type gaps. Excess masking material is removed to leave a patterned mask. A pattern is transferred from the patterned mask into the base.

Abstract: A method for patterning a plurality of features in a non-rectangular pattern on an integrated circuit device includes providing a substrate including a surface with a first layer and a second layer. Forming a plurality of elongated protrusions in a third layer above the first and second layers. Forming a first patterned layer over the plurality of elongated protrusions. The plurality of elongated protrusions are etched to form a first pattern of the elongated protrusions, the first pattern including at least one inside corner. Forming a second patterned layer over the first pattern of elongated protrusions and forming a third patterned layer over the first pattern of elongated protrusions. The plurality of elongated protrusions are etched using the second and third patterned layers to form a second pattern of the elongated protrusions, the second pattern including at least one inside corner.

Abstract: A method for forming small dimension openings in the organic masking layer of tri-layer lithography. The method includes forming an organic polymer layer over a semiconductor substrate; forming a silicon containing antireflective coating on the organic polymer layer; forming a patterned photoresist layer on the antireflective coating, the patterned photoresist layer having an opening therein; performing a first reactive ion etch to transfer the pattern of the opening into the antireflective coating to form a trench in the antireflective coating, the organic polymer layer exposed in a bottom of the trench; and performing a second reactive ion etch to extend the trench into the organic polymer layer, the second reactive ion etch forming a polymer layer on sidewalls of the trench, the second reactive ion etch containing a species derived from a gaseous hydrocarbon.

Abstract: A method of forming multiple different width dimension features simultaneously. The method includes forming multiple sidewall spacers of different widths formed from different combinations of conformal layers on different mandrels, removing the mandrels, and simultaneously transferring the pattern of the different sidewall spacers into an underlying layer.

Abstract: A three photomask image transfer method. The method includes using a first photomask, defining a set of mandrels on a hardmask layer on a substrate; forming sidewall spacers on sidewalls of the mandrels, the sidewall spacers spaced apart; removing the set of mandrels; using a second photomask, removing regions of the sidewall spacers forming trimmed sidewall spacers and defining a pattern of first features; forming a pattern transfer layer on the trimmed sidewall spacers and the hardmask layer not covered by the trimmed sidewall spacers; using a third photomask, defining a pattern of second features in the transfer layer, at least one of the second features abutting at least one feature of the pattern of first features; and simultaneously transferring the pattern of first features and the pattern of second features into the hardmask layer thereby forming a patterned hardmask layer.

Abstract: When a wiring structure is formed by a trench-first dual damascene method, a first hard mask for forming via holes and a second hard mask for forming wiring trenches are sequentially formed on an interlayer insulating film, openings are formed at the first hard mask while using the second hard mask as a mask, and thereafter, the openings are expanded in a lateral direction by an isotropic etching to form openings, via holes are formed by etching the interlayer insulating film while using the first hard mask and the second hard mask as masks, and wiring trenches communicating with the via holes are formed by etching the interlayer insulating film while using the second hard mask as a mask.

Abstract: A method of fabricating a substrate includes forming spaced first features and spaced second features over a substrate. The first and second features alternate with one another and are spaced relative one another. Width of the spaced second features is laterally trimmed to a greater degree than any lateral trimming of width of the spaced first features while laterally trimming width of the spaced second features. After laterally trimming of the second features, spacers are formed on sidewalls of the spaced first features and on sidewalls of the spaced second features. The spacers are of some different composition from that of the spaced first features and from that of the spaced second features. After forming the spacers, the spaced first features and the spaced second features are removed from the substrate. The substrate is processed through a mask pattern comprising the spacers. Other embodiments are disclosed.

Abstract: Hemispheres and spheres are formed and employed for a plurality of applications. Hemispheres are employed to form a substrate having an upper surface and a lower surface. The upper surface includes peaks of pillars which have a base attached to the lower surface. The peaks have a density defined at the upper surface by an array of hemispherical metal structures that act as a mask during an etch to remove substrate material down to the lower surface during formation of the pillars. The pillars are dense and uniform and include a microscale average diameter. The spheres are formed as independent metal spheres or nanoparticles for other applications.

Abstract: A method of high aspect ratio contact etching a substantially vertical contact hole in an oxide layer using a hard photoresist mask is described. The oxide layer is deposited on an underlying substrate. A plasma etching gas is formed from a carbon source gas. Dopants are mixed into the gas. The doped plasma etching gas etches a substantially vertical contact hole through the oxide layer by doping carbon chain polymers formed along the sidewalls of the contact holes during the etching process into a conductive state. The conductive state of the carbon chain polymers reduces the charge buildup along sidewalls to prevent twisting of the contact holes by bleeding off the charge and ensuring proper alignment with active area landing regions. The etching stops at the underlying substrate.

Abstract: The substrate is provided with a layer of first material, a first etching mask, a covering layer and a second etching mask. The covering layer has a covered main area and an uncovered secondary area. The secondary area of the covering layer is partially etched via the second etching mask to form a salient pattern. Lateral spacers are formed around the salient pattern defining a third etching mask. The second etching mask is eliminated. The covering layer is etched by means of the third etching mask to form a salient pattern in the covering layer and to uncover the first etching mask and the first material. The layer of first material is etched to form the pattern made from the first material.

Abstract: A method for etching a dielectric layer disposed below a patterned organic mask with features, with hardmasks at bottoms of some of the organic mask features is provided. An etch gas is provided. The etch gas is formed into a plasma. A bias RF with a frequency between 2 and 60 MHz is provided that provides pulsed bias with a pulse frequency between 10 Hz and 1 kHz wherein the pulsed bias selectively deposits on top of the organic mask with respect to the dielectric layer.

Abstract: A method for the selective removal of material from a substrate surface for forming a deepening includes the steps of applying a mask onto the substrate surface in accordance with the desired selective removal and dry-etching the substrate, a metal, preferably aluminum, being used as the masking material. Power may be coupled inductively to a plasma.

Abstract: A method of fabricating a semiconductor device may include forming spacer line patterns on sidewalls of photoresist. A planarization etching process may be performed on a subsequently added planarization layer, after forming a mesh-shaped mask pattern from the spacer line patterns.