Compound Semiconductor Patents (Class 438/718)
-
Patent number: 11538690Abstract: In certain embodiments, a method for processing a semiconductor substrate includes receiving a semiconductor substrate that includes a film stack. The film stack includes a first silicon layer, a second silicon layer, and a first germanium-containing layer positioned between the first silicon layer and the second silicon layer. The method further includes selectively etching the first germanium-containing layer by exposing the film stack to a plasma that includes fluorine agents, nitrogen agents, and hydrogen agents. The plasma etches the first germanium-containing layer and causes a passivation layer to be formed on exposed surfaces of the first silicon layer and the second silicon layer to inhibit etching of the first silicon layer and the second silicon layer during exposure of the film stack to the plasma.Type: GrantFiled: February 9, 2021Date of Patent: December 27, 2022Assignee: TOKYO ELECTRON LIMITEDInventors: Pingshan Luan, Aelan Mosden
-
Patent number: 10418250Abstract: An etching method using a remote plasma source (RPS) and a method of fabricating a semiconductor device, the etching method including generating a plasma by supplying a process gas to at least one RPS and applying power to the at least one RPS; and etching a first material film including SiNx by supplying the plasma and at least one control gas selected from HBr, HCl, HI, NH3, SiH4, CHF3, and CH2F2 to a process chamber.Type: GrantFiled: January 12, 2018Date of Patent: September 17, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Gon-jun Kim, Yuri Barsukov, Vladimir Volynets, Dali Liu, Sang-jin An, Beom-jin Yoo, Sang-heon Lee, Shamik Patel
-
Patent number: 10163647Abstract: A method for forming a deep trench structure is provided. The method includes forming a first recess in a top portion of a substrate and forming a first protective layer on sidewalls of the first recess. The method includes etching a middle portion of the substrate by using the first protective layer as a mask to form a second recess and forming a second protective layer on sidewalls of the second recess. The method also includes etching a bottom portion of the substrate by using the second protective layer as a mask to form a third recess; and removing the first protective layer and the second protective layer to form a deep trench structure. The deep trench structure is constructed by the first recess, the second recess and the third recess, and the deep trench structure has a stair shape.Type: GrantFiled: January 26, 2017Date of Patent: December 25, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Min-Ying Tsai, Cheng-Ta Wu, Yeur-Luen Tu
-
Patent number: 10134626Abstract: A semiconductor device is provided. The semiconductor device includes a doped isolation structure formed above a substrate, and the doped isolation structure includes a first doped portion and a second doped portion, and a doped concentration of the second doped portion is different from a doped concentration of the first doped portion. The semiconductor device also includes a first fin partially embedded in the doped isolation structure, and a sidewall surface of the first fin is in direct contact with the first doped portion. The semiconductor device includes a second fin partially embedded in the doped isolation structure, and the doped isolation structure is between the first fin and the second fin, and a sidewall surface of the second fin is in direct contact with the second doped portion.Type: GrantFiled: December 11, 2017Date of Patent: November 20, 2018Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tsung-Yu Chiang, Chung-Wei Lin, Kuang-Hsin Chen, Bor-Zen Tien
-
Patent number: 9984890Abstract: Isotropic silicon and silicon-germanium etching with tunable selectivity is described. The method includes receiving a substrate having a layer of silicon and a layer of silicon-germanium with sidewall surfaces of silicon and silicon-germanium being uncovered, positioning the substrate in a processing chamber configured for etching substrates, and modifying uncovered surfaces of silicon and silicon-germanium by exposing the uncovered surfaces of silicon and silicon-germanium to radical species.Type: GrantFiled: March 2, 2017Date of Patent: May 29, 2018Assignee: Tokyo Electron LimitedInventors: Subhadeep Kal, Kandabara N. Tapily, Aelan Mosden
-
Publication number: 20150126039Abstract: Methods of selectively etching silicon relative to silicon germanium are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor and a hydrogen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon. The plasmas effluents react with exposed surfaces and selectively remove silicon while very slowly removing other exposed materials. The methods are useful for removing Si(1-X)GeX faster than Si(1-Y)GeY, for X<Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.Type: ApplicationFiled: May 5, 2014Publication date: May 7, 2015Inventors: Mikhail Korolik, Nitin K. Ingle, Jingchun Zhang, Anchuan Wang, Jie Liu
-
Publication number: 20150126040Abstract: Methods of selectively etching silicon germanium relative to silicon are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the silicon germanium. The plasmas effluents react with exposed surfaces and selectively remove silicon germanium while very slowly removing other exposed materials. Generally speaking, the methods are useful for removing Si(1-X)GeX (including germanium i.e. X=1) faster than Si(1-Y)GeY, for all X>Y. In some embodiments, the silicon germanium etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.Type: ApplicationFiled: May 5, 2014Publication date: May 7, 2015Inventors: Mikhail Korolik, Nitin K. Ingle, Anchuan Wang, Jingjing Xu
-
Patent number: 9006111Abstract: A pattern-formation process including: providing a substrate material having on a major surface a difficult-to-access recess formed by a 1st mask; depositing a 2nd mask having a higher etching resistance than the 1st mask by physical evaporation on the upper surface of the 1st mask and peripherally on a side of the recess, the second mask forming a series of films; and etching the substrate material via the 1st and 2nd mask, wherein forming the 2nd mask includes depositing the 2nd mask material by physical evaporation vertically onto the major surface of the substrate material; and the recess is sized such that, upon deposition, the 2nd mask material cannot substantially reach the bottom of the recess. Accordingly, portions of the recesses formed by the etching masks can be processed by etching even when those recesses are 25 nm or less, and especially 20 nm or less in size.Type: GrantFiled: September 27, 2012Date of Patent: April 14, 2015Assignee: Dai Nippon Printing Co., Ltd.Inventors: Tsuyoshi Chiba, Yusuke Kawano, Yuki Aritsuka
-
Publication number: 20150099368Abstract: In a dry etching method for isotropically etching each of SiGe layers selectively relative to each of Si layers in a laminated film composed of the Si layers and SiGe layers alternately and repeatedly laminated, the each of the SiGe layers is plasma-etched with pulse-modulated plasma using NF3 gas.Type: ApplicationFiled: July 31, 2014Publication date: April 9, 2015Inventors: Ze SHEN, Tetsuo ONO, Hisao YASUNAMI
-
Patent number: 8941145Abstract: Systems and methods for dry eteching a photodetector array based on InAsSb are provided. A method for fabricating an array of photodetectors includes receiving a pattern of an array of photodetectors formed from InAsSb, the pattern including at least one trench defined between adjacent photodetectors, and dry etching the at least one trench with a plasma including BrCl3 and Ar.Type: GrantFiled: June 17, 2013Date of Patent: January 27, 2015Assignee: The Boeing CompanyInventor: Pierre-Yves Delaunay
-
Patent number: 8932406Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.Type: GrantFiled: March 15, 2013Date of Patent: January 13, 2015Assignee: Matheson Tri-Gas, Inc.Inventors: Glenn Mitchell, Ramkumar Subramanian, Carrie L. Wyse, Robert Torres, Jr.
-
Publication number: 20140357087Abstract: Provided are an apparatus and method for etching an organic layer, in which an organic material deposited in a non-layer forming area of a substrate is etched. The apparatus includes an etching chamber; a plasma generator configured to supply plasma into the etching chamber; a stage disposed in the etching chamber and configured to support the substrate; and a mask configured to guide the plasma toward the non-pixel area.Type: ApplicationFiled: September 17, 2013Publication date: December 4, 2014Applicant: Samsung Display Co., Ltd.Inventors: Yoshiaki SAKAMOTO, Nam Ha
-
Patent number: 8871647Abstract: A group III nitride substrate in one embodiment has a surface layer. The surface layer contains 3 at. % to 25 at. % of carbon and 5×1010 atoms/cm2 to 200×1010 atoms/cm2 of a p-type metal element. The group III nitride substrate has a stable surface.Type: GrantFiled: August 18, 2011Date of Patent: October 28, 2014Assignee: Sumitomo Electric Industries, Ltd.Inventor: Keiji Ishibashi
-
Publication number: 20140302683Abstract: The invention is directed to providing a dry etching agent having little effect on the global environment but having the required performance. Provided is a dry etching agent containing, each at a specific vol %: (A) a fluorine-containing unsaturated hydrocarbon represented by the formula CaFbHc (in the formula, a, b and c are each positive integers and satisfy the correlations of 2?a?5, c<b?1, 2a+2>b+c and b?a+c, excluding the case where a=3, b=4 or c=2); (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2, COF2, F2, NF3, Cl2, Br2, I2, and YFn (where Y is Cl, Br or I and n is an integer of 1 to 5); and (C) at least one kind of gas selected from the group consisting of N2, He, Ar, Ne, Xe, and Kr.Type: ApplicationFiled: June 13, 2012Publication date: October 9, 2014Applicant: Central Glass Company, LimitedInventors: Akiou Kikuchi, Tomonori Umezaki, Yasuo Hibino, Isamu Mori, Satoru Okamoto
-
Patent number: 8841220Abstract: The light extraction surface of a nitride semiconductor light-emitting element, including a crystal plane other than a c plane, is subjected to a surface modification process to control its wettability, and then covered with a layer of fine particles. By etching that layer of fine particles after that, an unevenness structure, in which roughness curve elements have an average length (RSm) of 150 nm to 800 nm, is formed on the light extraction surface.Type: GrantFiled: May 13, 2013Date of Patent: September 23, 2014Assignee: Panasonic CorporationInventors: Masaki Fujikane, Akira Inoue, Toshiya Yokogawa
-
Publication number: 20140273491Abstract: A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.Type: ApplicationFiled: May 27, 2014Publication date: September 18, 2014Applicant: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Yunyu Wang, Young Lee
-
Patent number: 8815720Abstract: A workpiece is implanted to a first depth to form a first amorphized region. This amorphized region is then etched to the first depth. After etching, the workpiece is implanted to a second depth to form a second amorphized region below a location of the first amorphized region. The second amorphized region is then etched to the second depth. The implant and etch steps may be repeated until structure is formed to the desired depth. The workpiece may be, for example, a compound semiconductor, such as GaN, a magnetic material, silicon, or other materials.Type: GrantFiled: April 5, 2012Date of Patent: August 26, 2014Assignee: Varian Semiconductor Equipment Associates, Inc.Inventors: Ludovic Godet, Morgan D. Evans, Chi-Chun Chen
-
Patent number: 8791025Abstract: The method of producing a GaN-based microstructure includes a step of preparing a semiconductor structure provided with a trench formed in a main surface of the nitride semiconductor and a heat-treating mask covering a main surface of the nitride semiconductor excluding the trench, a first heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to form a crystallographic face of the nitride semiconductor on at least a part of a sidewall of the trench, a step of removing the heat-treating mask after the first heat-treatment step and a second heat-treatment step of heat-treating the semiconductor structure under an atmosphere containing nitrogen element to close an upper portion of the trench on the sidewall of which the crystallographic face is formed with a nitride semiconductor.Type: GrantFiled: July 27, 2010Date of Patent: July 29, 2014Assignee: Canon Kabushiki KaishaInventors: Shoichi Kawashima, Takeshi Kawashima, Yasuhiro Nagatomo, Katsuyuki Hoshino
-
Patent number: 8790530Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.Type: GrantFiled: February 10, 2010Date of Patent: July 29, 2014Assignee: Spansion LLCInventors: Angela T. Hui, Gang Xue
-
Patent number: 8772172Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.Type: GrantFiled: July 22, 2013Date of Patent: July 8, 2014Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
-
Patent number: 8771536Abstract: A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.Type: GrantFiled: October 24, 2011Date of Patent: July 8, 2014Assignee: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Yunyu Wang, Young Lee
-
Patent number: 8765611Abstract: A process for etching semiconductors, such as II-VI or III-V semiconductors is provided. The method includes sputter etching the semiconductor through an etching mask using a nonreactive gas, removing the semiconductor and cleaning the chamber with a reactive gas. The etching mask includes a photoresist. Using this method, light-emitting diodes with light extracting elements or nano/micro-structures etched into the semiconductor material can be fabricated.Type: GrantFiled: November 2, 2010Date of Patent: July 1, 2014Assignee: 3M Innovative Properties CompanyInventors: Michael A. Haase, Terry L. Smith, Jun-Ying Zhang
-
Patent number: 8664123Abstract: There is provided a method for manufacturing a nitride semiconductor substrate, comprising: etching and flattening a surface of a nitride semiconductor substrate disposed facing a surface plate, by using the surface plate having a surface composed of any one of Ni, Ti, Cr, W, and Mo or nitride of any one of them, disposing the surface of the surface plate and a flattening surface of a nitride semiconductor substrate proximately so as to be faced each other, and supplying gas containing at least hydrogen and ammonia between the surface of the surface plate and the surface of the nitride semiconductor substrate, wherein the surface plate and the nitride semiconductor substrate facing each other are set in a high temperature state of 900° C. or more.Type: GrantFiled: June 6, 2012Date of Patent: March 4, 2014Assignee: Hitachi Cable, Ltd.Inventor: Hajime Fujikura
-
Patent number: 8652343Abstract: A method for the selective removal of material from a substrate surface for forming a deepening includes the steps of applying a mask onto the substrate surface in accordance with the desired selective removal and dry-etching the substrate, a metal, preferably aluminum, being used as the masking material. Power may be coupled inductively to a plasma.Type: GrantFiled: August 14, 2003Date of Patent: February 18, 2014Assignee: Excelitas Technologies Singapore Pte. Ltd.Inventor: Martin Hausner
-
Patent number: 8586859Abstract: A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.Type: GrantFiled: July 27, 2012Date of Patent: November 19, 2013Assignee: Emcore Solar Power, Inc.Inventor: Tansen Varghese
-
Patent number: 8575033Abstract: Provided are processes for the low temperature deposition of silicon-containing films using carbosilane precursors containing a carbon atom bridging at least two silicon atoms. Certain methods comprise providing a substrate; in a PECVD process, exposing the substrate surface to a carbosilane precursor containing at least one carbon atom bridging at least two silicon atoms; exposing the carbosilane precursor to a low-powered energy sourcedirect plasma to provide a carbosilane at the substrate surface; and densifying the carbosilanestripping away at least some of the hydrogen atoms to provide a film comprising SiC. The SiC film may be exposed to the carbosilane surface to a nitrogen source to provide a film comprising SiCN.Type: GrantFiled: September 11, 2012Date of Patent: November 5, 2013Assignee: Applied Materials, Inc.Inventors: Timothy W. Weldman, Todd Schroeder
-
Patent number: 8546269Abstract: Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.Type: GrantFiled: April 3, 2009Date of Patent: October 1, 2013Assignee: International Business Machines CorporationInventors: Tymon Barwicz, Guy Cohen, Lidija Sekaric, Jeffrey Sleight
-
Patent number: 8491805Abstract: A semiconductor device manufacturing method includes a plasma etching step for etching an etching target film formed on a substrate accommodated in a processing chamber. In the plasma etching step, a processing gas including a gaseous mixture containing predetermined gases is supplied into the processing chamber, and a cycle including a first step in which a flow rate of at least one of the predetermined gases is set to a first value during a first time period and a second step in which the flow rate thereof is set to a second value that is different from the first value during a second time period is repeated consecutively at least three times without removing a plasma. The first time period and the second time period are set to about 1 to 15 seconds.Type: GrantFiled: February 2, 2011Date of Patent: July 23, 2013Assignee: Tokyo Electron LimitedInventors: Masato Kushibiki, Eiichi Nishimura
-
Patent number: 8476166Abstract: A manufacturing method of a semiconductor device includes: forming step of forming an etching mask on a second main face of a substrate, the etching mask being made of Cu or Cu alloy and having an opening, the second main face being on an opposite side of a first main face of the substrate where a nitride semiconductor layer is provided; a first etching step of applying a dry etching to the second main face of the substrate with use of the etching mask so that all of or a part of the nitride semiconductor layer is left; a removing step of removing the etching mask after the first etching step; and a second etching step of dry-etching the left nitride semiconductor layer after the removing step.Type: GrantFiled: September 29, 2010Date of Patent: July 2, 2013Assignee: Sumitomo Electric Device Innovations, Inc.Inventors: Toshiyuki Kosaka, Haruo Kawata, Tsutomu Komatani
-
Patent number: 8440571Abstract: Methods for deposition of silicon carbide films on a substrate surface are provided. The methods include the use of vapor phase carbosilane precursors and may employ plasma enhanced atomic layer deposition processes. The methods may be carried out at temperatures less than 600° C., for example between about 23° C. and about 200° C. or at about 100° C. This silicon carbide layer may then be densified to remove hydrogen content. Additionally, the silicon carbide layer may be exposed to a nitrogen source to provide reactive N—H groups, which can then be used to continue film deposition using other methods. Plasma processing conditions can be used to adjust the carbon, hydrogen and/or nitrogen content of the films.Type: GrantFiled: November 3, 2011Date of Patent: May 14, 2013Assignee: Applied Materials, Inc.Inventors: Timothy W. Weidman, Todd Schroeder
-
Publication number: 20130034968Abstract: A method of etching exposed silicon-and-carbon-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-carbon-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-carbon-containing material from the exposed silicon-and-carbon-containing material regions while very slowly removing other exposed materials. The silicon-and-carbon-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.Type: ApplicationFiled: October 24, 2011Publication date: February 7, 2013Applicant: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin K. Ingle, Yunyu Wang, Young Lee
-
Publication number: 20130023128Abstract: There is provided a method for manufacturing a nitride semiconductor substrate, comprising: etching and flattening a surface of a nitride semiconductor substrate disposed facing a surface plate, by using the surface plate having a surface composed of any one of Ni, Ti, Cr, W, and Mo or nitride of any one of them, disposing the surface of the surface plate and a flattening surface of a nitride semiconductor substrate proximately so as to be faced each other, and supplying gas containing at least hydrogen and ammonia between the surface of the surface plate and the surface of the nitride semiconductor substrate, wherein the surface plate and the nitride semiconductor substrate facing each other are set in a high temperature state of 900° C. or more.Type: ApplicationFiled: June 6, 2012Publication date: January 24, 2013Applicant: HITACHI CABLE, LTD.Inventor: Hajime FUJIKURA
-
Patent number: 8330036Abstract: A method of fabricating a multi-junction solar cell on a separable substrate, and structure formed thereby are provided. The method comprises establishing a substrate having a semiconductive composition and forming a sacrificial layer upon the substrate. A solar cell portion is formed upon the sacrificial layer, such that the solar cell portion includes a plurality of multi junction layers. A stabilizing cell layer of semiconductor material is then formed on the solar cell portion, with the stabilizing cell layer having a predetermined thickness greater than a thickness of any individual one of the III-V multi junction layers. Etching is thereafter carried out to remove the sacrificial layer for releasing the solar cell portion from the substrate.Type: GrantFiled: August 31, 2009Date of Patent: December 11, 2012Inventor: Seoijin Park
-
Patent number: 8288290Abstract: A method is provided for the integration of an optical gain material into a Complementary metal oxide semiconductor device, the method comprising the steps of: configuring a workpiece from a silicon wafer upon which is disposed an InP wafer bearing an epitaxy layer; mechanically removing the InP substrate; etching the InP remaining on epitaxy layer with hydrochloric acid; depositing at least one Oxide pad on revealed the epitaxy layer; using the Oxide pad as a mask during a first pattern etch removing the epitaxy to an N level; etching with a patterned inductively coupled plasma (ICP) technique; isolating the device on the substrate with additional pattern etching patterning contacts, applying the contacts.Type: GrantFiled: August 29, 2008Date of Patent: October 16, 2012Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventor: Daniel N. Carothers
-
Publication number: 20120238102Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.Type: ApplicationFiled: March 9, 2012Publication date: September 20, 2012Applicant: Applied Materials, Inc.Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
-
Patent number: 8263500Abstract: A method for fabricating a semiconductor laser device, by etching facets using a photoelectrochemical (PEC) etch, so that the facets are sufficiently smooth to support optical modes within a cavity bounded by the facets.Type: GrantFiled: February 1, 2010Date of Patent: September 11, 2012Assignee: The Regents of the University of CaliforniaInventors: Adele C. Tamboli, Evelyn L. Hu, Steven P. DenBaars, Arpan Chakraborty
-
Patent number: 8263853Abstract: A method of forming a plurality of discrete, interconnected solar cells mounted on a carrier by providing a first semiconductor substrate; depositing on the first substrate a sequence of layers of semiconductor material forming a solar cell structure; forming a metal back contact layer over the solar cell structure; mounting a carrier on top of the metal back contact; removing the first substrate; and lithographically patterning and etching the solar cell structure to form a plurality of discrete solar cells mounted on the carrier.Type: GrantFiled: August 7, 2008Date of Patent: September 11, 2012Assignee: Emcore Solar Power, Inc.Inventor: Tansen Varghese
-
Patent number: 8232212Abstract: An apparatus for adaptive self-aligned dual patterning and method thereof. The method includes providing a substrate to a processing platform configured to perform an etch process and a deposition process and a metrology unit configured for in-vacuo critical dimension (CD) measurement. The in-vacuo CD measurement is utilized for feedforward adaptive control of the process sequence processing platform or for feedback and feedforward adaptive control of chamber process parameters. In one aspect, a first layer of a multi-layered masking stack is etched to form a template mask, an in-vacuo CD measurement of the template mask is made, and a spacer is formed, adjacent to the template mask, to a width that is dependent on the CD measurement of the template mask.Type: GrantFiled: July 11, 2008Date of Patent: July 31, 2012Assignee: Applied Materials, Inc.Inventors: Matthew F. Davis, Thorsten B. Lill, Lei Lian
-
Patent number: 8222157Abstract: A device for inductively confining capacitively coupled RF plasma formed in a plasma processing apparatus. The apparatus includes an upper electrode and a lower electrode that is adapted to support a substrate and to generate the plasma between the substrate and the upper electrode. The device includes a dielectric support ring that concentrically surrounds the upper electrode and a plurality of coil units mounted on the dielectric support ring. Each coil unit includes a ferromagnetic core positioned along a radial direction of the dielectric support ring and at least one coil wound around each ferromagnetic core. The coil units generate, upon receiving RF power from an RF power source, electric and magnetic fields that reduce the number of charged particles of the plasma diffusing away from the plasma.Type: GrantFiled: November 12, 2010Date of Patent: July 17, 2012Assignee: Lam Research CorporationInventors: Alexei Marakhtanov, Rajinder Dhindsa, Eric Hudson, Andreas Fischer
-
Patent number: 8211808Abstract: A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate.Type: GrantFiled: August 31, 2009Date of Patent: July 3, 2012Assignee: Applied Materials, Inc.Inventors: Kedar Sapre, Jing Tang, Linlin Wang, Abhijit Basu Mallick, Nitin Ingle
-
Patent number: 8173891Abstract: Modeling a monolithic, multi-bandgap, tandem, solar photovoltaic converter or thermophotovoltaic converter by constraining the bandgap value for the bottom subcell to no less than a particular value produces an optimum combination of subcell bandgaps that provide theoretical energy conversion efficiencies nearly as good as unconstrained maximum theoretical conversion efficiency models, but which are more conducive to actual fabrication to achieve such conversion efficiencies than unconstrained model optimum bandgap combinations. Achieving such constrained or unconstrained optimum bandgap combinations includes growth of a graded layer transition from larger lattice constant on the parent substrate to a smaller lattice constant to accommodate higher bandgap upper subcells and at least one graded layer that transitions back to a larger lattice constant to accommodate lower bandgap lower subcells and to counter-strain the epistructure to mitigate epistructure bowing.Type: GrantFiled: May 15, 2008Date of Patent: May 8, 2012Assignee: Alliance for Sustainable Energy, LLCInventors: Mark W. Wanlass, Angelo Mascarenhas
-
Publication number: 20120083130Abstract: Apparatus and methods for plasma etching are disclosed. In one embodiment, a method of etching a plurality of features on a wafer includes positioning a wafer on a feature plate within a chamber of a plasma etcher, providing a plasma source gas within the chamber, providing an anode above the feature plate and a cathode below the feature plate, connecting a portion of the cathode to the feature plate, generating plasma ions using a radio frequency power source and the plasma source gas, directing the plasma ions toward the wafer using an electric field, and providing an electrode shield around the cathode. The electrode shield is configured to protect the cathode from ions directed toward the cathode including the portion of the cathode connected to the feature plate.Type: ApplicationFiled: October 5, 2010Publication date: April 5, 2012Applicant: Skyworks Solutions, Inc.Inventors: Daniel K. Berkoh, Elena B. Woodard, Dean G. Scott
-
Patent number: 8133818Abstract: In a method of forming a hard mask pattern in a semiconductor device, only processes for forming patterns having a row directional line shape and a column directional line shape on a plane are performed so that the hard mask patterns can be formed to define densely disposed active regions. A pitch of the hard mask patterns is less than a resolution limit of an exposure apparatus.Type: GrantFiled: June 4, 2008Date of Patent: March 13, 2012Assignee: Hynix Semiconductor Inc.Inventor: Woo Yung Jung
-
Patent number: 8119532Abstract: A dual zone plasma processing chamber is provided. The plasma processing chamber includes a first substrate support having a first support surface adapted to support a first substrate within the processing chamber and a second substrate support having a second support surface adapted to support a second substrate within the processing chamber. One or more gas sources in fluid communication with one or more gas distribution members supply process gas to a first zone adjacent to the first substrate support and a second zone adjacent to the second substrate support. A radio-frequency (RF) antenna adapted to inductively couple RF energy into the interior of the processing chamber and energize the process gas into a plasma state in the first and second zones. The antenna is located between the first substrate support and the second substrate support.Type: GrantFiled: May 26, 2011Date of Patent: February 21, 2012Assignee: Lam Research CorporationInventor: Sanket P. Sant
-
Patent number: 8105953Abstract: A semiconductor manufacturing apparatus includes a chamber, a gas supplier, a vacuum pump, an electrode, a conductive knitted wire mesh and a radio frequency power supply. The electrode is placed outside of the chamber and fixed to the chamber. The gas supplier supplies gas into the chamber. The vacuum pump exhausts the chamber. The radio frequency power supply supplies radio frequency power to the electrode through the conductive knitted wire mesh.Type: GrantFiled: July 26, 2011Date of Patent: January 31, 2012Assignee: Renesas Electronics CorporationInventor: Keiichirou Takehara
-
Patent number: 8067687Abstract: A monolithic, multi-bandgap, tandem solar photovoltaic converter has at least one, and preferably at least two, subcells grown lattice-matched on a substrate with a bandgap in medium to high energy portions of the solar spectrum and at least one subcell grown lattice-mismatched to the substrate with a bandgap in the low energy portion of the solar spectrum, for example, about 1 eV.Type: GrantFiled: December 30, 2004Date of Patent: November 29, 2011Assignee: Alliance for Sustainable Energy, LLCInventor: Mark W. Wanlass
-
Patent number: 8021564Abstract: A method for detecting an end point of a resist peeling process in which a resist is gasified to be peeled off by producing hydrogen radicals by catalytic cracking reaction where a hydrogen-containing gas contacts with a high-temperature catalyst, and contacting the produced hydrogen radicals with a resist on a substrate, includes monitoring one or more parameters indicating a state of the catalyst and detecting the end point of the resist peeling process based on variations of the monitored parameters. The hydrogen-containing gas may be a H2 gas. The parameters indicating the state of the catalyst may be one or more electrical parameters when a power is supplied to the catalyst. Further, the catalyst may be a filament made of a high melting point metal.Type: GrantFiled: October 5, 2007Date of Patent: September 20, 2011Assignee: Tokyo Electron LimitedInventors: Isamu Sakuragi, Kazuhiro Kubota
-
Patent number: 7964424Abstract: A method for manufacturing a nitride semiconductor light-emitting element comprises: forming a semiconductor laminated structure wherein an n-type nitride semiconductor epitaxial layer, an active layer, and a p-type nitride semiconductor epitaxial layer are laminated on a substrate; forming a p-type electrode having a first electrode layer containing Pd and a second electrode layer containing Ta on the p-type nitride semiconductor epitaxial layer; heat treating at a temperature between 400° C. and 600° C. in ambient containing oxygen after forming the p-type electrode; and forming a pad electrode containing Au on the p-type electrode after the heat treating.Type: GrantFiled: November 5, 2008Date of Patent: June 21, 2011Assignee: Mitsubishi Electric CorporationInventors: Kyozo Kanamoto, Katsuomi Shiozawa, Kazushige Kawasaki, Shinji Abe, Hitoshi Sakuma
-
Patent number: 7948075Abstract: A silicon nitride substrate having appropriately adjusted warpage and surface roughness can be obtained by mixing magnesium oxide of 3 to 4 wt % and at least one kind of rare-earth element oxide of 2 to 5 wt % with silicon nitride source material powder to form a sheet-molded body, sintering the sheet-molded body, and performing a heat treatment at a temperature of 1,550 to 1,700 degree C. with a pressure of 0.5 to 6.0 kPa with a plurality of substrates being stacked. Also, a silicon nitride circuit board and a semiconductor module using the same are provided.Type: GrantFiled: March 3, 2009Date of Patent: May 24, 2011Assignee: Hitachi Metals, Ltd.Inventors: Youichirou Kaga, Junichi Watanabe
-
Patent number: RE42955Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.Type: GrantFiled: October 1, 2004Date of Patent: November 22, 2011Assignee: BAE Systems Information and Electronic Systems Integration Inc.Inventors: Liberty L. Gunter, Kanin Chu, Charles R. Eddy, Jr., Theodore D. Moustakas, Enrico Bellotti