Compound Semiconductor Patents (Class 438/718)
  • Publication number: 20110053380
    Abstract: A method of etching silicon-and-carbon-containing material is described and includes a SiConi™ etch in combination with a flow of reactive oxygen. The reactive oxygen may be introduced before the SiConi™ etch reducing the carbon content in the near surface region and allowing the SiConi™ etch to proceed more rapidly. Alternatively, reactive oxygen may be introduced during the SiConi™ etch further improving the effective etch rate.
    Type: Application
    Filed: August 31, 2009
    Publication date: March 3, 2011
    Applicant: Applied Materials, Inc.
    Inventors: Kedar Sapre, Jing Tang, Linlin Wang, Abhijit Basu Mallick, Nitin Ingle
  • Patent number: 7892979
    Abstract: A method of manufacturing a dot pattern includes the steps of preparing a structured material composed of a plurality of columnar members containing a first component and a region containing a second component different from the first component surrounding the columnar members, with the structured material being formed by depositing the first component and the second component on a substrate, and removing the columnar members from the structured material to form a porous material having a columnar hole. In addition, a material is introduced into the columnar hole portions of the porous material to form a dot pattern, and the porous material is removed.
    Type: Grant
    Filed: May 13, 2008
    Date of Patent: February 22, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventors: Miki Ogawa, Hirokatsu Miyata, Albrecht Otto, Akira Kuriyama, Hiroshi Okura, Tohru Den, Kazuhiko Fukutani
  • Patent number: 7842617
    Abstract: The present invention is an etching method for performing an etching process in the presence of a plasma on an object to be processed in which a layer to be etched made of a tungsten-containing material is formed on a base layer made of a silicon-containing material in a process vessel capable of being evacuated to create therein a vacuum, wherein a chlorine-containing gas, an oxygen-containing gas, and a nitrogen-containing gas are used as an etching gas for performing the etching process.
    Type: Grant
    Filed: November 18, 2005
    Date of Patent: November 30, 2010
    Assignee: Tokyo Electron Limited
    Inventor: Tetsuya Nishizuka
  • Patent number: 7828987
    Abstract: In some implementations, a method is provided in a plasma reactor for etching a trench in an organic planarization layer of a resist structure comprising a photoresist mask structure over a hardmask masking the organic planarization layer. This may include introducing into the plasma reactor an etchant gas chemistry including N2, H2, and O2 and etching a masked organic planarization layer using a plasma formed from the etchant gas chemistry. This may include etching through the planarization layer to form a trench with a single etch step.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: November 9, 2010
    Assignee: Applied Materials, Inc.
    Inventors: Jens Karsten Schneider, Ying Xiao, Gerardo A. Delgadino
  • Publication number: 20100279511
    Abstract: Provided are a wafer through silicon via (TSV) forming method and equipment therefor. The wafer TSV forming method includes the operations of arranging a wafer having a front surface having a circuit area patterned thereon; recognizing locations of bond pads in the circuit area of the front surface of the wafer by using an image recognition camera, and converting the recognition of the locations into bond pad location information with respect to a back surface of the wafer; flipping the wafer; forming etching holes with middle depth in the back surface of the wafer by using a laser in a manner to match the locations of the bond pads by using the bond pad location information from the image recognition camera; and performing a plasma isotropic etching on the back surface having formed therein the etching holes with middle depth, thereby forming TSVs penetrating the bond pads.
    Type: Application
    Filed: July 30, 2009
    Publication date: November 4, 2010
    Inventors: Jung Hwan CHUN, Gyu Han KIM
  • Patent number: 7811891
    Abstract: A semiconductor process and apparatus uses a predetermined sequence of patterning and etching steps to etch a gate stack (30, 32) formed over a substrate (36), thereby forming an etched gate (33) having a vertical sidewall profile (35). By constructing the gate stack (30, 32) with a graded material composition of silicon-based layers, the composition of which is selected to counteract the etching tendencies of the predetermined sequence of patterning and etching steps, a more idealized vertical gate sidewall profile (35) may be obtained.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: October 12, 2010
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Marius K. Orlowski, Olubunmi O. Adetutu, Phillip J. Stout
  • Patent number: 7776752
    Abstract: Provided are an etching method for a multi-layered structure of semiconductors in groups III-V and a method of manufacturing a VCSEL using the etching method. According to the etching method, a stacked structure including a first semiconductor layer and a second semiconductor layer is exposed to a plasma of a mixture consisting of Cl2, Ar, CH4, and H2 to etch the stacked structure, so that a mirror layer of the VCSEL is formed. The first semiconductor layer is formed of a semiconductor in groups III-V and the second semiconductor layer is formed of a semiconductor in groups III-V, other than the semiconductor of the first semiconductor layer. At least part of a lower mirror layer, a lower electrode layer, an optical gain layer, an upper electrode layer, and an upper mirror layer is etched using one time of an etching process, so that a clean and smooth etched surface is obtained.
    Type: Grant
    Filed: December 7, 2006
    Date of Patent: August 17, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: O Kyun Kwon, Mi Ran Park, Won Seok Han, Hyun Woo Song
  • Patent number: 7767596
    Abstract: A wafer support pin has a front end contacted with a wafer such that the front end is flat or rounded. Thus, gravitational stress is minimized during annealing the wafer, thereby minimizing slip dislocation. This wafer support pin is suitably used for annealing of a wafer, particularly high temperature rapid thermal annealing of a large-diameter wafer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: August 3, 2010
    Assignee: Siltron, Inc.
    Inventors: Kun Kim, Jin-Kyun Hong, Woo-Hyun Seo, Kyoung-Hwan Song
  • Patent number: 7758762
    Abstract: An electron-emitting device comprises a pair of electrodes and an electroconductive film arranged between the electrodes and including an electron-emitting region carrying a graphite film. The graphite film shows, in a Raman spectroscopic analysis using a laser light source with a wavelength of 514.5 nm and a spot diameter of 1 ?m, peaks of scattered light, of which 1) a peak (P2) located in the vicinity of 1,580 cm?1 is greater than a peak (P1) located in the vicinity of 1,335 cm?1 or 2) the half-width of a peak (P1) located in the vicinity of 1,335 cm?1 is not greater than 150 cm?1.
    Type: Grant
    Filed: June 19, 2007
    Date of Patent: July 20, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventors: Fumio Kishi, Masato Yamanobe, Takeo Tsukamoto, Toshikazu Ohnishi, Keisuke Yamamoto, Sotomitsu Ikeda, Yasuhiro Hamamoto, Kazuya Miyazaki
  • Publication number: 20100155899
    Abstract: An etching method forms a metal-fluoride layer at a temperature of 150° C. or higher at least as a part of an etching mask formed over a semiconductor layer; patterns the metal-fluoride layer; and etches the semiconductor layer using the patterned metal-fluoride layer as a mask. According to the etching method, an etching-resistant semiconductor layer such as a Group III-V nitride semiconductor can be easily etched by a relatively simpler process.
    Type: Application
    Filed: April 30, 2007
    Publication date: June 24, 2010
    Applicant: MITSUBISHI CHEMICAL CORPORATION
    Inventor: Hideyoshi Horie
  • Patent number: 7737043
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Grant
    Filed: May 16, 2007
    Date of Patent: June 15, 2010
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Patent number: 7718499
    Abstract: In a method of fabricating a semiconductor device, an additive gas is mixed with an etching gas to reduce a fluorine ratio of the etching gas. The etching gas having a reduced fluorine rate is utilized in the process for etching a nitride layer formed on an oxide layer to prevent the oxide layer formed below the nitride layer from being etched along with the nitride layer. The method comprises primarily etching an exposed charge storage layer using an etching gas; and secondarily etching the charge storage layer using the etching gas under a condition that a ratio of fluorine contained in the etching gas utilized in the secondary etching step is less than a ratio of fluorine contained in the etching gas utilized in the primary etching step. Thus, the tunnel insulating layer formed below the charge storage layer is not damaged when the charge storage layer is patterned.
    Type: Grant
    Filed: June 27, 2008
    Date of Patent: May 18, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Choong Bae Kim
  • Patent number: 7691735
    Abstract: The invention relates to a method for manufacturing chips composed of at least one electrically conductive material. Such a method comprises the following steps: deposition, on a support, of an alloy comprising at least the electrically conductive material and a second material; exposure of the alloy to plasma etching, in order to cause the desorption of the materials of the alloy not forming part of the composition of the chips, that is at least the second material but not the electrically conductive material; formation of chips composed of at least said electrically conductive material.
    Type: Grant
    Filed: October 20, 2008
    Date of Patent: April 6, 2010
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Laurent Grenouillet, Jonathan Garcia, François Marion, Nicolas Olivier, Marion Perrin
  • Patent number: 7682991
    Abstract: A method of manufacturing a silicon carbide semiconductor device includes forming a trench for a MOS gate in an SiC substrate by dry etching. Thereafter, the substrate with the trench is heat treated. The heat treatment includes heating the substrate in an Ar gas atmosphere or in a mixed gas atmosphere containing SiH4 and Ar at a temperature between 1600° C. and 1800° C., and thereafter in a hydrogen gas atmosphere at a temperature between 1400° C. and 1500° C. The present manufacturing method smoothens the trench inner surface and rounds the corners in the trench to prevent the electric field from localizing thereto.
    Type: Grant
    Filed: December 19, 2007
    Date of Patent: March 23, 2010
    Assignee: Fuji Electric Device Technology Co., Ltd.
    Inventors: Yasuyuki Kawada, Takeshi Tawara, Tae Tawara
  • Patent number: 7682937
    Abstract: A method and arrangement for treating a substrate processed using a laser beam, wherein said substrate comprises at least a body of semiconductor material. The method comprises a step of etching said substrate for removing from said body of semiconductor material recast material deposited on said body during said laser processing. The step of etching is controlled for removing in addition to said recast layer, at least a part of said semiconductor material of said body for improving mechanical strength of said substrate.
    Type: Grant
    Filed: November 25, 2005
    Date of Patent: March 23, 2010
    Assignee: Advanced Laser Separation International B.V.
    Inventors: Rogier Evertsen, Hans Peter Chall
  • Patent number: 7674395
    Abstract: The invention provides a laser etching method for optical ablation working by irradiating a work article formed of an inorganic material with a laser light from a laser oscillator capable of emitting in succession light pulses of a large energy density in space and time with a pulse radiation time not exceeding 1 picosecond, wherein, in laser etching of the work article formed of the inorganic material by irradiation thereof with the laser light from the laser oscillator with a predetermined pattern and with a predetermined energy density, there is utilized means for preventing deposition of a work by-product around the etching position.
    Type: Grant
    Filed: January 3, 2007
    Date of Patent: March 9, 2010
    Assignee: Canon Kabushiki Kaisha
    Inventor: Jun Koide
  • Patent number: 7666795
    Abstract: A method for manufacturing a semiconductor device includes forming a SiGe layer on a Si substrate, forming a dummy pattern to expose a surface of the Si substrate, and wet etching the SiGe layer while an etchant is contacted with, the dummy pattern.
    Type: Grant
    Filed: December 13, 2007
    Date of Patent: February 23, 2010
    Assignee: Seiko Epson Corporation
    Inventors: Juri Kato, Hideaki Oka, Masamitsu Uehara
  • Patent number: 7648915
    Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.
    Type: Grant
    Filed: January 12, 2007
    Date of Patent: January 19, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Larson Lindholm, Aaron R. Wilson, David K. Hwang
  • Publication number: 20090236693
    Abstract: Films of III-nitride for semiconductor device growth are planarized using an etch-back method. The method includes coating a III-nitride surface having surface roughness features in the micron range with a sacrificial planarization material such as an appropriately chose photoresist. The sacrificial planarization material is then etched together with the III-nitride roughness features using dry etch methods such as inductivel coupled plasma reactive ion etching. By closely matching the etch rates of the sacrificial planarization material and the III-nitride material, a planarized III-nitride surface is achieved. The etch-back process together with a high temperature annealing process yields a planarize III-nitride surface with surface roughness features reduced to the nm range. Planarized III-nitride, e.g., GaN, substrates and devices containing them are also provided.
    Type: Application
    Filed: February 2, 2007
    Publication date: September 24, 2009
    Applicant: Trustees of Boston University
    Inventors: Theodore D. Moustakas, Adrian D. Williams
  • Patent number: 7585698
    Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 8, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiromitsu Ishii
  • Patent number: 7575998
    Abstract: Embodiments relate to a method for forming a wiring in a semiconductor device, that may include laminating a conductive layer for wiring formation on a semiconductor substrate, forming a photoresist layer pattern on the conductive layer, performing primary dry etching for the conductive layer after employing the photoresist layer pattern as a mask, thereby forming a wiring pattern, partially removing the photoresist layer pattern through secondary dry etching, thereby forming a passivation layer on a surface of the wiring pattern, performing tertiary dry etching for the wiring pattern and a diffusion barrier after employing the photoresist layer pattern as a mask, thereby forming a metal wiring, and removing the photoresist layer pattern.
    Type: Grant
    Filed: December 22, 2006
    Date of Patent: August 18, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jong Soon Lee
  • Patent number: 7544611
    Abstract: An aluminum gallium nitride/gallium nitride layer (III-V nitride semiconductor layer) is formed on the surface of a silicone carbide substrate. The aluminum gallium nitride/gallium nitride layer is dry-etched from an exposed surface, using a chlorine-based gas (first gas) and a surface via hole is thereby formed. A back via hole, which is to be connected to the surface via hole, is formed by dry-etching the silicon carbide substrate from an exposed back side using a fluorine-based gas (second gas).
    Type: Grant
    Filed: November 6, 2007
    Date of Patent: June 9, 2009
    Assignee: Mitsubishi Electric Corporation
    Inventor: Takeo Shirahama
  • Patent number: 7528076
    Abstract: A method of manufacturing gate oxide layers with different thicknesses is disclosed. The method includes that a substrate is provided first. The substrate has a high voltage device region and a low voltage device region. Then, a high voltage gate oxide layer is formed on the substrate. Afterwards, a first wet etching process is performed to remove a portion of the high voltage gate oxide layer in the low voltage device region. Then, a second wet etching process is performed to remove the remaining high voltage gate oxide layer in the low voltage device region. The etching rate of the second wet etching process is smaller than that of the first wet etching process. Next, a low voltage gate oxide layer is formed on the substrate in the low voltage device region.
    Type: Grant
    Filed: May 11, 2007
    Date of Patent: May 5, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Shu-Chun Chan, Jung-Ching Chen, Shyan-Yhu Wang
  • Patent number: 7482177
    Abstract: A method for manufacturing an optical device includes the steps of: forming a first multilayer film, including forming a first mirror above a substrate, forming an active layer above the first mirror, forming a second mirror above the active layer, forming a semiconductor layer on the second mirror, and forming a sacrificial layer on the semiconductor layer; conducting a first examination step of conducting a reflectance examination on the first multilayer film; forming a second multilayer film by removing the sacrificial layer from the first multilayer film; conducting a second examination step of conducting a reflection coefficient examination on the second multilayer film; and patterning the second multilayer film to form a surface-emitting laser section having the first mirror, the active layer and the second mirror, and a diode section having the semiconductor layer, wherein the sacrificial layer is formed to have an optical film thickness of an odd multiple of ?/4, where ? is a design wavelength of ligh
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 27, 2009
    Assignee: Seiko Epson Corporation
    Inventor: Yasutaka Imai
  • Publication number: 20080268647
    Abstract: The present invention provides a method of plasma etching with pattern mask. There are two different devices in the two section of a wafer, comprising silicon and Gallium Arsenide (GaAs). The Silicon section is for general semiconductor. And the GaAs section is for RF device. The material of pad in the silicon is usually metal, and metal oxide is usually formed on the pads. The metal oxide is unwanted for further process; therefore it should be removed by plasma etching process. A film is attached to the surface of the substrate exposing the area need for etching. Then a mask is attached and aligned onto the film therefore exposing the area need for etching. Then plasma dry etching is applied on the substrate for removing the metal oxide.
    Type: Application
    Filed: June 6, 2008
    Publication date: October 30, 2008
    Inventors: Wen-Kun Yang, Jui-Hsien Chang, Wen-Bin Sun
  • Patent number: 7436075
    Abstract: The ion beam irradiation apparatus has a vacuum chamber 10, an ion source 2, a substrate driving mechanism 30, rotation shafts 14, arms 12, and a motor. The ion source 2 is disposed inside the vacuum chamber 10, and emits an ion beam 4 which is larger in width than a substrate 6, to the substrate 6. The substrate driving mechanism 30 reciprocally drives the substrate 6 in the vacuum chamber 10. The center axes 14a of the rotation shafts 14 are located in a place separated from the ion source 2 toward the substrate, and substantially parallel to the surface of the substrate. The arms 12 are disposed inside the vacuum chamber 10, and support the ion source 2 through the rotation shafts 14. The motor is disposed outside the vacuum chamber 10, and reciprocally rotates the rotation shaft 14.
    Type: Grant
    Filed: August 31, 2005
    Date of Patent: October 14, 2008
    Assignee: Nissin Ion Equipment Co., Ltd.
    Inventor: Yasunori Ando
  • Patent number: 7429534
    Abstract: An improved solution for producing nitride-based heterostructure(s), heterostructure device(s), integrated circuit(s) and/or Micro-Electro-Mechanical System(s) is provided. A nitride-based etch stop layer that includes Indium (In) is included in a heterostructure. An adjacent layer of the heterostructure is selectively etched to expose at least a portion of the etch stop layer. The etch stop layer also can be selectively etched. In one embodiment, the adjacent layer can be etched using reactive ion etching (RIE) and the etch stop layer is selectively etched using a wet chemical etch. In any event, the selectively etched area can be used to generate a contact or the like for a device.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: September 30, 2008
    Assignee: Sensor Electronic Technology, Inc.
    Inventors: Remigijus Gaska, Xuhong Hu, Qhalid Fareed, Michael Shur
  • Patent number: 7413958
    Abstract: An etched grooved GaN-based permeable-base transistor structure is disclosed, along with a method for fabrication of same.
    Type: Grant
    Filed: October 1, 2004
    Date of Patent: August 19, 2008
    Assignee: BAE Systems Information and Electronic Systems Integration Inc.
    Inventors: Liberty L Gunter, Kanin Chu, Charles R Eddy, Jr., Theodore D Moustakas, Enrico Bellotti
  • Patent number: 7390750
    Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.
    Type: Grant
    Filed: March 23, 2005
    Date of Patent: June 24, 2008
    Assignee: Cypress Semiconductor Corp.
    Inventors: Krishnaswamy Ramkumar, Alain P. Blosse, James A. Hunter
  • Patent number: 7387967
    Abstract: A method of manufacturing a dot pattern includes the steps of preparing a structured material composed of a plurality of columnar members containing a first component and a region containing a second component different from the first component surrounding the columnar members, with the structured material being formed by depositing the first component and the second component on a substrate, and removing the columnar members from the structured material to form a porous material having a columnar hole. Additional steps include introducing a mask material into the columnar hole of the porous material to form a dot pattern, and removing the porous material.
    Type: Grant
    Filed: December 12, 2003
    Date of Patent: June 17, 2008
    Assignee: Canon Kabushiki Kaisha
    Inventors: Miki Ogawa, Hirokatsu Miyata, Albrecht Otto, Akira Kuriyama, Hiroshi Okura, Tohru Den, Kazuhiko Fukutani
  • Patent number: 7375037
    Abstract: To improve the shape of a gate electrode having SiGe, after patterning a gate electrode 15G having an SiGe layer 15b by a dry etching process, a plasma processing (postprocessing) is carried out in an atmosphere of an Ar/CHF3 gas. Thereby, the gate electrode 15G can be formed without causing side etching at two side faces (SiGe layer 15b) of the gate electrode 15G.
    Type: Grant
    Filed: August 13, 2003
    Date of Patent: May 20, 2008
    Assignee: Renesas Technology Corp.
    Inventors: Kazuo Yamazaki, Shinji Kuniyoshi, Kousuke Kusakari, Takenobu Ikeda, Masahiro Tadokoro
  • Patent number: 7368394
    Abstract: Methods for forming anisotropic features for high aspect ratio application in etch process are provided in the present invention. The methods described herein advantageously facilitates profile and dimension control of features with high aspect ratios through a sidewall passivation management scheme. In one embodiment, sidewall passivations are managed by selectively forming an oxidation passivation layer on the sidewall and/or bottom of etched layers. In another embodiment, sidewall passivation is managed by periodically clearing the overburden redeposition layer to preserve an even and uniform passivation layer thereon. The even and uniform passivation allows the features with high aspect ratios to be incrementally etched in a manner that pertains a desired depth and vertical profile of critical dimension in both high and low feature density regions on the substrate without generating defects and/or overetching the underneath layers.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 6, 2008
    Assignee: Applied Materials, Inc.
    Inventors: Meihua Shen, Uwe Leucke, Guangxiang Jin, Xikun Wang, Wei Liu, Scott Williams
  • Publication number: 20080102642
    Abstract: A method of seasoning an idle silicon nitride etcher is described. A buffer material having stronger adhesion to an internal wall of the chamber of the silicon nitride etcher than silicon nitride is etched in the chamber, so as to form a buffer layer on the internal wall of the chamber. Then, silicon nitride is etched in the chamber to form a layer of SiN-based polymer on the buffer layer.
    Type: Application
    Filed: October 31, 2006
    Publication date: May 1, 2008
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Ping-Hung Chen, Kuang-Hua Shih
  • Patent number: 7341952
    Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: March 11, 2008
    Assignee: Nanya Technology Corporation
    Inventors: Kaan-Lu Tzou, Tzu-Ching Tsai, Yi-Nan Chen
  • Patent number: 7316979
    Abstract: A method and apparatus for providing integrated active regions on silicon-on-insulator (SOI) devices by oxidizing a portion of the active layer. When the active layer of the SOI wafer is relatively thick, such as about 200 ? to 1000 ? or greater, the etching process partially removes the active layer. The remaining active layer is oxidized prior to a wet dip for removing the mask layer, preventing the wet dip process from undercutting the active region. When the active layer of the SOI wafer is relatively thin, such as about 25 ? to 400 ?, the partial etching step may be reduced or eliminated. In this case, the active layer is oxidized with little or no etching of the active layer. The exposed active layer is oxidized to prevent the wet dip process from undercutting the active region.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: January 8, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jhon-Jhy Liaw
  • Patent number: 7309656
    Abstract: A method for forming a step channel of a semiconductor device is disclosed. The method for forming a step channel of a semiconductor device comprises forming a hard mask layer pattern defining a step channel region on a semiconductor substrate, forming a spacer on a sidewall of the hard mask layer pattern, and simultaneously etching the spacer and a predetermined thickness of the semiconductor substrate using the hard mask layer pattern and the spacer as an etching mask.
    Type: Grant
    Filed: June 9, 2005
    Date of Patent: December 18, 2007
    Assignee: Hynix Semiconductors, Inc.
    Inventor: Young Man Cho
  • Publication number: 20070287296
    Abstract: Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor film made of In—Ga—Zn—O formed on a substrate.
    Type: Application
    Filed: May 22, 2007
    Publication date: December 13, 2007
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Chienliu Chang
  • Publication number: 20070275563
    Abstract: Methods of forming a mask for implanting a substrate and implanting using an implant stopping layer with a photoresist provide lower aspect ratio masks that cause minimal damage to trench isolations in the substrate during removal of the mask. In one embodiment, a method of forming a mask includes: depositing an implant stopping layer over the substrate; depositing a photoresist over the implant stopping layer, the implant stopping layer having a density greater than the photoresist; forming a pattern in the photoresist by removing a portion of the photoresist to expose the implant stopping layer; and transferring the pattern into the implant stopping layer by etching to form the mask. The implant stopping layer may include: hydrogenated germanium carbide, nitrogenated germanium carbide, fluorinated germanium carbide, and/or amorphous germanium carbon hydride (GeHX), where X includes carbon. The methods/mask reduce scattering during implanting because the mask has higher density than conventional masks.
    Type: Application
    Filed: May 25, 2006
    Publication date: November 29, 2007
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Katherina Babich, Todd C. Bailey, Richard A. Conti, Ryan P. Deschner
  • Publication number: 20070269989
    Abstract: There are provided an inspection method of a compound semiconductor substrate that can have the amount of impurities at the surface of the compound semiconductor substrate reduced, a compound semiconductor substrate, a surface treatment method of a compound semiconductor substrate, and a method of producing a compound semiconductor crystal. In the inspection method of the surface of the compound semiconductor substrate, the surface roughness Rms of the compound semiconductor substrate is measured using an atomic force microscope at the pitch of not more than 0.4 nm in a scope of not more than 0.2 ?m square. The surface roughness Rms of the compound semiconductor substrate measured by the inspection method is not more than 0.2 nm.
    Type: Application
    Filed: May 16, 2007
    Publication date: November 22, 2007
    Inventors: Takayuki Nishiura, So Tanaka, Yusuke Horie, Kyoko Okita, Takatoshi Okamoto
  • Patent number: 7288486
    Abstract: In a method for manufacturing a semiconductor device wherein via holes are formed in an SiC substrate, a stacked film consisting of a Ti film and an Au film is formed on the back face of the SiC substrate, and a Pd film is formed thereon. Then, an Ni film is formed by non-electrolytic plating, using the Pd film as a catalyst. Thereafter, via holes penetrating through the SiC substrate are formed by etching, using the Ni film as a mask.
    Type: Grant
    Filed: June 22, 2006
    Date of Patent: October 30, 2007
    Assignee: Mitsubishi Electric Corporation
    Inventors: Takeo Shirahama, Toshihiko Shiga, Kouichirou Hori
  • Patent number: 7282454
    Abstract: A component delivery mechanism for distributing a component inside a process chamber is disclosed. The component is used to process a work piece within the process chamber. The component delivery mechanism includes a plurality of component outputs for outputting the component to a desired region of the process chamber. The component delivery mechanism further includes a spatial distribution switch coupled to the plurality of component outputs. The spatial distribution switch is arranged for directing the component to at least one of the plurality of component outputs. The component delivery mechanism also includes a single component source coupled to the spatial distribution switch. The single component source is arranged for supplying the component to the spatial distribution switch.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: October 16, 2007
    Assignee: Lam Research Corporation
    Inventors: Richard A. Gottscho, Robert J. Steger
  • Patent number: 7268085
    Abstract: The present invention relates to a method for forming a storage node contact of a semiconductor device. The method includes the steps of: depositing sequentially a conductive layer, a nitride layer and a polysilicon layer on a substrate having an insulating structure and a conductive structure; etching selectively the polysilicon layer, the nitride layer and the conductive layer to form a plurality of conductive patterns with a stack structure of the conductive layer and a dual hard mask including the polysilicon layer and the nitride layer; forming an insulation layer along a profile containing the conductive patterns; and etching the insulation layer by using a line type photoresist pattern as an etch mask to form a contact hole exposing the conductive structure disposed between the neighboring conductive patterns.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: September 11, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Yu-Chang Kim, Soo-Young Park
  • Patent number: 7262137
    Abstract: Accordingly, this invention relates to an dry etching process for semiconductor wafers. More particularly, the present invention discloses a dry etching process including a halogen etchant (24) and a nitrogen gas (28) that selectively etches a compound semiconductor material (18) faster than the front-side metal layers (16A)(16B). Further, the dry etching process produces a vertical wall profile on compound semiconductor material (18) in both X (38) and Y (40) crystalline directions without undercutting the top of a via-opening.
    Type: Grant
    Filed: February 18, 2004
    Date of Patent: August 28, 2007
    Assignee: Northrop Grumman Corporation
    Inventors: Jennifer Wang, Huai-Min Sheng, Mike Barsky
  • Publication number: 20070197040
    Abstract: A plasma etching method includes the step of performing a plasma etching on a silicon-containing dielectric layer formed on a substrate to be processed by using a plasma, while using an organic layer as a mask. The plasma is generated from a processing gas at least including a C6F6 gas, a rare gas and an oxygen gas, and a flow rate ratio of the oxygen gas to the C6F6 gas (an oxygen gas flow rate/a C6F6 gas flow rate) is set to be about 2.8 to 3.3.
    Type: Application
    Filed: February 22, 2007
    Publication date: August 23, 2007
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Akinori Kitamura, Masanobu Honda, Nozomi Hirai, Kumiko Yamazaki
  • Patent number: 7259102
    Abstract: The present invention is directed to a method of etching a multi-layer structure formed from a layer of a first material and a layer of a second material differing from the first material to obtain a desired degree of planarization. To that end, the method includes creating a first set of process conditions to etch the first material, generating a second set of process conditions to etch the second material; and establishing an additional set of process conditions to concurrently etch the first and second materials at substantially the same etch rate.
    Type: Grant
    Filed: September 30, 2005
    Date of Patent: August 21, 2007
    Assignee: Molecular Imprints, Inc.
    Inventors: David C. Wang, Frank Y. Xu
  • Patent number: 7256134
    Abstract: The present invention includes a process for selectively etching a low-k dielectric material formed on a substrate using a plasma of a gas mixture in a plasma etch chamber. The gas mixture comprises a fluorine-rich fluorocarbon or hydrofluorocarbon gas, a nitrogen-containing gas, and one or more additive gases, such as a hydrogen-rich hydrofluorocarbon gas, an inert gas and/or a carbon-oxygen gas. The process provides a low-k dielectric to a photoresist mask etching selectivity ratio greater than about 5:1, a low-k dielectric to a barrier/liner layer etching selectivity ratio greater about 10:1, and a low-k dielectric etch rate higher than about 4000 ?/min.
    Type: Grant
    Filed: August 1, 2003
    Date of Patent: August 14, 2007
    Assignee: Applied Materials, Inc.
    Inventors: Yunsang Kim, Neungho Shin, Heeyeop Chae, Joey Chiu, Yan Ye, Fang Tian, Xiaoye Zhao
  • Patent number: 7250349
    Abstract: A ferroelectric memory capacitor is formed by forming a barrier layer, a first metal layer, a ferroelectric layer, a second metal layer, and a hard mask layer, on dielectric layer (70). Using the patterned hard mask layer (255), the layers are etched to form an etched barrier layer (205), and etched first metal layer (215), and etched ferroelectric layer (225), and etched second metal layers (235, 245). The etched layers form a ferroelectric memory capacitor (270) with sidewalls that form an angle with the plane of the upper surface of the dielectric layer (70) between 78° and 88°. The processes used to etch the layers are plasma processes performed at temperatures between 200° C. and 500° C.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: July 31, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Francis G. Celii, Mahesh J. Thakre, Scott R. Summerfelt
  • Patent number: 7208423
    Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.
    Type: Grant
    Filed: March 28, 2002
    Date of Patent: April 24, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Koji Hashimoto, Soichi Inoue, Kazuhiro Takahata, Kei Yoshikawa
  • Patent number: RE40028
    Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh
    Type: Grant
    Filed: January 7, 2004
    Date of Patent: January 22, 2008
    Assignee: LG. Philips LCD Co., Ltd.
    Inventors: Kwangjo Hwang, Changwook Han
  • Patent number: RE41632
    Abstract: The present invention discloses a method of manufacturing a liquid crystal display device including a first photolithography process forming a gate electrode on a substrate; a second photolithography process including: a) depositing sequentially a gate insulating layer, first and second semiconductor layers, and a metal layer; b) applying a first photoresist on the metal layer; c) aligning a first photo mask with the substrate; d) light exposing and developing the first photoresist to produce a first photoresist pattern; e) etching the metal layer using a first etchant, the first etchant ashing the first photoresist pattern on a predetermined portion of the metal layer to produce a second photoresist pattern, thereby exposing the predetermined portion of the metal layer; and f) etching the gate insulating layer, the first and second semiconductor layer, and the predetermined portion of the metal layer using a second etchant according to the second photoresist pattern to form source and drain electrodes, an oh
    Type: Grant
    Filed: November 16, 2007
    Date of Patent: September 7, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Kwangjo Hwang, Changwook Han