Abstract: A resist pattern (5) is formed in a dimension of a limitation of an exposure resolution over a hard mask material film (4) over a work film (3). The material film (4) is processed using the resist pattern (5) as a mask. A hard mask pattern (6) is thereby formed. Thereby a resist pattern (7), over a non-selected region (6b), having an opening (7a) through which a selection region (6a) in the mask pattern is exposed is formed. Only the mask pattern (6a) exposed through the opening (7a) is slimmed by performing a selection etching, the work film (3) is etched by using the mask pattern (6). A work film pattern (8) is thereby formed, which include a wide pattern section (8a) of a dimension width of the limitation of the exposure resolution and a slimmed pattern section (8a) of a dimension that is not more than the limitation of the exposure resolution.

Abstract: III-V based compounds are etched to produce smooth sidewalls for electro-optical applications using BCl3 together with chemistries of CH4 and H2 in RIE and/or ICP systems. HI or IBr or some combination of group VII gaseous species (Br, F, I) may be added in accordance with the invention.

Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.

Abstract: The invention provides a laser etching method for optical ablation working by irradiating a work article formed of an inorganic material with a laser light from a laser oscillator capable of emitting in succession light pulses of a large energy density in space and time with a pulse radiation time not exceeding 1 picosecond, wherein, in laser etching of the work article formed of the inorganic material by irradiation thereof with the laser light from the laser oscillator with a predetermined pattern and with a predetermined energy density, there is utilized means for preventing deposition of a work by-product around the etching position.

Abstract: A method for in situ formation of low defect, strained silicon and a device formed according to the method are disclosed. In one embodiment, a silicon germanium layer is formed on a substrate, and a portion of the silicon germanium layer is removed to expose a surface that is smoothed with a smoothing agent. A layer of strained silicon is formed on the silicon germanium layer. In various embodiments, the entire method is conducted in a single processing chamber, which is kept under vacuum.

Abstract: A heterostructure comprising: a buffer layer; a bottom barrier layer formed on the buffer layer; a quantum well layer formed on the bottom barrier layer; a top barrier layer formed on the quantum well layer; and a p-doped cap layer formed on the top barrier layer; wherein a portion of the cap layer is etched to form conducting electrons in the quantum well layer below the etched portion of the cap layer. A method of etching comprising the steps of: providing a heterostructure; providing an etchant solution comprising acetic acid, hydrogen peroxide, and water; and contacting the etchant solution to the heterostructure to etch the heterostructure.

Abstract: A method for fabricating a nitride semiconductor element according to the present invention comprises the steps of: forming a nitride semiconductor layer 13 on a base substrate 11; forming, on part of the upper surface of the nitride semiconductor layer 13, a conductive film 14 made of an electron emitting layer 14b and a dry etching mask layer 14a from bottom to top; performing dry etching on the nitride semiconductor layer 13; and performing wet etching on the nitride semiconductor layer 13 by emitting electrons from the nitride semiconductor layer 13 through the conductive film 14 to the outside.

Abstract: The present invention provides a method of forming a strained semiconductor layer. The method comprises growing a strained first semiconductor layer, having a graded dopant profile, on a wafer, having a first lattice constant. The dopant imparts a second lattice constant to the first semiconductor layer. The method further comprises growing a strained boxed second semiconductor layer having the second lattice constant on the first semiconductor layer and growing a sacrificial third semiconductor layer having the first lattice constant on the second semiconductor layer. The method further comprises etch annealing the third and second semiconductor layer, wherein the third semiconductor layer is removed and the second semiconductor layer is relaxed.

Abstract: Antimony-based semiconductor devices are formed over a substrate structure (10) that includes an antimony-based buffer layer (24) and an antimony-based buffer cap (26). Multiple epitaxial layers (30–42) formed over the substrate structure (10) are dry etched to form device mesas (12) and the buffer cap (26) provides a desirably smooth mesa floor and electrical isolation around the mesas.

Abstract: The present invention provides a method and an apparatus for establishing endpoint during an alternating cyclical etch process or time division multiplexed process. A substrate is placed within a plasma chamber and subjected to an alternating cyclical process having an etching step and a deposition step. A variation in plasma emission intensity is monitored using known optical emission spectrometry techniques. An amplitude information is extracted from a complex waveform of the plasma emission intensity using an envelope follower algorithm. The alternating cyclical process is discontinued when endpoint is reached at a time that is based on the monitoring step.

Abstract: A method of making a micro corner cube array includes the steps of: providing a substrate, at least a surface portion of which consists of cubic single crystals and which has a surface that is substantially parallel to {111} planes of the crystals; and dry-etching the surface of the substrate anisotropically with an etching gas that is reactive with the substrate, thereby forming a plurality of unit elements of the micro corner cube array on the surface of the substrate. Each of the unit elements is made up of a number of crystal planes that have been etched at a lower etch rate than the {111} planes of the crystals.

Abstract: A semiconductor structure including a semiconductor substrate, at least one first crystalline epitaxial layer on the substrate, the first layer having a surface which is planarized, and at least one second crystalline epitaxial layer on the at least one first layer. In another embodiment of the invention there is provided a semiconductor structure including a silicon substrate, and a GeSi graded region grown on the silicon substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing. In yet another embodiment of the invention there is provided a semiconductor structure including a semiconductor substrate, a first layer having a graded region grown on the substrate, compressive strain being incorporated in the graded region to offset the tensile strain that is incorporated during thermal processing, the first layer having a surface which is planarized, and a second layer provided on the first layer.

Abstract: A dual damascene process is disclosed. According to the dual damascene process of the present invention, a first recessed region through an intermetal dielectric layer is filled with a bottom protecting layer, and the bottom protecting layer and the intermetal dielectric layer are simultaneously etched to form a second recessed region that has a shallower depth and wider width than the first recessed region on the first recessed region by using an etch gas selectively etches the intermetal dielectric layer with respect to the bottom protecting layer. In other words, the etch selectivity ratio, the intermetal dielectric layer with respect to the bottom protecting layer, is preferably about 0.5 to about 1.5. Thus, it is possible to form a dual damascene structure without the formation of a byproduct or an oxide fence.

Abstract: A process for making a laser structure. The process is for the fabrication of a laser device such a vertical cavity surface emitting laser (VCSEL). The structures made involve dielectric and spin-on material planarization over wide and narrow trenches, coplanar contacts, non-coplanar contacts, thick and thin pad dielectric, air bridges and wafer thinning.

Abstract: A dual damascene structure with a lesser degree of shoulder loss is achieved. In a method for forming a dual damascene structure having a shoulder in an organic low k film layer by dry-etching the organic low k film layer 208 and a mask layer 210 formed over the organic low k film 208 using at least two different mixed gases, a first step in which the mask layer is etched using a first process gas and then the organic low k film layer is etched into a predetermined depth by continuously using the first process gas and a second step following the first step, in which the organic low k film layer is etched using a second process gas are executed. Since a protective wall is formed at a side wall of a via during the first step, the extent of the shoulder loss occurring in the junction region where a trench and a via form a junction can be reduced.

Abstract: Organic etch residues are often left within vias formed by etching through resist masks. Since the etch is designed to expose an underlying metal layer and is directional in order to produce vertical via sidewalls, the residue often incorporates metal. The present invention discloses a method of removing such etch residues while passivating exposed metal, including exposing the residue to ammonia. In the disclosed embodiment, ammonia and oxygen are mixed in a plasma step, such that the resist can be burned off at the same time as the residue treatment. The residue can thus be easily rinsed away.

Abstract: A first Group III nitride compound semiconductor layer 31 is etched, to thereby form an island-like structure such as a dot-like, stripe-shaped, or grid-like structure, so as to provide a trench/post. Thus, a second Group III nitride compound layer 32 can be epitaxially grown, vertically and laterally, from a top surface of the post and a sidewall/sidewalls of the trench serving as a nucleus for epitaxial growth, to thereby bury the trench and also grow the layer in the vertical direction. In this case, propagation of threading dislocations contained in the first Group III nitride compound semiconductor layer 31 can be prevented in the upper portion of the second Group III nitride compound semiconductor 32 that is formed through lateral epitaxial growth. As a result, a region having less threading dislocations is formed at the buried trench.

Abstract: A method of producing a field emission device includes laying a group III-nitride semiconductor layer over a substrate, placing a photoresist mask over the group III-nitride semiconductor layer, patterning a generally circular grid in the photoresist mask and the group III-nitride semiconductor layer, and forming the group III-nitride semiconductor layer into generally pointed tips using an inductively coupled plasma dry etching process, wherein the group III-nitride semiconductor layer comprises a group III-nitride semiconductor material having a low positive electron affinity or a even a negative electron affinity, wherein the inductively coupled plasma dry etching process selectively creates an anisotropic deep etch in the group III-nitride semiconductor layer, and wherein the inductively coupled plasma dry etching process creates an isotropic etch in the group III-nitride semiconductor layer. Preferably, the photoresist layer is approximately 1.

Abstract: In one embodiment, a method of forming a multijunction solar cell having lattice mismatched layers and lattice-matched layers comprises growing a top subcell having a first band gap over a growth semiconductor substrate. A middle subcell having a second band gap is grown over the top subcell, and a lower subcell having a third band gap is grown over the middle subcell. The lower subcell is substantially lattice-mismatched with respect to the growth semiconductor substrate. The first band gap of the top subcell is larger than the second band gap of the middle subcell. The second band gap of the middle subcell is larger than the third band gap of the lower subcell. A support substrate is formed over the lower subcell, and the growth semiconductor substrate is removed. In various embodiments, the multijunction solar cell may further comprise additional lower subcells. A parting layer may also be provided between the growth substrate and the top subcell in certain embodiments.

Abstract: On a multilayer film which is formed on a semiconductor substrate, an opening which is opened on a base and an emitter is formed in the multilayer film, and after an SiGe/SiGeC film, which has a composition with a higher content of Si in an upper layer region and a lower layer region, and a higher content of Ge in an intermediate layer region, is formed on an entire surface, anisotropic dry etching is performed for the SiGe/SiGeC film up to a predetermined height of the opening.

Abstract: A patterning method for fabricating integrated circuits. The method includes forming a material layer over a substrate and then forming a photoresist layer over the material layer. The photoresist layer has a thickness small enough to relax the limitations when the photoresist layer is patterned in a photolithographic process. A shroud liner is formed over the photoresist layer such that height of the shroud liner is significantly greater than width of the shroud liner. Thereafter, the shroud liner undergoes a processing treatment to remove the sections attached to the sidewalls of the photoresist layer. Using the remaining shroud liner as an etching mask, an etching operation is carried out to pattern the material layer.

Abstract: A substrate whose elemental constituents are selected from Groups III and V of the Periodic Table, is provided with pre-defined masked regions. Etching of the substrate comprising the steps of: a) forming a gas containing molecules having at least one methyl group (CH3) linked to nitrogen into a plasma; and b) etching the unmasked regions of the substrate by means of the plasma. For a substrate whose elemental constituents are selected from Groups II and VI of the Periodic Table, the plasma etching gas used is trimethylamine. Since the methyl compound of nitrogen has a lower bond energy than for hydrocarbon mixtures, free methyl radicals are easier to obtain and the gas is more efficient as a methyl source. In addition, compared with hydrocarbon mixtures, reduced polymer formation can be expected due to preferential formation of methyl radicals over polymer-generating hydrocarbon radicals because of the lower bond energy for the former.

Abstract: Conventional methods of semiconductor fabrication and processing typically utilize three gas (e.g., HBr, Cl2 and O2) and four gas (e.g., HBr, Cl2, O2 and CF4) chemistries to perform gate etching in plasma process chambers. However, the silicon to resist selectivity achieved by these chemistries is limited to about 3:1. The present invention concerns a plasma source gas comprising SF6 and one or more fluorine-containing gases selected from C3F6, C4F8, C5F8, CH2F2, CHF3, and C4F6 (e.g., SF6 and C4F8), allowing the use of a two gas etch chemistry that provides enhanced silicon to photoresist selectivity in gate etching processes.

Abstract: A lithography process for creating patterns in an activating light curable liquid using electric fields followed by curing of the activating light curable liquid is described. The process involves the use of a template that is formed of non-conductive and electrically conductive portions. The template is brought into close proximity to the activating light curable liquid on the substrate. An external electric field is applied to the template-substrate interface while maintaining a uniform, carefully controlled gap between the template and substrate. This causes the activating light curable liquid to be attracted to the raised portions of the template. Activating light is applied to the curable liquid while an electric field is applied to the template to create a patterned layer on the substrate.

Abstract: The invention provides a laser etching method for optical ablation working by irradiating a work article formed of an inorganic material with a laser light from a laser oscillator capable of emitting in succession light pulses of a large energy density in space and time with a pulse radiation time not exceeding 1 picosecond, wherein, in laser etching of the work article formed of the inorganic material by irradiation thereof with the laser light from the laser oscillator with a predetermined pattern and with a predetermined energy density, there is utilized means for preventing deposition of a work by-product around the etching position.

Abstract: Drive circuitry to provide a DC bias voltage and a high frequency modulation current to an electroabsorption modulator (EAM), including a high frequency modulation current source, a coupling capacitor, and a first DC lead. The drive circuitry may include termination circuitry. One lead of the high frequency modulation current source is electrically coupled to the first semiconductor type contact of the EAM and the other lead of the high frequency modulation current source is electrically coupled to an AC ground. The coupling capacitor includes a first electrode electrically coupled to the second semiconductor type contact of the EAM, a second electrode electrically coupled to the AC ground, and a dielectric layer between the electrodes. The first DC lead is electrically coupled to the EAM-side capacitor electrode and configured to be coupled to a first DC potential.

Abstract: A method for etching a feature in a layer through an etching mask is provided. A protective layer is formed on exposed surfaces of the etching mask and vertical sidewalls of the feature with a passivation gas mixture. The feature is etched through the etching mask with reactive etching mixtures containing at least one etching chemical and at least one passivation chemical.

Abstract: A plasma etching method for improving an etching profile including providing a substrate including an oxide containing insulating layer in a multilayer semiconductor device; providing a patterned photoresist layer exposing an uppermost layer of the substrate for anisotropically plasma etching a first opening; anisotropically plasma etching through a thickness of at least a portion of the substrate to form the first opening; blanket depositing an etching stop liner to cover at least a portion of the sidewalls of the first opening; patterning according to a photolithographic process for etching a second opening at least partially overlying and encompassing the first opening; and, anisotropically plasma etching through at least another portion of the thickness of the substrate including the first opening to form a second opening at least partially overlying a remaining portion of the first opening.

Abstract: This invention relates to a method of heating an insulating layer, such as is found in semiconductor devices, in which a formation has been etched through a layer of resist comprising reactive etching the resist, inhibiting absorption of or removing water vapour and/or oxygen at the exposed surfaces of the etched formation and filling the formation with conductive metal in the absence of said water vapour and/or oxygen.

Abstract: Thinning and dicing substrates using inductively coupled plasma reactive ion etching (ICP RIE). When dicing, a hard photo-resist pattern or metal mask pattern that defines scribe lines is formed on a sapphire substrate or on a semiconductor epitaxial layer, beneficially by lithographic techniques. Then, the substrate is etched along the scribe lines to form etched channels. An etching gas comprised of BCl3 and/or BCl3/Cl2 gas is used (optionally, Ar can be added). Stress lines are then produced through the substrate along the etched channels. The substrate is then diced along the stress lines. When thinning, a surface of a substrate is subjected to inductively coupled plasma reactive ion etching (ICP RIE) using BCl3 and/or BCl3/Cl2 gas, possibly with some Ar. ICP RIE is particularly useful when working sapphire and other hard substrates.

Abstract: A nanomachining method for producing high-aspect ratio precise nanostructures. The method begins by irradiating a wafer with an energetic charged-particle beam. Next, a layer of patterning material is deposited on one side of the wafer and a layer of etch stop or metal plating base is coated on the other side of the wafer. A desired pattern is generated in the patterning material on the top surface of the irradiated wafer using conventional electron-beam lithography techniques. Lastly, the wafer is placed in an appropriate chemical solution that produces a directional etch of the wafer only in the area from which the resist has been removed by the patterning process. The high mechanical strength of the wafer materials compared to the organic resists used in conventional lithography techniques with allows the transfer of the precise patterns into structures with aspect ratios much larger than those previously achievable.

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract: First, a substrate, on which a plurality of semiconductor devices is formed, is provided. Next, a first etching treatment is carried out to the substrate with a first etching gas comprising CF4 to form a base trench having a rounded-off upper edge or tapered upper edge. A second etching treatment is carried out to the substrate to form a trench region at the base trench so that the trench region has a rounded-off upper edge. And then, an insulating layer is formed on the substrate to fill up the trench region therewith.

Abstract: A phase-change memory may have a tapered lower electrode coated with an insulator. The coated, tapered electrode acts as a mask for a self-aligned trench etch to electrically separate adjacent wordlines. In some embodiments, the tapered lower electrode may be formed over a plurality of doped regions, and isotropic etching may be used to taper the electrode as well as part of the underlying doped regions.

Abstract: A semiconductor device having a thinned semiconductor element that can be easily handled is manufactured with a method of manufacturing. The semiconductor device includes a semiconductor element and a bumper member bonded, as a reinforcing member, to a back surface opposite to an electrode-formed surface of the semiconductor element with an adhesive. The adhesive has a low elastic modulus and easily expands and contracts after bonding, and bonds the semiconductor element to the bumper member while allowing the semiconductor element to be deformed. Thus, the semiconductor device can be easily handled, and the semiconductor element can be deformed in response to the deformation of a substrate after being mounted. In addition, a thermal stress in a heat cycle can be alleviated effectively.

Abstract: This invention relates to a method for reducing halogen gasses and byproducts in post-etch applications. The method consists of exposing the substrate to O2/N2 plasma and water vapor in a process chamber.

Abstract: In one illustrative embodiment, the method comprises forming a gate insulation layer above a substrate, forming a layer of polysilicon above the gate insulation layer, implanting a dopant material into the layer of polysilicon, forming an undoped layer of polysilicon above the doped layer of polysilicon and performing an etching process on the undoped layer of polysilicon and the doped layer of polysilicon to define a gate electrode having a width at an upper surface that is greater than a width of the gate electrode at a base of the gate electrode. In further embodiments, the method comprises forming a layer of refractory metal above the gate electrode and performing at least one heating process to form a metal silicide region on the gate electrode structure.

Abstract: A method for reducing electrical charge imbalances in a semiconductor process wafer including providing a semiconductor process wafer including a dielectric insulating layer; exposing the semiconductor process wafer to a semiconductor process whereby an electrical charge imbalance accumulates in charge imbalance portions of the dielectric insulating layer; and, treating the semiconductor process wafer with a controlled atmosphere of treatment gas including at least one of inert gas and hydrogen to reduce an accumulated charge imbalance in the charge imbalance portions.

Abstract: A method for removal of post reactive ion etch by-product from a semiconductor wafer surface or microelectronic composite structure comprising: supplying a reducing gas plasma incorporating a forming gas mixture selected from the group consisting of a mixture of N2/H2 or a mixture of NH3/H2 into a vacuum chamber in which a semiconductor wafer surface or a microelectronic composite structure is supported to form a post-RIE polymer material by-product on the composite structure without significant removal of an organic, low K material which has also been exposed to the reducing gas plasma; and removing the post-RIE polymer material by-product with a wet clean.

Abstract: There is disclosed a method of manufacturing of optical devices, for example, semiconductor optoelectronic devices such as laser diodes, optical modulators, optical amplifiers, optical switches, and the like. There is further disclosed Optoelectronic Integrated Circuits (OEICs) and Photonic Integrated Circuits (PICs) including such devices. According to the present invention there is provided a method of manufacturing an optical device (40), a device body portion (15) from which the device (40) is to be made including a Quantum Well Intermixing (QWI) structure (30), the method including the step of plasma etching at least part of a surface of the device body portion (5) prior to depositing a dielectric layer (51) thereon so as to introduce structural defects at least into a portion (53) of the device body portion (5) adjacent the dielectric layer (51). The structural defects substantially comprise “point” defects.

Abstract: A heterojunction structure has an AlxGa1−xAs layer (0<x≦1), on which an AlyGa1−yAs layer (0≦y≦1 and y<x) is provided and having a band gap energy smaller than that of the AlxGa1−xAs layer and a valence band energy edge higher than that of the AlxGa1−xAs layer. When the AlyGa1−yAs layer is selectively etched, an Au electrode film is formed on a surface of the AlyGa1−yAs layer outside an etching region, a resist pattern is formed covering the Au electrode film and leaving exposed the etching region, and the AlyGa1−yAs layer is selectively removed by etching while irradiating with light, using an etching solution having a Fermi level higher than that of the AlyGa1−yAs layer.

Abstract: The invention relates to a method using dry etching to obtain contamination free surfaces on of a material chosen from the group comprising GaAs, GaAlAs, InGaAsP, and InGaAs to obtain nitride layers on arbitrary structures on GaAs based lasers, and a GaAs based laser manufactured in accordance with the method. The laser surface is provided with a mask masking away parts of its surface to be prevented from dry etching. The laser is then placed in vacuum. Dry etching is then performed using a substance chosen from the group containing: chemically reactive gases, inert gases, a mixture between chemically reactive gases and inert gases. A native nitride layer is created using plasma containing nitrogen. A protective layer and/or a mirror coating is added.

Abstract: The present invention provides different schemes for reducing the size (such as thickness) of at least a semiconductor unit (such as an IC chip) which is to be packaged. It replaces, in packaging at least a semiconductor unit, conventional grinding processes by etching schemes, particularly when the thickness of the semiconductor unit approximates an expected specification. The etching process may be embodied in a way that a semiconductor unit attached to a carrier such as a substrate, or placed onto a seating apparatus such as a chip tray, and properly shielded, is etched by means of using gas such as plasma, or beams of light. The semiconductor unit packaged according to the scheme provided by the present invention can thus be immunized against the failure resulting from die crack or back-side chipping.

Abstract: The method for fabricating a micro machine comprises the step of burying an oxide film 54 in a first semiconductor substrate 6, the step of bonding the first semiconductor substrate to the second semiconductor substrate with an insulation film 18 therebetween, the step of forming a first mask 66 with an opening in a first region and a second region on both sides of the first region, the step of etching the first semiconductor substrate with a first mask 66 and an oxide film 54 as a mask to thereby form a spring portion 20a integral with the first semiconductor substrate between the oxide film and the insulation film to thereby form a torsion bar including the spring portion, the step of forming a second mask 74 with an opening in the first region and the second region, the step of etching the second semiconductor substrate by using the second mask 74, and the step of etching the insulation film 18 in the first region and the second region. The thickness of the torsion bar can be easily controlled.

Abstract: An alternative etching chemistry which can provide inherently anisotropic etching and eliminate notch formation without the need for heavy polymer deposition is provided by the present invention. The etch is performed with a combination of HBr and N2 at substrate temperatures greater than approximately 160° C. to provide an essentially notch-free and carbon-polymer free anisotropic etching process. The alternative etching chemistry allows for the production of substantially vertical features with smooth sidewalls in an Indium containing multiple layered structure in an ICP plasma etch system.

Abstract: On a multilayer film which is formed on a semiconductor substrate, an opening which is opened on a base and an emitter is formed in the multilayer film, and after an SiGe/SiGeC film, which has a composition with a higher content of Si in an upper layer region and a lower layer region, and a higher content of Ge in an intermediate layer region, is formed on an entire surface, anisotropic dry etching is performed for the SiGe/SiGeC film up to a predetermined height of the opening.

Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing half-tone phase-shift film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a half-tone phase-shift photomask by forming patterns to be transferred to a wafer on a photomask blank for a chromium-containing half-tone phase-shift mask. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.

Abstract: A method for manufacturing a monolithic apparatus including a plurality of materials presenting a plurality of coplanar lands includes the steps of: (a) providing a substrate constructed of a first material and presenting a first land; (b) trenching the substrate to effect a cavity appropriately dimensioned to receive a semiconductor structure in an orientation presenting a second land generally coplanar with the first land; (c) depositing an accommodating layer constructed of a second material on the substrate and within the cavity to establish a workpiece; (d) depositing a composition layer constructed of a third material on the substrate; (e) selectively removing portions of the composition layer and the accommodating layer to establish the semiconductor structure; (f) depositing a cap layer constructed of a fourth material on the workpiece; and (g) removing the cap layer to establish a substantially planar face displaced from the plurality of lands by a predetermined distance.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: A method for protecting a passivation layer during a solder bump formation process including providing a semiconductor process wafer having a process surface including at least two metal layers comprising an uppermost metal layer and a lowermost metal layer said lowermost metal layer overlying a passivation layer including metal bonding pad regions; photolithographically patterning and anisotropically etching through a first thickness portion of at least the uppermost metal layer to form a first patterned metal layer portion disposed over the metal bonding pad regions and reveal a second thickness portion including the lowermost metal layer; forming a solder bump over the first patterned metal layer portion according to at least a first reflow process; and, anisotropically etching through the second thickness portion surrounding the completely formed solder bump to reveal the passivation layer.