Silicide Patents (Class 438/721)
  • Patent number: 8895426
    Abstract: A gate-last method for forming a metal gate transistor is provided. The method includes forming an opening within a dielectric material over a substrate. A gate dielectric structure is formed within the opening and over the substrate. A work function metallic layer is formed within the opening and over the gate dielectric structure. A silicide structure is formed over the work function metallic layer.
    Type: Grant
    Filed: May 20, 2010
    Date of Patent: November 25, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Jeff J. Xu
  • Patent number: 8865556
    Abstract: Techniques for forming a smooth silicide without the use of a cap layer are provided. In one aspect, a FET device is provided. The FET device includes a SOI wafer having a SOI layer over a BOX and at least one active area formed in the wafer; a gate stack over a portion of the at least one active area which serves as a channel of the device; source and drain regions of the device adjacent to the gate stack, wherein the source and drain regions of the device include a semiconductor material selected from: silicon and silicon germanium; and silicide contacts to the source and drain regions of the device, wherein an interface is present between the silicide contacts and the semiconductor material, and wherein the interface has an interface roughness of less than about 5 nanometers.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: October 21, 2014
    Assignee: International Business Machines Corporation
    Inventors: Joseph S. Newbury, Kenneth Parker Rodbell, Zhen Zhang, Yu Zhu
  • Patent number: 8765586
    Abstract: Disclosed herein are various methods of forming metal silicide regions on semiconductor devices. In one example, the method includes forming a sacrificial gate structure above a semiconducting substrate, performing a selective metal silicide formation process to form metal silicide regions in source/drain regions formed in or above the substrate, after forming the metal silicide regions, removing the sacrificial gate structure to define a gate opening and forming a replacement gate structure in the gate opening, the replacement gate structure comprised of at least one metal layer.
    Type: Grant
    Filed: December 20, 2011
    Date of Patent: July 1, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Clemens Fitz, Peter Baars, Markus Lenski
  • Patent number: 8691703
    Abstract: A semiconductor device is manufactured by, inter alia: forming second gate lines, arranged at wider intervals than each of first gate lines and first gate lines, over a semiconductor substrate; forming a multi-layered insulating layer over the entire surface of the semiconductor substrate including the first and the second gate lines; etching the multi-layered insulating layer so that a part of the multi-layered insulating layer remains between the first gate lines and the first and the second gate lines; forming mask patterns formed on the respective remaining multi-layered insulating layers and each formed to cover the multi-layered insulating layer between the second gate lines; and etching the multi-layered insulating layers remaining between the first gate lines and between the first and the second gate lines and not covered by the mask patterns so that the first and the second gate lines are exposed.
    Type: Grant
    Filed: August 14, 2012
    Date of Patent: April 8, 2014
    Assignee: SK Hynix Inc.
    Inventors: Suk Ki Kim, Hyeon Soo Kim
  • Patent number: 8569170
    Abstract: It is an object of the present invention to obtain a transistor with a high ON current including a silicide layer without increasing the number of steps. A semiconductor device comprising the transistor includes a first region in which a thickness is increased from an edge on a channel formation region side and a second region in which a thickness is more uniform than that of the first region. The first and second region are separated by a line which is perpendicular to a horizontal line and passes through a point where a line, which passes through the edge of the silicide layer and forms an angle ? (0°<?<45°) with the horizontal line, intersects with an interface between the silicide layer and an impurity region, and the thickness of the second region to a thickness of a silicon film is 0.6 or more.
    Type: Grant
    Filed: December 14, 2009
    Date of Patent: October 29, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Hajime Tokunaga
  • Patent number: 8563429
    Abstract: Methods of forming a metal silicide layer are provided that include exposing polysilicon through just dry etching (JDE) and recessesing an oxide layer through chemical dry etching (CDE). In particular, dry etching is primarily performed to an extent to expose the polysilicon. Then, CDE is secondarily performed to expose the polysilicon. The CDE process includes selecting an etchant source among combinations of NF3 and NH3, HF and NH3, and N2, H2, and NF3, dissociating the etchant source, forming an etchant of NH4F and NH4F.HF through the dissociation, producing solid by-products of (NH4)2SiF6 through the reaction between the etchant and an oxide at a low temperature, and annealing the by-products at a high temperature such that the by-products are sublimated into gas-phase SiF4, NH3, and HF.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 22, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Won-Goo Hur, Kyu-Tae Na, Min Kim, Hyun-Young Kim, Je-Hyeon Park
  • Patent number: 8492286
    Abstract: Embodiment of the present invention provides a method of forming electronic fuse or commonly known as e-fuse. The method includes forming a polysilicon structure and a field-effect-transistor (FET) structure together on top of a common semiconductor substrate, the FET structure having a sacrificial gate electrode; implanting at least one dopant into the polysilicon structure to create a doped polysilicon layer in at least a top portion of the polysilicon structure; subjecting the polysilicon structure and the FET structure to a reactive-ion-etching (RIE) process, the RIE process selectively removing the sacrificial gate electrode of the FET structure while the doped polysilicon layer being substantially unaffected by the RIE process; and converting the polysilicon structure including the doped polysilicon layer into a silicide to form the electronic fuse.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Henry K. Utomo, Ying Li, Gerald L. Leake
  • Patent number: 8470707
    Abstract: A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching a sidewall dielectric and stopping on an etch stop layer, implanting source and drain dopants self aligned to the sidewall spacers, followed by removing a portion of the sidewall dielectric and removing the etch stop layer self aligned to the reduced sidewall spacers prior to forming silicide.
    Type: Grant
    Filed: November 2, 2011
    Date of Patent: June 25, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Weize Xiong, Deborah J. Riley
  • Publication number: 20130157465
    Abstract: Methods are provided for cleaning metal regions overlying semiconductor substrates. A method for removing material from a metal region comprises heating the metal region, forming a plasma from a gas comprising hydrogen and carbon dioxide, and exposing the metal region to the plasma.
    Type: Application
    Filed: February 5, 2013
    Publication date: June 20, 2013
    Inventors: David Chen, Haruhiro Harry Goto, Martina Martina, Frank Greer, Shamsuddin Alokozai
  • Patent number: 8455268
    Abstract: Methods of replacing/reforming a top oxide around a charge storage element of a memory cell and methods of improving quality of a top oxide around a charge storage element of a memory cell are provided. The method can involve removing a first poly over a first top oxide from the memory cell; removing the first top oxide from the memory cell; and forming a second top oxide around the charge storage element. The second top oxide can be formed by oxidizing a portion of the charge storage element or by forming a sacrificial layer over the charge storage element and oxidizing the sacrificial layer to a second top oxide.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: June 4, 2013
    Assignee: Spansion LLC
    Inventors: Chungho Lee, Hiroyuki Kinoshita, Kuo-Tung Chang, Rinji Sugino, Chi Chang, Huaqiang Wu
  • Patent number: 8344461
    Abstract: A MOS solid-state imaging device having: a semiconductor substrate provided with a pair of source and drain regions in a pixel area, the pair of source and drain regions constituting part of a transistor in the pixel area; an insulating film formed over the semiconductor substrate; a wiring layer formed over the insulating film; and a contact plug penetrating through the insulating film to connect either one of the pair of source and drain regions with the wiring layer, wherein a surface area of said one of the pair of source and drain regions is silicided, the surface area contacting with the contact plug, and a width of the surface area is equal to a width of the contact plug.
    Type: Grant
    Filed: September 29, 2010
    Date of Patent: January 1, 2013
    Assignee: Panasonic Corporation
    Inventor: Tomotsugu Takeda
  • Patent number: 8216933
    Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.
    Type: Grant
    Filed: August 31, 2010
    Date of Patent: July 10, 2012
    Assignee: Applied Materials, Inc.
    Inventors: Wei D. Wang, Srinivas Gandikota, Kishore Lavu
  • Patent number: 8202799
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: June 19, 2012
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chaing-Ming Chuang, Shau-Lin Shue
  • Patent number: 8187969
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Hwan Kim
  • Patent number: 8168538
    Abstract: Methods for manufacturing buried silicide lines are described herein, along with high density stacked memory structures. A method for manufacturing an integrated circuit as described herein includes forming a semiconductor body comprising silicon. A plurality of trenches are formed in the semiconductor body to define semiconductor lines comprising silicon between adjacent trenches, the semiconductor lines having sidewalls. A silicide precursor is deposited within the trenches to contact the sidewalls of the semiconductor lines, and a portion of the silicide precursor is removed to expose upper portions of the sidewalls and leave remaining strips of silicide precursor along the sidewalls. Silicide conductors are then formed by inducing reaction of the strips of silicide with the silicon of the semiconductor lines.
    Type: Grant
    Filed: May 26, 2009
    Date of Patent: May 1, 2012
    Assignee: Macronix International Co., Ltd.
    Inventors: Shih-Hung Chen, Tian-Jue Hong
  • Patent number: 8030210
    Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a source/drain region adjacent the gate dielectric; a silicide region on the source/drain region; a metal layer on top of, and physical contacting, the silicide region; an inter-layer dielectric (ILD) over the metal layer; and a contact opening in the ILD. The metal layer is exposed through the contact opening. The metal layer further extends under the ILD. The semiconductor structure further includes a contact in the contact opening.
    Type: Grant
    Filed: March 11, 2010
    Date of Patent: October 4, 2011
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Ya Wang, Chung-Hu Ke, Wen-Chin Lee
  • Patent number: 7939452
    Abstract: In a method of manufacturing a transistor and a method of manufacturing a semiconductor device using the same, the method may include forming a preliminary metal silicide pattern on a single-crystalline silicon substrate and on a polysilicon pattern, and partially etching the preliminary metal silicide pattern to form a first metal silicide pattern on the substrate and a second metal silicide pattern on the polysilicon pattern, the second metal silicide pattern having a line width the same as or smaller than that of the polysilicon pattern. The method may include the transistor having no metal silicide residue on the spacer. Accordingly, an operation failure due to the residue may be prevented or reduced.
    Type: Grant
    Filed: January 30, 2009
    Date of Patent: May 10, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Deog Lee, Ki-Chul Kim
  • Patent number: 7915174
    Abstract: Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
    Type: Grant
    Filed: July 22, 2008
    Date of Patent: March 29, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Kie Y. Ahn, Leonard Forbes
  • Patent number: 7816218
    Abstract: A microelectronic device includes a metal gate with a metal gate upper surface. The metal gate is disposed in an interlayer dielectric first layer. The interlayer dielectric first layer also has an upper surface that is coplanar with the metal gate upper surface. A dielectric etch stop layer is disposed on the metal gate upper surface but not on the interlayer dielectric first layer upper surface.
    Type: Grant
    Filed: August 14, 2008
    Date of Patent: October 19, 2010
    Assignee: Intel Corporation
    Inventors: Jason Klaus, Sean King, Willy Rachmady
  • Patent number: 7781316
    Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: August 24, 2010
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7727897
    Abstract: A method of etching a top electrode/ferroelectric stack using an etch stop layer includes forming a first layer of a first dielectric material on a substrate; forming a bottom electrode in the first layer of a first dielectric material; depositing an etch stop layer on the first layer of the first dielectric material and the bottom electrode, including forming a hole therein; depositing a layer of ferroelectric material and depositing top electrode material on the ferroelectric material to form a top electrode/ferroelectric stack; stack etching the top electrode and ferroelectric material; depositing a layer of a second dielectric material encapsulating the top electrode and ferroelectric material; etching the layer of the second dielectric material to form a sidewall about the top electrode and ferroelectric material; and depositing a second and third layers of the first dielectric material.
    Type: Grant
    Filed: August 30, 2005
    Date of Patent: June 1, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Bruce D. Ulrich, Lisa H. Stecker, Fengyan Zhang, Sheng Teng Hsu
  • Patent number: 7691754
    Abstract: A method for removing a photoresist layer is provided. The method is suitable for a dielectric layer, wherein the dielectric layer has a patterned photoresist layer formed thereon and a metal silicide layer disposed thereunder and there is an etching stop layer disposed between the dielectric layer and the metal silicide layer. The method comprises steps of removing a portion of the dielectric layer by using the patterned photoresist layer as a mask so as to form an opening, wherein the opening exposes a portion of the etching stop layer above the metal silicide layer. the patterned photoresist layer is removed by using an oxygen-free plasma.
    Type: Grant
    Filed: October 18, 2006
    Date of Patent: April 6, 2010
    Assignee: United Microelectronics Corp.
    Inventor: An-Chi Liu
  • Patent number: 7678678
    Abstract: An embodiment includes a process of forming a gate stack that acts to resist the redeposition to the semiconductive substrate of mobilized metal such as from a metal gate electrode. An embodiment also relates to a system that achieves the process. An embodiment also relates to a gate stack structure that provides a composition that resists the redeposition of metal during processing and field use.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: March 16, 2010
    Assignee: Micron Technology, Inc.
    Inventors: Fernando Gonzalez, Don Carl Powell
  • Patent number: 7659159
    Abstract: In a method of fabricating a flash memory device, a semiconductor substrate includes a tunnel insulating layer and a charge storage layer formed in an active region and a trench formed in an isolation region. A first insulating layer is formed to fill a part of the trench. A second insulating layer is formed on the first insulating layer so that the trench is filled. The first and second insulating layers are removed such that the first and second insulating layers remain on sidewalls of the charge storage layer and on a part of the trench. A third insulating layer is formed on the first and second insulating layers so that a space defined by the charge storage layer is filled. The third insulating layer is removed so that a height of the third insulating layer is lowered.
    Type: Grant
    Filed: May 24, 2007
    Date of Patent: February 9, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: Sung Hoon Lee
  • Patent number: 7648917
    Abstract: A manufacturing method of a solid-state imaging device includes: forming a first and second insulating films having different properties on a silicon substrate such that they cover sides of gate electrodes formed on the silicon substrate; subjecting the second insulating film to selective etching, and forming sidewalls on the sides of the gate electrode; subjecting the gate electrode having the sidewalls formed to ion implantation; covering the gate electrode having the sidewalls formed and forming a third insulating film on the silicon substrate; covering with a mask material part of the gate electrodes covered with the third insulating film, and subjecting the substrate to etching to remove exposed third insulating film; and, after removing the mask material, forming a metal film capable of forming a silicide on the silicon substrate such that the metal film covers the gate electrodes and the third insulating film to form a silicide layer.
    Type: Grant
    Filed: September 19, 2007
    Date of Patent: January 19, 2010
    Assignee: Sony Corporation
    Inventors: Kai Yoshitsugu, Kenichi Chiba
  • Patent number: 7605069
    Abstract: A method for fabricating a semiconductor device with a gate is provided. The method includes: forming a gate insulation layer over a substrate; sequentially forming a polysilicon layer, a silicide layer and a hard mask layer over the gate insulation layer; selectively patterning the hard mask layer; etching the silicide layer using the patterned hard mask layer as a mask such that the silicide layer has a cross-sectional etch profile that is negatively sloped; etching the polysilicon layer using the patterned hard mask layer as a mask to form a gate; and performing a light oxidation process to oxidize exposed sidewalls of the polysilicon layer and the silicide layer.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: October 20, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Tae-Woo Jung, Young-Hun Bae
  • Patent number: 7560379
    Abstract: In one aspect, the invention provides a method of fabricating a semiconductive device 200 that comprises forming a raised layer [510] adjacent a gate [340] and over a source/drain [415], depositing a silicidation layer [915] over the gate [340] and the raised layer [510], and moving at least a portion of the silicidation layer [915] into the source/drain [415] through the raised layer [510].
    Type: Grant
    Filed: February 7, 2006
    Date of Patent: July 14, 2009
    Assignee: Texas Instruments Incorporated
    Inventors: Puneet Kohli, Manfred B. Ramin
  • Patent number: 7550372
    Abstract: A method of fabricating conductive lines is described. A substrate having a polysilicon layer thereon is provided. A mask layer having an opening that exposes the polysilicon layer is formed on the polysilicon layer. Then, spacers are formed on the sidewalls of the mask layer. Using the mask layer and the spacers as a mask, a portion of the polysilicon layer is removed until the substrate is exposed. After that, an insulating layer that completely fills the opening is formed over the substrate. The insulating layer has an etching selectivity different from the mask layer. Thereafter, the mask layer is removed to expose the polysilicon layer and then a metal silicide layer is formed on the upper surface of the polysilicon layer.
    Type: Grant
    Filed: August 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Powerchip Semiconductor Corp.
    Inventors: Su-Yuan Chang, Min-San Huang, Hann-Jye Hsu
  • Patent number: 7544621
    Abstract: A method of removing a metal silicide layer on a gate electrode in a semiconductor manufacturing process is disclosed, in which the gate electrode, a metal silicide layer, a spacer, a silicon nitride cap layer, and a dielectric layer have been formed. The method includes performing a chemical mechanical polishing process to polish the dielectric layer using the silicon nitride cap layer as a polishing stop layer to expose the silicon nitride cap layer over the gate electrode; removing the exposed silicon nitride cap layer to expose the metal silicide layer; and performing a first etching process to remove the metal silicide layer on the gate electrode.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: June 9, 2009
    Assignee: United Microelectronics Corp.
    Inventors: Cheng-Kuen Chen, Chih-Ning Wu, Wei-Tsun Shiau, Wen-Fu Yu
  • Patent number: 7544616
    Abstract: A method of forming word lines of a memory includes providing a substrate and forming a conductive layer on the substrate. A metal silicide layer is formed on the conductive layer, and a mask pattern is formed on the metal silicide layer. A mask liner covering the mask pattern and the surface of the metal silicide layer is formed on the substrate to shorten distances between the word line regions. An etching process is performed on the mask liner and the mask pattern until the partial surface of the metal silicide layer is exposed. The metal silicide layer and the conductive layer are etched to form word lines by utilizing the mask liner and the mask pattern as a mask. A silicon content of the metal silicide layer must be less than or equal to 2 for reducing a bridge failure rate between the word lines.
    Type: Grant
    Filed: October 17, 2007
    Date of Patent: June 9, 2009
    Assignee: MACRONIX International Co., Ltd.
    Inventors: Chi-Pin Lu, Ling-Wu Yang
  • Patent number: 7501317
    Abstract: A junction leak current of a transistor including a silicide layer provided on a source/drain region is to be suppressed. After forming a gate electrode over a chip-side surface of a silicon substrate, an insulating layer is formed over the gate electrode. The insulating layer is etched back so as to form a sidewall that covers the sidewall of the gate electrode, and a region adjacent to the sidewall on the chip-side surface of the silicon substrate, where a source/drain region is to be formed, is etched so as to form a generally horizontal scraped section on the chip-side surface. Then a dopant is implanted to the silicon substrate around the gate electrode, to thereby form the source/drain region. On the chip-side surface of the silicon substrate where the gate electrode is provided, a Ni layer is formed, so that the Ni layer is reacted with the silicon substrate thus to form a Ni-silicide layer.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: March 10, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Tomoko Matsuda, Hiroshi Kitajima
  • Patent number: 7425482
    Abstract: A non-volatile memory device and a method for fabricating the same are provided. The method includes: forming a plurality of gate structures on a substrate, each gate structure including a first electrode layer for a floating gate; forming a first insulation layer covering the gate structures and active regions located at each side of the gate structures; forming a second electrode layer over the first insulation layer; and forming a plurality of control gates on the active regions located at each side of the gate structures by performing an etch-back process to the second electrode layer.
    Type: Grant
    Filed: October 12, 2005
    Date of Patent: September 16, 2008
    Assignee: Magna-Chip Semiconductor, Ltd.
    Inventor: Yong-Sik Jeong
  • Patent number: 7396764
    Abstract: The technology which can improve the performance of a MOS transistor in which all the regions of the gate electrode were silicided is offered. A gate insulating film and a gate electrode of an nMOS transistor are laminated and formed in this order on a semiconductor substrate. A source/drain region of the nMOS transistor is formed in the upper surface of the semiconductor substrate. The source/drain region is silicided after siliciding all the regions of the gate electrode. Thus, silicide does not cohere in the source/drain region by the heat treatment at the silicidation of the gate electrode by siliciding the source/drain region after the silicidation of the gate electrode. Therefore, the electric resistance of the source/drain region is reduced and junction leak can be reduced. As a result, the performance of the nMOS transistor improves.
    Type: Grant
    Filed: May 4, 2006
    Date of Patent: July 8, 2008
    Assignee: Renesas Technology Corp.
    Inventor: Shigeki Komori
  • Patent number: 7371333
    Abstract: The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate comprising nickel silicide is exposed to a fluid comprising H3PO4 and H2O at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch nickel silicide from the substrate. In one implementation, at least one of nickel silicide or cobalt silicide is exposed to a fluid comprising H2SO4, H2O2, H2O, and HF at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch the at least one of nickel silicide or cobalt silicide from the substrate.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Prashant Raghu
  • Patent number: 7344985
    Abstract: The invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a gate structure located over a substrate, the gate structure including a gate dielectric layer and gate electrode layer. The semiconductor device may further include source/drain regions located in/over the substrate and adjacent the gate structure, and a nickel alloy silicide located in the source/drain regions, the nickel alloy silicide having an amount of indium located therein.
    Type: Grant
    Filed: October 20, 2006
    Date of Patent: March 18, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Patent number: 7323418
    Abstract: The present invention leverages an etch-back process to provide an electrode cap for a polymer memory element. This allows the polymer memory element to be formed within a via embedded in layers formed on a substrate. By utilizing the etch-back process, the present invention provides tiny electrical contacts necessary for the proper functioning of polymer memory devices that utilize the vias. In one instance of the present invention, one or more via openings are formed in a dielectric layer to expose an underlying layer. A polymer layer is then formed within the via on the underlying layer with a top electrode material layer deposited over the polymer layer, filling the remaining portion of the via. Excess portions of the top electrode material are then removed by an etching process to form an electrode cap that provides an electrical contact point for the polymer memory element.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: January 29, 2008
    Assignee: Spansion LLC
    Inventors: Minh Van Ngo, Angela T. Hui, Sergey D. Lopatin
  • Patent number: 7309655
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Grant
    Filed: September 8, 2006
    Date of Patent: December 18, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Jae Jung
  • Patent number: 7297638
    Abstract: A method of forming patterns in a semiconductor device comprises: forming a conductive film on a substrate; forming an anti-reflective layer on the conductive film; cleaning oxide residues on the anti-reflective layer using a first cleaning solution; cleaning the oxide residues on the anti-reflective layer using a second cleaning solution; forming a photoresist pattern on the anti-reflective layer; and patterning the conductive film using the photoresist pattern.
    Type: Grant
    Filed: February 20, 2004
    Date of Patent: November 20, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ju-Jin An, Soo-Woong Lee
  • Patent number: 7268065
    Abstract: A method of manufacturing a microelectronic device including forming an opening in a dielectric layer located over a substrate, forming a semi-conductive layer substantially conforming to the opening, and forming a conductive layer substantially conforming to the semi-conductive layer. At least a portion of the semi-conductive layer is doped by implanting through the conductive layer. The semi-conductive layer and the conductive layer may then be annealed.
    Type: Grant
    Filed: June 18, 2004
    Date of Patent: September 11, 2007
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Tung Lin, Chih-Wei Chang, Chii-Ming Wu, Mei-Yun Wang, Chiang-Ming Chuang, Shau-Lin Shue
  • Patent number: 7244642
    Abstract: The present invention provides a method of fabricating a microelectronics device. In one aspect, the method comprises depositing a protective layer (510) over a spacer material (415) located over gate electrodes (250) and a doped region (255) located between the gate electrodes (250), removing a portion of the spacer material (415) and the protective layer (510) located over the gate electrodes (250). A remaining portion of the spacer material (415) remains over the top surface of the gate electrodes (250) and over the doped region (255), and a portion of the protective layer (510) remains over the doped region (255). The method further comprises removing the remaining portion of the spacer material (415) to form spacer sidewalls on the gate electrodes (250), expose the top surface of the gate electrodes (250), and leave a remnant of the spacer material (415) over the doped region (255).
    Type: Grant
    Filed: September 16, 2005
    Date of Patent: July 17, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Steven A. Vitale, Hyesook Hong, Freidoon Mehrad
  • Patent number: 7214621
    Abstract: The invention includes methods of forming devices associated with semiconductor constructions. In exemplary methods, common processing steps are utilized to form fully silicided recessed array access gates and partially silicided periphery transistor gates.
    Type: Grant
    Filed: May 18, 2005
    Date of Patent: May 8, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Hasan Nejad, Gordon A. Haller, Thomas Arthur Figura, Ravi Iyer
  • Patent number: 7211516
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefore and a method for manufacturing an integrated circuit including the same. The semiconductor device, among other elements, may include a substrate (110), as well as a nickel silicide region (170) located over the substrate (110), the nickel silicide region (170) having an amount of indium located therein.
    Type: Grant
    Filed: April 1, 2005
    Date of Patent: May 1, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Peijun J. Chen, Duofeng Yue, Amitabh Jain, Sue Crank, Thomas D. Bonifield, Homi Mogul
  • Patent number: 7208409
    Abstract: Fluorine containing regions (70) are formed in the source and drain regions (60) of the MOS transistor. A metal layer (90) is formed over the fluorine containing regions (70) and the source and drain regions (60). The metal layer is reacted with the underlying fluorine containing regions to form a metal silicide.
    Type: Grant
    Filed: March 7, 2005
    Date of Patent: April 24, 2007
    Assignee: Texas Instruments Incorporated
    Inventors: Jiong-Ping Lu, Duofeng Yue, Xiaozhan Liu, Donald S. Miles, Lance S. Robertson
  • Patent number: 7192532
    Abstract: A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: March 20, 2007
    Assignee: Tokyo Electron Limited
    Inventors: Akiteru Koh, Toshihiro Miura, Takayuki Fukasawa, Akitaka Shimizu, Masato Kushibiki, Asao Yamashita, Fumihiko Higuchi
  • Patent number: 7179707
    Abstract: A method for forming a gate electrode in the semiconductor device is disclosed. The disclosed methods for forming a gate electrode in a semiconductor includes forming a polysilicon film and a metal silicide film sequentially on an upper portion of a semiconductor substrate; performing an annealing process to crystallize the metal silicide film, so that etch rate of the crystallized metal silicide film is similar to that of the polysilicon film; and forming a gate electrode by performing an etching process at one time on the metal silicide film and the polysilicon film using the similar etch rates of the crystallized metal silicide film and the polysilicon film. According to the disclosed methods, the tungsten silicide film is crystallized by an annealing process and the polysilicon film and the crystallized tungsten suicide film are etched at one time to prevent any formation of recesses of the polysilicon film, so that it is possible to form the gate electrode pattern having the vertical profile.
    Type: Grant
    Filed: November 26, 2003
    Date of Patent: February 20, 2007
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cha Deok Dong, Ho Min Son
  • Patent number: 7176139
    Abstract: Disclosed is an etching method for semiconductor processing by which a pattern loading phenomenon is reduced. First, plasma is generated while setting a bias power applied to a wafer to zero and applying a source power. After a predetermined time period, an etching process is implemented onto a predetermined layer formed on the wafer by setting the bias power to a predetermined value. Since by-products generated during preceding etching processes can be readily removed during an etching using plasma, an etching process change due to a difference of pattern densities can be reduced. In addition, a progressive pattern loading generated as the number of processed wafers increase, can be prevented.
    Type: Grant
    Filed: April 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Young-Jae Jung
  • Patent number: 7163879
    Abstract: A transistor gate structure that is free from notches is formed by using a hard mask. The hard mask has a bilayer structure of a BARC (bottom antireflective coating) over a silicon dioxide layer. A photoresist layer is formed over a portion corresponding to the gates. A first etch forms the gate structure. Following removal of the photoresist, a second etch completely removes the BARC. The silicon dioxide layer can be removed by a subsequent wet etch with HF.
    Type: Grant
    Filed: May 30, 2002
    Date of Patent: January 16, 2007
    Assignee: Sharp Kabushiki Kaisha
    Inventor: Koji Tamura
  • Patent number: 7148143
    Abstract: The present invention provides a semiconductor device, a method of manufacture therefor, and a method for manufacturing an integrated circuit. The semiconductor device (100), among other possible elements, includes a silicided gate electrode (150) located over a substrate (110), the silicided gate electrode (150) having gate sidewall spacers (160) located on sidewalls thereof. The semiconductor device (100) further includes source/drain regions (170) located in the substrate (110) proximate the silicided gate electrode (150), and silicided source/drain regions (180) located in the source/drain regions (170) and at least partially under the gate sidewall spacers (160).
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: December 12, 2006
    Assignee: Texas Instruments Incorporated
    Inventors: Haowen Bu, Jiong-Ping Lu, Shaofeng Yu, Ping Jiang, Clint Montgomery
  • Patent number: 7122477
    Abstract: The present invention is a plasma processing method including: a step of introducing a substrate into a processing container, a metal or metallic compound film being formed on a surface of the substrate; a step of supplying a noble gas and an H2 gas into the processing container; and a step of generating plasma in the processing container while the noble gas and the H2 gas are supplied, so that a natural oxide film formed on a surface of the metal or metallic compound film is removed by means of the plasma. According to the invention, the noble gas and the H2 gas are supplied into the processing container, the plasma is generated in the processing container, and the plasma acts on the natural oxide film formed on a surface of the metal or metallic compound film. Thus, active hydrogen in the plasma reduces the natural oxide film, and active species of the noble gas etch the natural oxide film. As a result, the natural oxide film can be removed with a satisfactory selective ratio.
    Type: Grant
    Filed: September 11, 2002
    Date of Patent: October 17, 2006
    Assignee: Tokyo Electron Limited
    Inventor: Taro Ikeda
  • Patent number: 7115523
    Abstract: A process is provided for etching a silicon based material in a substrate, such as a photomask, to form features with straight sidewalls, flat bottoms, and high profile angles between the sidewalls and bottom, and minimizing the formation of polymer deposits on the substrate. In the etching process, the substrate is positioned in a processing chamber, a processing gas comprising a fluorocarbon, which advantageously is a hydrogen free fluorocarbon, is introduced into the processing chamber, wherein the substrate is maintained at a reduced temperature, and the processing gas is excited into a plasma state at a reduced power level to etch the silicon based material of the substrate. The processing gas may further comprise an inert gas, such as argon.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: October 3, 2006
    Assignee: Applied Materials, Inc.
    Inventors: Brigitte C. Stoehr, Michael D. Welch, Melisa J. Buie