Abstract: A method of manufacturing quantum dots includes placing nickel powder having a certain particle size, a precursor material, and an organic solvent into a container, maintaining a pressure in the container at a certain value, and synthesizing quantum dots by stirring the nickel powder, the precursor material, and the organic solvent in the container.

Abstract: Systems and methods for thermal treatment of a workpiece are provided. In one example, a method for conducting a treatment process on a workpiece, such as a thermal treatment process, an annealing treatment process, an oxidizing treatment process, or a reducing treatment process in a processing apparatus is provided. The processing apparatus includes a plasma chamber and a processing chamber. The plasma chamber and the processing chamber are separated by a plurality of separation grids or grid plates. The separation grids or grid plates operable to filter ions generated in the plasma chamber. The processing chamber has a workpiece support operable to support a workpiece.

Abstract: Exemplary etching methods may include flowing a halogen-containing precursor into a remote plasma region of a semiconductor processing chamber while striking a plasma to produce plasma effluents. The methods may include contacting a substrate housed in a processing region with the plasma effluents. The substrate may define an exposed region of tungsten oxide. The contacting may produce a tungsten oxy-fluoride material. The methods may include flowing an etchant precursor into the processing region. The methods may include contacting the tungsten oxy-fluoride material with the etchant precursor. The methods may include removing the tungsten oxy-fluoride material.

Abstract: A plasma processing method for processing a silicon containing film formed on a substrate including a step of removing a reaction product with a first plasma formed from a first gas containing halogen, hydrogen, and carbon in a case where the reaction product is formed when performing an etching process on the silicon containing film by using an etching mask having an etching pattern.

Abstract: An electronic device includes a substrate, a first conductive layer disposed over the substrate, an organic insulating layer, including an organic material, disposed over the first conductive layer and having an aperture exposing a portion of the first conductive layer, a second conductive layer, which is metallic, covering a top face of the organic insulating layer, an inner circumferential face that faces the aperture in the organic insulating layer, and the exposed portion of the first conductive layer, and an intermediate layer that includes an oxide or a nitride, disposed only between the second conductive layer and the inner circumferential face that faces the aperture in the organic insulating layer. The first conductive layer and the second conductive layer are in contact at the bottom face of the aperture in the organic insulating layer.

Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor including a silicon region, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, a first insulating layer, a second insulating layer, a third insulating layer, and a second transistor, which includes an oxide semiconductor layer over the third insulating layer, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode, and a fourth insulating layer and a fifth insulating layer. A first electrode passes through the first insulating layer and the second insulating layer to be electrically connected to the silicon region, and a second electrode passes through the third insulating layer, the fourth insulating layer and the fifth insulating layer to be electrically connected to the first electrode.

Abstract: A method is provided for fabricating an ultra short gate length thin film transistor. A plurality of layers is deposited on a substrate including a refractory metal and a first and second photosensitive material. The second material is sensitive to longer wavelength optical radiation than the first material and the first material is not soluble in chemicals used to develop or strip the second material. A source contact pattern is defined in the second material to mask the first photosensitive material. The first material is processed to produce an undercut of the first material with respect to the second material. A metal layer is deposited at a normal incidence on the second material and an exposed portion of the refractory metal. The second material is removed. Exposed portions of the refractory metal corresponding to the undercut of the first material are removed to form a gap in the refractory metal.

Abstract: Undesirable heating of a semiconductor process ring is prevented by thermally isolating the process ring from the insulating puck of an electrostatic chuck, and providing a thermally conductive and electrically insulating thermal ring contacting both the semiconductor process ring and an underlying metal base having internal coolant flow passages.

Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.

Abstract: An object is to provide a deposition technique for depositing an oxide semiconductor film. Another object is to provide a method for manufacturing a highly reliable semiconductor element using the oxide semiconductor film. A novel sputtering target obtained by removing an alkali metal, an alkaline earth metal, and hydrogen that are impurities in a sputtering target used for deposition is used, whereby an oxide semiconductor film containing a small amount of those impurities can be deposited.

Abstract: Some embodiments include methods of forming memory cells in which a metal oxide material is formed over a first electrode material, an oxygen-sink material is formed over and directly against the metal oxide material, and a second electrode material is formed over the oxygen-sink material. The second electrode material is of a different composition than the oxygen-sink material. The metal oxide material is treated to transfer oxygen from a region of the metal oxide material to the oxygen-sink material and thereby subdivide the metal oxide material into at least two regions, with one of the regions nearest the oxygen-sink material being relatively oxygen depleted relative to another of the regions.

Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch using plasma effluents formed from a fluorine-containing precursor in combination with ammonia (NH3). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. Increasing a flow of ammonia during the process removes a typical skin of tungsten oxide having higher oxidation coordination number first and then selectively etching lower oxidation tungsten oxide. In some embodiments, the tungsten oxide etch selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region.

Abstract: A chemical vapor deposition reactor and method. Reactive gases, such as gases including a Group III metal source and a Group V metal source, are introduced into the chamber (10) of a rotating-disc reactor and directed downwardly onto a wafer carrier (32) and substrates (40) which are maintained at an elevated substrate temperature, typically above about 400° C. and normally about 700-1100° C. to deposit a compound such as a III-V semiconductor. The gases are introduced into the reactor at an inlet temperature desirably above about 75° C. and most preferably about 100°-350° C. The walls of the reactor may be at a temperature close to the inlet temperature. Use of an elevated inlet temperature allows the use of a lower rate of rotation of the wafer carrier, a higher operating pressure, lower flow rate, or some combination of these.

Abstract: One object is to provide a deposition technique for forming an oxide semiconductor film. By forming an oxide semiconductor film using a sputtering target including a sintered body of a metal oxide whose concentration of hydrogen contained is low, for example, lower than 1×1016 atoms/cm3, the oxide semiconductor film contains a small amount of impurities such as a compound containing hydrogen typified by H2O or a hydrogen atom. In addition, this oxide semiconductor film is used as an active layer of a transistor.

Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.

Abstract: Hydrogen concentration and oxygen vacancies in an oxide semiconductor film are reduced. Reliability of a semiconductor device which includes a transistor using an oxide semiconductor film is improved. One embodiment of the present invention is a semiconductor device which includes a base insulating film; an oxide semiconductor film formed over the base insulating film; a gate insulating film formed over the oxide semiconductor film; and a gate electrode overlapping with the oxide semiconductor film with the gate insulating film provided therebetween. The base insulating film shows a signal at a g value of 2.01 by electron spin resonance. The oxide semiconductor film does not show a signal at a g value of 1.93 by electron spin resonance.

Abstract: The present disclosure provides a patterning process for an oxide film, including: covering a barrier layer composition on a substrate to form a patterned barrier layer, wherein the barrier layer composition includes an inorganic component and an organic binder with a weight ratio of 50-98:2-50; forming an oxide film on the patterned barrier layer and the substrate, wherein a thickness ratio (D1/D2) of the barrier layer (D1) to the oxide film (D2) is about 5-2000; and lifting off the barrier layer and the oxide film thereon, while leaving portions of the oxide film on the substrate.

Abstract: A method for manufacturing an oxide semiconductor thin film transistor (TFT) is provided, which includes the steps below. A source electrode and a drain electrode are provided. A patterned insulating layer is formed to partially cover the source electrode and the drain electrode, and expose a portion of the source electrode and a portion of the drain electrode. An oxide semiconductor layer is formed to contact the portion of the source electrode and the portion of the drain electrode. A gate electrode is provided. A gate dielectric layer positioned between the oxide semiconductor layer and the gate electrode is provided. An oxide semiconductor TFT is also provided herein.

Abstract: A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.

Abstract: A method for selectively removing nano-crystals on an insulating layer. The method includes providing an insulating layer with nano-crystals thereon; exposing the nano-crystals to a high density plasma comprising a source of free radical chlorine, ionic chlorine, or both to modify the nano-crystals; and removing the modified nano-crystals with a wet etchant.

Abstract: Methods of selectively etching tungsten oxide relative to tungsten, silicon oxide, silicon nitride and/or titanium nitride are described. The methods include a remote plasma etch formed from a fluorine-containing precursor and/or hydrogen (H2). Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the tungsten oxide. The plasmas effluents react with exposed surfaces and selectively remove tungsten oxide while very slowly removing other exposed materials. In some embodiments, the tungsten oxide selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.

Abstract: Wafers having a high K dielectric layer and an oxide or nitride containing layer are etched in an inductively coupled plasma processing chamber by applying a source power to generate an inductively coupled plasma, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 100° C. and 350° C., and etching the wafer with a selectivity of high K dielectric to oxide or nitride greater than 10:1. Wafers having an oxide layer and a nitride layer are etched in a reactive ion etch processing chamber by applying a bias power to the wafer, introducing into the chamber a gas including BCl3, setting the temperature of the wafer to be between 20° C. and 200° C., and etching the wafer with an oxide to nitride selectivity greater than 10:1.

Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum layer on a TiN layer on an HfO2 or ZrO2 layer on a substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a plasma etch process comprises CHF3 and oxygen to selectively etch the TiN, HfO2 or ZrO2 layers with respect to the substrate.

Abstract: Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: Methods are provided for removing an oxide layer from a metal pad on an integrated circuit in order to reduce contact resistance. In one embodiment, aluminum oxide, on the surface of a bond pad substantially comprised of aluminum, is reacted with a first chemical agent to form an inorganic salt, and the inorganic salt is then reacted with a second chemical agent leaving a substantially bare, that is, unoxidized, aluminum surface.

Abstract: To remove the deposit including a high dielectric constant film deposited on an inside of a processing chamber, by using a cleaning gas activated only by heat. The method includes the steps of: loading a substrate or a plurality of substrates into the processing chamber; performing processing to deposit the high dielectric constant film on the substrate by supplying processing gas into the processing chamber; unloading the processed substrate from the inside of the processing chamber; and cleaning the inside of the processing chamber by supplying a halide gas and an oxygen based gas into the processing chamber, and removing the deposit including the high dielectric constant film deposited on the inside of the processing chamber, and in the step of cleaning the inside of the processing chamber, the concentration of the oxygen based gas in the halide gas and the oxygen based gas is set to be less than 7%.

Abstract: A method of fabricating a patterned magnetic recording medium, comprises steps of: (a) providing a layer stack including an uppermost non-magnetic interlayer; (b) forming a resist layer on the interlayer; (c) forming a first pattern comprising a first group of recesses extending through the resist layer and exposing a first group of spaced apart surface portions of the interlayer; (d) filling the first group of recesses with a layer of a hard mask material; (e) selectively removing the resist layer to form a second pattern comprising a second group of recesses extending through the hard mask layer and exposing a second group of spaced apart surface portions of the interlayer; and (f) filling the second group of recesses with a layer of a magnetically hard material forming a magnetic recording layer.

Abstract: A method is disclosed for the selective etching of a multi-layer metal oxide stack comprising a platinum or tungsten layer on a TiN layer on an HfO2 or ZrO2 layer on a silicon substrate. In some embodiments, the method comprises a physical sputter process to selectively etch the platinum layer, followed by a first wet etch using a mixture of NH4OH and H2O2 to selectively etch the TiN layer, and a second wet etch using a dilute mixture of HF and HCl to selectively etch the HfO2 or ZrO2 layer.

Abstract: In a semiconductor that has a structure in which a work function controlling metal conductor is provided on a high dielectric insulation film, fine processing is performed without deteriorating a device. In a method of semiconductor processing, in which the semiconductor has an insulation film containing Hf or Zr formed on a semiconductor substrate and a conductor film containing Ti or Ta or Ru formed on an insulation film, and the conductor film is processed by using a resist formed on the conductor film under a plasma atmosphere, the resist is removed under the plasma atmosphere of gas that contains hydrogen and does not contain oxygen.

Abstract: Stabilized precursor solutions can be used to form radiation inorganic coating materials. The precursor solutions generally comprise metal suboxide cations, peroxide-based ligands and polyatomic anions. Design of the precursor solutions can be performed to achieve a high level of stability of the precursor solutions. The resulting coating materials can be designed for patterning with a selected radiation, such as ultraviolet light, x-ray radiation or electron beam radiation. The radiation patterned coating material can have a high contrast with respect to material properties, such that development of a latent image can be successful to form lines with very low line-width roughness and adjacent structures with a very small pitch.

Abstract: A method and apparatus are described for fabricating metal gate electrodes (85, 86) over a high-k gate dielectric layer (32) having a rare earth oxide capping layer (44) in at least the NMOS device area by treating the surface of a rare earth oxide capping layer (44) with an oxygen-free plasma process (42) to improve photoresist adhesion, forming a patterned photoresist layer (52) directly on the rare earth oxide capping layer (44), and then applying a wet etch process (62) to remove the exposed portion of the rare earth oxide capping layer (44) from the PMOS device area.

Abstract: Oxide thin film, electronic devices including the oxide thin film and methods of manufacturing the oxide thin film, the methods including (A) applying an oxide precursor solution comprising at least one of zinc (Zn), indium (In) and tin (Sn) on a substrate, (B) heat-treating the oxide precursor solution to form an oxide layer, and (C) repeating the steps (A) and (B) to form a plurality of the oxide layers.

Abstract: An object is to provide a semiconductor device with a novel structure. A semiconductor device includes a first transistor, which includes a channel formation region provided in a substrate including a semiconductor material, impurity regions, a first gate insulating layer, a first gate electrode, and a first source electrode and a first drain electrode, and a second transistor, which includes an oxide semiconductor layer over the substrate including the semiconductor material, a second source electrode and a second drain electrode, a second gate insulating layer, and a second gate electrode. The second source electrode and the second drain electrode include an oxide region formed by oxidizing a side surface thereof, and at least one of the first gate electrode, the first source electrode, and the first drain electrode is electrically connected to at least one of the second gate electrode, the second source electrode, and the second drain electrode.

Abstract: A method of depositing a bilayer of tungsten over tungsten nitride by a plasma sputtering process in which krypton is used as the sputter working gas during the tungsten deposition. Argon may be used as the sputtering working gas during the reactive sputtering deposition of tungsten nitride. The beneficial effect of reduction of tungsten resistivity is increased when the thickness of the tungsten layer is less than 50 nm and further increased when less than 35 nm. The method may be used in forming a gate stack including a polysilicon layer over a gate oxide layer over a silicon gate region of a MOS transistor in which the tungsten nitride acts as a barrier. A plasma sputter chamber in which the invention may be practiced includes gas sources of krypton, argon, and nitrogen.

Abstract: A method and system for etching a hafnium containing material using a boron tri-chloride (BCl3) based process chemistry is described. A substrate having a hafnium containing layer, such as a layer of hafnium dioxide (HfO2) is subjected a dry etching process comprising BCl3 and an additive gas including: an oxygen-containing gas, such as O2; or a nitrogen-containing gas, such as N2; or a hydrocarbon gas (CxHy), such as CH4; or a combination of two or more thereof.

Abstract: A method of fabricating organic solar arrays for application in DC power supplies for electrostatic microelectromechanical systems (MEMS) devices. A solar array with 20 miniature cells (as small as 1 mm2) interconnected in series is fabricated and characterized. Photolithography is used to isolate individual cells and output contacts of the array, whereas the thermal-vacuum deposition is employed to make the series connections of the array. With 1 mm2 for single cell and a total device area of 2.2 cm2, the organic solar array based on bulk heterojunction structure of ?-conjugated polymers and C60 derivative (6,6)-phenyl C61 butyric acid methyl ester produces an open-circuit voltage of 7.8 V and a short-circuit current of 55 ?A under simulated air mass (AM) 1.5 illumination with an intensity of 132 mW/cm2. The present method can be used in the fabrication of microarrays as small as 0.01 mm2.

Abstract: Substrate processing apparatus 100 includes supporting table 103 for not only supporting a target substrate W but also heating the target substrate W; processing chamber 101 having the supporting table disposed therein; and gas supply unit 102 for supplying a processing gas into the processing chamber 101. The processing gas includes organic acid metal complex or organic acid metal salt.

Abstract: A method according to one embodiment comprises forming a thin film layer; forming a hardmask layer above the thin film layer, the hardmask layer comprising laminated layers of diamond-like carbon; removing a portion of the hardmask layer; and removing a portion of the thin film layer that is unprotected by the hardmask layer. A method according to another embodiment comprises forming a thin film layer; forming a patterned hardmask layer above the thin film layer, the hardmask layer comprising laminated layers of diamond-like carbon; and implanting a material into a portion of the thin film layer that is unprotected by the patterned hardmask layer. Additional methods are disclosed.

Abstract: A method for detecting an end point of a resist peeling process in which a resist is gasified to be peeled off by producing hydrogen radicals by catalytic cracking reaction where a hydrogen-containing gas contacts with a high-temperature catalyst, and contacting the produced hydrogen radicals with a resist on a substrate, includes monitoring one or more parameters indicating a state of the catalyst and detecting the end point of the resist peeling process based on variations of the monitored parameters. The hydrogen-containing gas may be a H2 gas. The parameters indicating the state of the catalyst may be one or more electrical parameters when a power is supplied to the catalyst. Further, the catalyst may be a filament made of a high melting point metal.

Abstract: A two-stage method to remove a metal layer from a substrate surface comprises using a CMP process to remove a first portion of the metal layer from the substrate surface, and using an ALV process to remove a second portion of the copper layer from the substrate surface. The ALV process comprises pulsing a co-reactant into a reactor housing the substrate, wherein the co-reactant reacts with the metal layer to form a volatile metal-containing product, and then evacuating the reactor to volatize and remove the metal-containing product.

Abstract: The present invention provides a method for manufacturing a resistance change element that can reduce occurrence of corrosion without increasing a substrate temperature. A laminate film that includes a high melting-point metal film and a metal oxide film, is etched using a mask under a plasma atmosphere formed using any one of a mixture gas formed by adding at least one gas selected from the group consisting of Ar, He, Xe, Ne, Kr, O2, O3, N2, H2O, N2O, NO2, CO and CO2 to at least one kind of gasified compound selected from alcohol and hydrocarbon or the gas compound.

Abstract: A manufacturing method of a thin film transistor includes forming a pair of source/drain electrodes on a substrate, such that the source/drain electrodes define a gap therebetween; forming low resistance conductive thin films, which define a gap therebetween, on the source/drain electrodes; and forming an oxide semiconductor thin film layer on upper surface of the low resistance conductive thin films and in the gap defined between the low resistance conductive thin films so that the oxide semiconductor thin film layer functions as a channel. The low resistance conductive thin films and the oxide semiconductor thin film layer are etched so that side surfaces of the resistance conductive thin films and corresponding side surfaces of the oxide semiconductor thin film layer coincide with each other in a channel width direction of the channel. A gate electrode is mounted over the oxide semiconductor thin film layer.

Abstract: A thermal anneal process for preventing formation of certain BPSG surface defects following an etch or silicon clean step using a fluorine and hydrogen chemistry. The thermal anneal process is carried out while protecting the wafer from moisture, by heating the wafer to a sufficiently high temperature for a sufficient duration of time to thermally diffuse boron and/or phosphorus materials separated from silicon near the surface of the doped glass layer into the bulk of the layer. The thermal anneal process is completed by cooling the wafer to a sufficiently low temperature to fix the distribution of the boron and/or phosphorus materials in bulk of the doped glass layer.

Abstract: In one implementation, a method is provided for etching a high k dielectric material in a plasma etch reactor, the method comprising plasma etching the high k dielectric material with a first plasma gas reactant mixture having BCl3. The high k dielectric material may include Al2O3 in a stack having a silicon layer. The etching may include supplying a passivation gas, for example C2H4, and may further include supplying a diluent gas such as a noble gas, for example He. In some implementations, the etching may be performed with a reactive ion etch process.

Abstract: Dielectric layers containing a dielectric layer including lanthanum and hafnium and methods of fabricating such dielectric layers provide an insulating layer in a variety of structures for use in a wide range of electronic devices.

Abstract: The thin-film patterning method for a magnetoresistive device comprises forming a functional layer on a substrate; forming a first mask layer above the functional layer; forming a patterned resist on the first mask layer; etching the first mask layer by using the resist; removing the resist; forming a second mask layer by atomic layer deposition, the second mask layer covering a step defined by an edge of the first mask layer; dry-etching the second mask layer in a thickness direction of the substrate so as to leave the second mask layer on a side face of the step; removing the first mask layer so as to expose the functional layer under the first mask; and dry-etching the functional layer by using the second mask layer.

Abstract: An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Abstract: The use of a conductive bidimensional perovskite as an interface between a silicon, metal, or amorphous oxide substrate and an insulating perovskite deposited by epitaxy, as well as an integrated circuit and its manufacturing process comprising a layer of an insulating perovskite deposited by epitaxy to form the dielectric of capacitive elements having at least an electrode formed of a conductive bidimensional perovskite forming an interface between said dielectric and an underlying silicon, metal, or amorphous oxide substrate.

Abstract: A method of forming patterning multilayer metal gate structures for complementary metal oxide semiconductor (CMOS) devices includes performing a first etch process to remove exposed portions of a polysilicon layer included within a gate stack, the polysilicon layer formed on a metal layer also included within the gate stack; oxidizing an exposed top portion of the metal layer following the first etch process so as to create an metal oxide layer having an etch selectivity with respect to the polysilicon layer; removing the metal oxide layer through a combination of a physical ion bombardment thereof, and the introduction of an isotropic chemical component thereto so as to prevent oxide material at bottom corners of the polysilicon layer; and performing a second etch process to remove exposed portions of the metal layer.