Abstract: A process for preventing interconnect metal diffusion into the surrounding dielectric material. Prior to the formation of a metal interconnect in an opening of a dielectric region, the underlying metal surface is cleaned, during which metal can be deposited on the sidewalls of the opening. This metal can diffuse into the dielectric and cause leakage currents. To prevent deposition of the metal onto the sidewalls a barrier layer is deposited into the opening and sputtered onto the sidewalls before the metal surface cleaning step.

Abstract: According to one exemplary embodiment, a method for forming a contact over a silicide layer situated in a semiconductor die comprises a step of depositing a barrier layer on sidewalls of a contact hole and on a native oxide layer situated at a bottom of the contact hole, where the sidewalls are defined by the contact hole in a dielectric layer. The step of depositing the barrier layer on the sidewalls of the contact hole and on the native oxide layer can be optimized such that the barrier layer has a greater thickness at a top of the contact hole than a thickness at the bottom of the contact hole. According to this exemplary embodiment, the method further comprises a step of removing a portion of the barrier layer and the native oxide layer situated at the bottom of the contact hole to expose the silicide layer.

Abstract: An insulating film made of zirconia or hafnia is formed on the surface of a semiconductor substrate. A partial surface area of the insulating film is covered with a mask pattern. By using the mask pattern as a mask, ions are implanted into a region of the insulating film not covered with the mask pattern to give damages to the insulating film. By using the mask pattern as a mask, a portion of the insulating film is etched.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: A major problem in Lead Overlay design for GMR structures is that the magnetic read track width is wider than the physical read track width. This is due to high interfacial resistance between the leads and the GMR layer which is an unavoidable side effect of prior art methods. The present invention uses electroplating preceded by a wet etch to fabricate the leads. This approach requires only a thin protection layer over the GMR layer to ensure that interface resistance is minimal. Using wet surface cleaning avoids sputtering defects and plating is compatible with this so the cleaned surface is preserved Only a single lithography step is needed to define the track since there is no re-deposition involved.

Abstract: A method is provided which includes patterning one or more metal layers arranged above a metal insulating layer and terminating the patterning process upon exposure of the metal insulating layer. In particular, the method may be adapted to be more selective to the metal insulating layer than the one or more metal layers. In general, such an adaptation may include exposing the semiconductor topography to an etch chemistry comprising hydrogen bromide. In some cases, the etch chemistry may further include a fluorinated hydrocarbon. In yet other embodiments, the method may further or alternatively include using a reactive ion etch process, etching at a relatively low temperature, using a resist mask, and/or using an etch chemistry substantially absent of an oxygen plasma. In this manner, the method may, in some embodiments, include patterning the one or more metal layers using a reactive ion etch process substantially absent of an oxygen plasma.

Abstract: A method for releasing from underlying substrate material micromachined structures or devices without application of chemically aggressive substances or excessive forces. The method starts with the step of providing a partially formed device, comprising a substrate layer, a sacrificial layer deposited on the substrate, and a function layer deposited on the sacrificial layer and possibly exposed portions of the substrate layer and then etched to define micromechanical structures or devices therein. The etching process exposes the sacrificial layer underlying the removed function layer material. Next there are the steps of cleaning residues from the surface of the device, and then directing high-temperature hydrogen gas over the exposed surfaces of the sacrificial layer to convert the silicon dioxide to a gas, which is carried away from the device by the hydrogen gas.

Abstract: Methods for etching electrodes formed directly on gate dielectrics are provided. In one aspect, an etch process is provided which includes a main etch step, a soft landing step, and an over etch step. In another aspect, a method is described which includes performing a main etch having good etch rate uniformity and good profile uniformity, performing a soft landing step in which a metal/metal barrier interface can be determined, and performing an over etch step to selectively remove the metal barrier without negatively affecting the dielectric. In another aspect, a method is provided which includes a first non-selective etch chemistry for bulk removal of electrode material, a second intermediate selective etch chemistry with end point capability, and then a selective etch chemistry to stop on the gate dielectric.

Abstract: During manufacture, a magnetoresistive sensor having a ferromagnetic free layer is commonly provided with a tantalum cap layer. The tantalum cap layer provides protection to the sensor during manufacture and then is typically removed after performing annealing. The removal of the tantalum cap with a fluorine reactive ion etch leaves low volatility tantalum/fluorine byproducts. The present invention provides a method of using an argon/hydrogen reactive ion etch to remove the tantalum/fluorine byproducts. The resulting sensor has far less damage resulting from the presence of the fluorine byproducts.

Abstract: This invention relates to manufacturing of integrated circuits (ICs) and especially conductive layers suitable for use in an IC. According to the preferred method a metal oxide thin film is deposited on a substrate surface and reduced thereafter essentially into a metallic form with an organic reducing agent. The metal oxide is preferably deposited according to the principles of atomic layer deposition (ALD) using a metal source chemical and an oxygen source chemical. The reduction step is preferably carried out in an ALD reactor using one or more vaporized organic compounds that contain at least one functional group selected from the group consisting of —OH, —CHO and —COOH.

Abstract: A dual damascene process flow for forming interconnect lines and vias in which at least part of the via (116) is etched prior to the trench etch. A low-k material such as a thermoset organic polymer is used for the ILD (106) and IMD (110). After the at least partial via etch, a BARC (120) is deposited over the structure including in the via (116). Then, the trench (126) is patterned and etched. Although at least some of the BARC (120) material is removed during the trench etch, the bottom of the via (116) is protected.

Abstract: A thin film transistor having a source/drain electrode on an insulating substrate is provided with a metal oxide layer interposed between a source/drain electrode and a metal connecting line. The formation of the metal oxide layer prevents the occurrence of the galvanic phenomenon.

Abstract: It is an object of the present invention to effectively and efficiently inhibit the influence of an eliminated gas from a built-up film deposited in a reaction chamber and reduce an incubation time to improve flatness of a thin film. A manufacturing method of a semiconductor device includes a preprocess step and a film-forming step. In the preprocess step, an RPH (Remote Plasma Hydrogenation) process of supplying a hydrogen radical onto a substrate (202), thereafter, an RPN (Remote Plasma Nitridation) process of supplying a nitrogen radical onto the substrate (203), and thereafter, an RPO (Remote Plasma Oxidation) process of supplying an oxygen radical onto the substrate (204) are performed during a substrate temperature increase for raising a substrate temperature up to a film-forming temperature.

Abstract: A method is disclosed for the induction of a suitable band gap and electron emissive properties into a substance, in which the substrate is provided with a surface structure corresponding to the interference of electron waves. Lithographic or similar techniques are used, either directly onto a metal mounted on the substrate, or onto a mold which then is used to impress the metal. In a preferred embodiment, a trench or series of nano-sized trenches are formed in the metal.

Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.

Abstract: A method for removing silicon oxide from a surface of a substrate is disclosed. The method includes depositing material onto the silicon oxide (110) and heating the substrate surface to a sufficient temperature to form volatile compounds including the silicon oxide and the deposited material (120). The method also includes heating the surface to a sufficient temperature to remove any remaining deposited material (130).

Abstract: The present invention provides a microneedle incorporating a base that is broad relative to a height of the microneedle, to minimize breakage. The microneedle further includes a fluid channel and a beveled non-coring tip. Preferably arrays of such microneedles are fabricated utilizing conventional semiconductor derived micro-scale fabrication techniques. A dot pattern mask is formed on an upper surface of a silicon substrate, with each orifice of the dot pattern mask corresponding to a desired location of a microneedle. Orifices are formed that pass completely through the substrate by etching. A nitride pattern mask is formed to mask all areas in which a nitride layer is not desired. A nitride layer is then deposited on the bottom of the silicon substrate, on the walls of the orifice, and on the top of the silicon substrate around the periphery of the orifice. The nitride layer around the periphery of the orifice is offset somewhat, such that one side of the orifice has a larger nitride layer.

Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.

Abstract: In semiconductor device fabrication processes which include the formation of hardmask elements 17 including Al2O2, unwanted Al2O3 is left between the hardmask elements 17. The unwanted Al2O3 includes a layer 9 of Al2O3which is not homogenous across the surface of the structure 3 it overlies, and Al2O3 deposits on the sides of the hardmask elements 17. A method is proposed in which any such unwanted Al2O3 between the hardmask elements 17 is removed by a wet etching step in which the unwanted Al2O3 is exposed to an etchant liquid which etches the Al2O3 at a faster rate than other portions of the structure. This step allows the unwanted Al2O3 to be removed substantially completely without causing significant detriment to those other portions of the structure. Subsequently, an RIE etching step can be performed using the hardmask elements 17 as a mask, without the unwanted Al2O3 obstructing the RIE etching step.

Abstract: Contaminants are generated during etching processes for forming electrodes of storage capacitors for very high density future memory cells, such as ferroelectric random access memory (FeRAM) cells. These contaminants include significant quantities of noble metals, and in particular iridium and iridium compound particulates. In order to prevent undesirable iridium and iridium compound particulates from adversely affecting subsequent etching processes performed in the chamber, the plasma metal etch chamber is seasoned by exposing interior surfaces of the chamber to a seasoning plasma generated from a gas mixture comprising at least two gases selected from the group consisting of BCl3, HBr, and CF4. The chamber seasoning method of the invention is also applicable to etch processes involving other noble metals, such as platinum.

Abstract: In a plasma processing apparatus according to the present invention, a gas inlet port and a discharge port are provided on a chamber for introducing and discharging gas into and from the chamber respectively. A sample to be etched is placed on an electrode part, so that a high-frequency power source applies a high-frequency bias to the sample. An electromagnet provided on the periphery of a plasma generation area generates a magnetic field while a waveguide connected to an upper potion of the chamber introduces a microwave into the plasma generation area through a microwave introduction window. Electron cyclotron resonance is excited for the gas for generating plasma. At least a surface of the microwave introduction window exposed to the plasma generation area is made of quartz, while the gas contains fluorine. The apparatus having the aforementioned structure can remove a material adhering to the surface of the microwave introduction window when the sample is etched.

Abstract: A system and a method to remove a layer of high-k dielectric material during the manufacturing of an integrated circuit. In one embodiment of the invention, an etch reactant is employed to form volatile etch products when reacted with high-k layers. Alternately, high-k layers can be anisotropically etched of in accordance with a patterned photoresist or hard mask, where a hyperthermal beam of neutral atoms is used to aid in the reaction of an etch reactant with a high-k layer. Alternately, a hyperthermal beam of neutral atoms or a plasma treatment can used to modify a high-k layer, and subsequently etch the modified high-k layer utilizing an etch reactant that reacts with the modified high-k layer. In still another embodiment of the invention, the hyperthermal beam of neutral atoms is used to etch a high-k layer through physical bombardment of the high-k layer.

Abstract: A method for removing silicon oxide from a surface of a substrate is disclosed. The method includes depositing material onto the silicon oxide (110) and heating the substrate surface to a sufficient temperature to form volatile compounds including the silicon oxide and the deposited material (120). The method also includes heating the surface to a sufficient temperature to remove any remaining deposited material (130).

Abstract: A method for integrating a thin film resistor into an interconnect process flow where one of the metal layers is used as a hardmask. After a via (42) etch and fill, the thin film resistor material (62) is deposited. The metal interconnect layer (76) is then deposited, including any barrier layers desired. The metal leads (70) are then etched together with the shape of the thin film resistor (60). The metal (76) over the thin film resistor (60) is then removed.

Abstract: Disclosed herein is a method for forming quantum dots, comprising the steps of (a) depositing a metal thin layer onto a substrate, (b) coating a dielectric precursor onto the metal thin layer, and (c) stepwisely heating the resultant substrate; or a method for forming quantum dots, comprising the steps of (a) mixing a dielectric precursor diluted in a solvent and a metal powder and stirring the mixture, (b) coating the mixture onto a substrate, and (c) heating the resultant substrate. The method can easily control the size, density and uniformity of metal oxide quantum dots.

Abstract: A multimetal oxide material contains the elements Mo, V and Te and/or Sb and at least one of the elements Nb, Ti, W, Ta and Ce and promoters and has a specific X-ray diffraction pattern. Moreover, such a multimetal oxide material is used as a catalyst for heterogeneously catalyzed gas-phase partial oxidations of hydrocarbons.

Abstract: A method for fabricating a high density ferroelectric memory device is disclosed in which the burden of etching a storage electrode and a plate electrode is alleviated, and a ferroelectric capacitor module is made highly dense. A seed layer and a sacrificial layer are sequentially formed on a semiconductor substrate. The sacrificial layer is selectively etched to form a loop-shaped sacrificial layer pattern. First and second electrodes are simultaneously formed on the seed layer (thus exposed) by carrying out an electrochemical deposition process after formation of the sacrificial layer pattern. The sacrificial layer pattern is removed. The seed layer (thus exposed) is etched after removal of the sacrificial layer pattern. A ferroelectric thin film is formed by carrying out a spin-on process on the entire surface including the first and second electrodes.

Abstract: A method for forming a gate of a high integration semiconductor device in which, when forming a gate electrode on a semiconductor substrate by depositing a nitride layer and an anti-reflection layer after depositing a conductive layer constructed by a gate oxide layer, a polysilicon layer, a tungsten nitride layer and a tungsten layer, an etch prevention layer is formed between the nitride layer and the anti-reflection layer in order to prevent the nitride layer from over-etching, thereby preventing the leakage current, caused by the bridge formed between the gate and the bit line, from generating.

Abstract: In a method of manufacturing a contact element, provision is made of a laminated body which has an insulating film, an electrically conductive layer stacked on the insulating film, and bump holes opened. A treatment is carried out so as to remove organic materials and the like from an interior of the bump holes and/or a surface of the insulating film before bumps are formed on the bump holes. The treatment may be a plasma treatment or an X-ray irradiation.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: A dry-etching method comprises the step of dry-etching a metal thin film as a chromium-containing half-tone phase-shift film, wherein the method is characterized by using, as an etching gas, a mixed gas including (a) a reactive ion etching gas, which contains an oxygen-containing gas and a halogen-containing gas, and (b) a reducing gas added to the gas component (a), in the process for dry-etching the metal thin film. The dry-etching method permits the production of a half-tone phase-shift photomask by forming patterns to be transferred to a wafer on a photomask blank for a chromium-containing half-tone phase-shift mask. The photomask can in turn be used for manufacturing semiconductor circuits. The method permits the decrease of the dimensional difference due to the coexistence of coarse and dense patterns in a plane and the production of a high precision pattern-etched product.

Abstract: A process for removing a substance from a substrate, includes: (1) providing the substrate, wherein: (a) the substrate is at least partially coated with the substance; (b) the substance is a transition metal oxide, a transition metal silicate, a Group 13 metal oxide, a Group 13 metal silicate, or mixtures thereof; and (c) the substance has a dielectric constant greater than silicon dioxide; (2) reacting the substance with a reactive gas to form a volatile product, wherein the reactive gas comprises chlorine; and (3) removing the volatile product from the substrate to thereby remove the substance from the substrate, provided that when the substance is Al2O3 and the substrate is a semiconductor from which the substance is being selectively etched, the process is conducted in the absence of a plasma having a density greater than 1011 cm−3. The process is particularly suitable for etching semiconductors and for cleaning reaction chambers.

Abstract: A method of forming a planarized final copper structure including the following steps. A structure is provided having a patterned dielectric layer formed thereover. The patterned dielectric layer having an opening formed therein. A barrier layer is formed over the patterned dielectric layer, lining the opening. An initial planarized copper structure is formed within the barrier layer lined opening, and is planar with the barrier layer overlying the patterned dielectric layer. The initial planarized copper structure is recessed below the barrier layer overlying the patterned dielectric layer a distance to form a recessed copper structure. Any copper oxide formed upon the recessed copper structure is removed. A conductor film is formed over the recessed, copper oxide-free initial copper structure and the barrier layer.

Abstract: A semiconductor device production method that is used to uniformly and efficiently reduce metal oxides produced on metal (copper, for example) which forms electrodes or wirings on a semiconductor device. An object to be treated on which copper oxides are produced is put into a process chamber and is heated by a heater to a predetermined temperature. Then carboxylic acid stored in a storage tank is vaporized by a carburetor. The vaporized carboxylic acid, together with carrier gas, is introduced into the process chamber via a treating gas feed pipe to reduce the copper oxides produced on the object to be treated to metal copper. As a result, metal oxides can be reduced uniformly without making the surfaces of electrodes or wirings irregular. Moreover, in this case, carbon dioxide and water are both produced in a gaseous state. This prevents impurities from remaining on the surface of copper.

Abstract: A method for reducing a fluorine contamination level on a semiconductor wafer process surface including providing a semiconductor wafer surface having a process surface including an uppermost polyimide containing layer; reactive ion etching the process surface to include exposure of the process surface to a hydrofluorocarbon containing plasma; and heating the process surface according to a temperature profile to reduce a fluorine contamination level.

Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.

Abstract: A process for fabricating a semiconductor device, which comprises forming a recess portion in an insulating film covering a wiring made of copper or a copper alloy so that the recess portion reaches the wiring, wherein, after forming the recess portion, a plasma treatment using a gas containing hydrogen gas and nitrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion, or a plasma treatment using a gas containing hydrogen gas is conducted in a state such that the wiring is exposed through the bottom portion of the recess portion while cooling a substrate on which the wiring is formed. By the process of the present invention, a problem of redeposition of copper on the sidewall of a via hole in the argon sputtering and a problem of an etching process of the organic insulating film in the hydrogen plasma treatment can be solved, thus realizing excellent cleaning of the bottom portion of the via hole.

Abstract: A method of fabricating a semiconductor device using a damascene metal gate including the steps of forming a damascene gate oxide layer and a damascene gate electrode on a semiconductor substrate, forming a trench at an upper part of the damascene gate electrode by selectively etching a portion of the damascene gate electrode to a predetermined thickness, forming an insulating layer in the trench on the damascene gate electrode, forming an insulating interlayer on an upper surface of the entire structure, and forming a contact hole exposing a portion of the semiconductor substrate by selectively etching the insulating interlayer.

Abstract: A method of etching high dielectric constant materials using halogen gas and reducing gas chemistry. An embodiment of the method is accomplished using a 20 to 300 sccm of chlorine and 2 to 200 sccm of carbon monoxide, regulated to a total chamber pressure of 2-100 mTorr to etch a hafnium oxide layer.

Abstract: The invention provides a method for making thin film metal oxide actuator device. According to the method a first conductive layer is deposited on a silicon substrate. Next a thin film metal oxide layer is deposited on the first conductive layer. A negative photoresist material is applied to the metal oxide layer to provide a photoresist layer. The photoresist layer is patterned using light radiation energy and developed to provide one or more exposed portions of the metal oxide layer. The photoresist layer is etched with a reactive ion plasma sufficient to remove the photoresist layer and the metal oxide layer under the photoresist layer from the first conductive layer leaving the one or more exposed portions of metal oxide layer on the first conductive layer. A second conductive layer is attached to the metal oxide layer to provide a thin film metal oxide actuator device.

Abstract: A method in which etching or ashing is conducted by providing satisfactory kinetic energy of reaction seeds such as ions or radicals without damaging a substrate, and an apparatus used in this method are provided. A predetermined film of for example polycrystalline silicon on the substrate is etched in vapor phase using reaction seeds or precursors thereof generated by contacting a reaction gas such as CF4 with a heated catalyst of for example tungsten.

Abstract: A horizontal surrounding gate MOSFET comprises a monolithic structure formed in an upper silicon layer of a semiconductor substrate which is essentially a silicon-on-insulator (SOI) wafer, the monolithic structure comprising a source and drain portion oppositely disposed on either end of a cylindrical channel region longitudinally disposed between the source and drain. The channel is covered with a gate dielectric and an annular gate electrode is formed circumferentially covering the channel.

Abstract: A method of making a ferroelectric memory transistor includes preparing a silicon substrate including forming plural active areas thereon; depositing a layer of gate insulator on the substrate, and depositing a layer of polysilicon over the gate insulator layer; forming a source region, a drain region and a gate electrode; depositing a layer of bottom electrode material and finishing the bottom electrode without damaging the underlying gate insulator and silicon substrate; depositing a layer of ferroelectric material on the bottom electrode; depositing a layer of top electrode material on the ferroelectric material; and finishing the transistor, including passivation oxide deposition, contact hole etching and metalization.

Abstract: Methods of forming copper interconnects free from via-to-via leakage currents and having low resistances are disclosed. In a first aspect, a barrier layer is deposited on the first metal layer prior to copper oxide sputter-etching to prevent copper atoms from reaching the interlayer dielectric and forming via-to-via leakage current paths therein. In a second aspect, a capping dielectric barrier layer is deposited over the first metal layer prior to sputter etching. During sputter-etching, the capping dielectric barrier layer redistributes on the sidewalls of the interlayer dielectric, preventing sputter-etched copper atoms from reaching the interlayer dielectric and forming via-to-via leakage paths therein. In a third aspect, both a capping dielectric barrier layer and a barrier layer are deposited over the first metal layer prior to sputter-etching to prevent copper atoms produced during sputter-etching from reaching the interlayer dielectric and forming via-to-via leakage paths therein.

Abstract: A method of etching a multi-layer film, wherein the multi-layer film comprises at least one conductive layer and a ferroelectric layer formed sequentially on a substrate comprises forming a hard mask on at least one of the at least one conductive layers. The hard mask is used to etch the first conductive layer and the ferroelectric layer at a temperature that may exceed 100 degrees. A semiconductor device comprises first electrodes formed on a substrate, ferroelectric portions formed on the first electrodes, second electrodes formed on the ferroelectric portions, and hard masks formed on the second electrode.

Abstract: A method for removing sacrificial materials and metal contamination from silicon surfaces during the manufacturing of an integrated micromechanical device and a microelectronic device on a single chip is provided which includes the steps of adjusting the temperature of the chip using a reaction chamber to a temperature appropriate for the selection of a beta-diketone and the design of micromechanical and microelectronic devices, cycle purging the chamber using an inert gas to remove atmospheric gases and trace amounts of water, introducing HF and the beta-diketone as a reactive mixture into the reaction chamber which contains at least one substrate to be etched, flowing the reactive mixture over the substrate until the sacrificial materials and metal contamination have been substantially removed, stopping the flow of the reactive mixture; and cycle purging the chamber to remove residual reactive mixture and any remaining reaction by-products.

Abstract: The present disclosure pertains to a method of plasma etching a titanium nitride layer within a semiconductor structure. In many embodiments of the method, the titanium nitride layer is etched using a source gas comprising chlorine and a fluorocarbon. Also disclosed herein is a two-step method of plasma etching a titanium nitride gate consisting of a main etch step, followed by an overetch step which utilizes a source gas comprising chlorine and a bromine-containing compound, to etch a portion of the titanium nitride layer which was not etched in the main etch step. The chlorine/bromine overetch chemistry can be used in conjunction with a chlorine/fluorocarbon main etch chemistry, or with any other titanium nitride etch chemistry known in the art.

Abstract: A metal oxide, utilized as a gate dielectric, is removed using a combination of gaseous HCl (HCl), heat, and an absence of rf. The metal oxide, which is preferably hafnium oxide, is effectively removed in the areas not under the gate electrode. The use of HCl results in the interfacial oxide that underlies the metal oxide not being removed. The interfacial is removed to eliminate the metal and is replaced by another interfacial oxide layer. The subsequent implant steps are thus through just an interfacial oxide and not through a metal oxide. Thus, the problems associated with implanting through a metal oxide are avoided.

Abstract: The processes allow structuring of a metal-containing layer. The metal-containing layer is etched, using an etching mask, in a plasma-assisted etching gas atmosphere at a temperature of over 130° C. and in the presence of at least one halogen compound and at least one oxidizing agent. The concentration of the oxidizing agent is thereby set higher than the concentration of the halogen compound.

Abstract: The present invention provides a method of manufacturing a semiconductor device. The method includes depositing a metal oxide containing a dopant and having a high dielectric constant on a substrate; wherein the metal is aluminum or silicon and the dopant is zirconium or hafnium and etching the doped metal oxide with a plasma containing a halogenated compound.