Abstract: A method of promoting adhesion between a dielectric layer of a semiconductor device and a metal fill deposited within a trench in the dielectric layer, including performing an ion implantation process wherein an ion beam formed of an ionized dopant species is directed into the trench at an acute angle relative to a top surface of the dielectric layer to form an implantation layer in a sidewall of the trench, and depositing a metal fill in the trench atop an underlying bottom metal layer, wherein the metal fill adheres to the sidewall.

Abstract: Embodiments of the present disclosure provide a method for forming a hole structure in a semiconductor device. The method includes forming a first etch mask over a stack structure, and removing a portion of the stack structure exposed by the first etch mask. The first etch mask may have a first mask opening with a first lateral dimension. The method may also include forming a second etch mask from the first etch mask. The second etch mask may have a second mask opening with a second lateral dimension that is greater than the first lateral dimension. The method may further include removing another portion of the stack structure exposed by the second etch mask to form the hole structure having a first hole portion and a second hole portion connected to and over the first hole portion.

Abstract: A device includes three elements fabricated on a common substrate. The first element includes an active waveguide structure having at least three sub-layers supporting a first optical mode. The second element has a passive waveguide structure supporting a second optical mode, and the third element, butt-coupled to the first element, has an intermediate waveguide structure supporting intermediate optical modes. One sub-layer in the active waveguide structure includes an n-contact layer, another sub-layer includes a p-contact layer, and a third sub-layer includes an active region. A tapered waveguide structure in at least one of the second and third elements facilitates efficient adiabatic transformation between the second optical mode and an intermediate optical mode. No adiabatic transformation occurs between that intermediate optical mode and the first optical mode.

Abstract: A substrate processing method includes preparing a substrate including an etching target film and a mask; etching the etching target film through the mask by plasma; and heat-treating the substrate at a preset temperature after the etching of the etching target film.

Abstract: In an embodiment, a method of forming a semiconductor device includes forming a fin protruding above a substrate; forming a gate structure over the fin; forming a recess in the fin and adjacent to the gate structure; performing a wet etch process to clean the recess; treating the recess with a plasma process; and performing a dry etch process to clean the recess after the plasma process and the wet etch process.

Abstract: The present disclosure relates to an integrated chip. The integrated chip comprises a dielectric layer over a substrate. A first metal feature is over the dielectric layer. A second metal feature is over the dielectric layer and is laterally adjacent to the first metal feature. A first dielectric liner segment extends laterally between the first metal feature and the second metal feature along an upper surface of the dielectric layer. The first dielectric liner segment extends continuously from along the upper surface of the dielectric layer, to along a sidewall of the first metal feature that faces the second metal feature, and to along a sidewall of the second metal feature that faces the first metal feature. A first cavity is laterally between sidewalls of the first dielectric liner segment and is above an upper surface of the first dielectric liner segment.

Abstract: Exemplary methods for removing nitride may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. The methods may further include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor and flowing the plasma effluents into a processing region of the semiconductor processing chamber housing a substrate. The substrate may include a high-aspect-ratio feature. The substrate may further include a region of exposed nitride and a region of exposed oxide. The methods may further include providing a hydrogen-containing precursor to the processing region to produce an etchant. At least a portion of the exposed nitride may be removed with the etchant.

Abstract: Methods for pre-cleaning substrates having metal and dielectric surfaces are described. The substrate is exposed to a strong reductant to remove contaminants from the metal surface and damage the dielectric surface. The substrate is then exposed to an oxidation process to repair the damage to the dielectric surface and oxidize the metal surface. The substrate is then exposed to a weak reductant to reduce the metal oxide to a pure metal surface without substantially affecting the dielectric surface. Processing tools and computer readable media for practicing the method are also described.

Abstract: Improved process flows and methods are provided that use a cyclic dry process to transfer a pattern from a patterned organic layer to an underlying silicon-containing layer. The cyclic dry process disclosed herein includes a deposition step, an etch step and a purge step, which may be repeated a number of cycles to progressively etch the exposed portions of the silicon-containing layer. Unlike conventional pattern transfer processes, the cyclic dry process described herein anisotropically etches the silicon-containing layer with high selectivity to the patterned organic layer. In doing so, the disclosed process improves pattern transfer performance and avoids problems typically seen in conventional pattern transfer processes such as, e.g., CD enlargement, CD distortion and/or complete loss of photoresist.

Abstract: A semiconductor device includes a coaxial contact that has conductive layers extending from local interconnects and being coupled to metal layers. The local interconnects are stacked over a substrate and extend laterally along a top surface of the substrate. The metal layers are stacked over the local interconnects and extend laterally along the top surface of the substrate. The conductive layers are close-shaped and concentrically arranged, where each of the local interconnects is coupled to a corresponding conductive layer, and each of the conductive layers is coupled to a corresponding metal layer. The semiconductor device also includes insulating layers that are close-shaped, concentrically arranged, and positioned alternately with respect to the conductive layers so that the conductive layers are spaced apart from one another by the insulating layers.

Abstract: Processing methods may be performed to form semiconductor structures that may include three-dimensional memory structures. The methods may include forming a plasma of a fluorine-containing precursor in a remote plasma region of a processing chamber. The methods may include contacting a semiconductor substrate with effluents of the plasma. The semiconductor substrate may be housed in a processing region of the processing chamber. The methods may include selectively cleaning exposed nitride materials with the effluents of the plasma. The methods may also include subsequently depositing a cap material over the cleaned nitride material. The cap material may be selectively deposited on the nitride material relative to exposed regions of a dielectric material.

Abstract: Generally, examples are provided relating to conductive features that include a barrier layer, and to methods thereof. In an embodiment, a metal layer is deposited in an opening through a dielectric layer(s) to a source/drain region. The metal layer is along the source/drain region and along a sidewall of the dielectric layer(s) that at least partially defines the opening. The metal layer is nitrided, which includes performing a multiple plasma process that includes at least one directional-dependent plasma process. A portion of the metal layer remains un-nitrided by the multiple plasma process. A silicide region is formed, which includes reacting the un-nitrided portion of the metal layer with a portion of the source/drain region. A conductive material is disposed in the opening on the nitrided portions of the metal layer.

Abstract: Methods for minimizing sidewall damage during low k etch processes are disclosed. The methods etch the low k layers f using the plasma activated vapor of an organofluorine compound having a formula selected from the group consisting of N?C—R; (N@C—)—(R)—(—C?N); Rx[-C?N(Rz)]y; and R(3-a)-N—Ha, wherein a=1-2, x=1-2, y=1-2, z=0-1, x+z=1-3, and each R independently has the formula HaFbCc with a=0-11, b=0-11, and c=0-5.

Abstract: Methods and systems for cyclic etching of a patterned layer are described. In an embodiment, a method includes receiving a substrate comprising an underlying layer, a mask layer that exposes portions of an intermediate layer that is disposed between the underlying layer and the mask layer. An embodiment may also include forming a first layer on the mask layer and a second layer on the exposed portions of the intermediate layer, the first layer and the second layer being concurrently formed. Additionally, the method may include removing, concurrently, the first layer and the second layer from the substrate. In such embodiments, the method may include alternating between the forming and the removing until portions of the underlying layer are exposed.

Abstract: An embodiment includes first, second, and third metal layers; first, second, and third metal lines included in the second metal layer; a layer including airgaps, the first metal layer being between the layer including airgaps and the second metal layer; a first void between the first and second metal lines and a second void between the second and third metal lines; a conformal layer between the first and second metal lines; an additional layer between the first and second metal layers; wherein the first void includes air and the second void includes air; wherein a first axis intersects the first, second, and third metal lines and the first and second voids; wherein a second axis, orthogonal to the first axis, intersects the conformal layer and the additional layer; wherein a third axis, orthogonal to the first axis, intersects the second metal line and the additional layer.

Abstract: In an embodiment, a method of processing a substrate includes introducing a first process gas or a mixture of the first process gas and a second process gas into an etch chamber; exposing the substrate to the first process gas or to the mixture of the first and second process gases, the substrate having halogen residue formed on an exposed surface, the substrate having high aspect ratio features; forming and maintaining a plasma of the first process gas or a plasma of the mixture of the first and second process gases in the etch chamber to remove the residue from the surface by applying a first source power; exposing the substrate to the second process gas; and forming and maintaining a plasma of the second process gas in the etch chamber to remove the residue from the surface by applying a second source power and a bias power.

Abstract: An etching method is provided for selectively etching a first region of silicon oxide with respect to a second region of silicon nitride by performing plasma processing on a target object including the first region and the second region. In the etch method, first, a plasma of a processing gas including a fluorocarbon gas is generated in a processing chamber where the target object is accommodated. Next, the plasma of the processing gas including the fluorocarbon gas is further generated in the processing chamber where the target object is accommodated. Next, the first region is etched by radicals of fluorocarbon contained in a deposit which is formed on the target object by the generation and the further generation of the plasma of the processing gas containing the fluorocarbon gas. A high frequency powers used for the plasma generation is smaller than a high frequency power used for plasma further generation.

Abstract: A semiconductor device includes a first insulating interlayer on a substrate, metal lines in the first insulating interlayer, a first air gap between the metal lines in a first region of the substrate and a second air gap between the first insulating interlayer and at least one of the metal lines in a second region of the substrate, a liner layer covering top surfaces and side walls of the metal lines and a top surface and a side wall of the first insulating interlayer, adjacent to the first and second air gaps, and a second insulating interlayer on the liner layer and contacting the liner layer.

Abstract: Methods for structuring objects with a particle beam apparatus are disclosed.

Abstract: Exemplary cleaning or etching methods may include flowing a fluorine-containing precursor into a remote plasma region of a semiconductor processing chamber. Methods may include forming a plasma within the remote plasma region to generate plasma effluents of the fluorine-containing precursor. The methods may also include flowing the plasma effluents into a processing region of the semiconductor processing chamber. A substrate may be positioned within the processing region, and the substrate may include a region of exposed oxide. Methods may also include providing a hydrogen-containing precursor to the processing region. The methods may further include removing at least a portion of the exposed oxide while maintaining a relative humidity within the processing region below about 50%. Subsequent to the removal, the methods may include increasing the relative humidity within the processing region to greater than or about 50%. The methods may further include removing an additional amount of the exposed oxide.

Abstract: A method of making multi-level contacts includes providing an in-process multilevel device having a device region and a contact region including a stack of alternating sacrificial layers and insulating layers located over a major surface of a substrate. A contact mask having contact mask openings is provided over the stack, and a first over mask having first over mask openings is provided over the contact mask. A subset of the contact mask openings is substantially aligned with the first over mask openings. Contact openings are formed through the stack, wherein each of the contact openings extends substantially perpendicular to the major surface of the substrate to a respective one of the sacrificial layers. A plurality of electrically conductive via contacts is formed in the plurality of the contact openings.

Abstract: Some embodiments include methods for depositing copper-containing material utilizing physical vapor deposition of the copper-containing material while keeping a temperature of the deposited copper-containing material at greater than 100° C. Some embodiments include methods in which openings are lined with a metal-containing composition, copper-containing material is physical vapor deposited over the metal-containing composition while a temperature of the copper-containing material is no greater than about 0° C., and the copper-containing material is then annealed while the copper-containing material is at a temperature in a range of from about 180° C. to about 250° C. Some embodiments include methods in which openings are lined with a composition containing metal and nitrogen, and the lined openings are at least partially filled with copper-containing material.

Abstract: An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a first metal line and a second metal line over a substrate; a portion of a first low-k (LK) dielectric layer between the first metal line and the second metal line; and a second LK dielectric layer over the portion of the first LK dielectric layer. A top surface of the second LK dielectric layer is substantially coplanar with a top surface of the first metal line or the second metal line, and a thickness of the second LK dielectric layer is less than a thickness of the first metal line or a thickness of the second metal line.

Abstract: A method of fabricating a field-effect transistor is disclosed. In one aspect, the method includes forming a channel layer comprising germanium over a substrate. The method additionally includes forming a gate structure on the channel layer, where the gate structure comprises a gate layer comprising silicon, and the gate layer has sidewalls above a surface of the channel layer. The method additionally includes forming sidewall spacers comprising silicon dioxide on the sidewalls by subjecting the gate structure to a solution adapted for forming a chemical silicon oxide on materials comprising silicon. The method further includes forming elevated source/drain structures on the channel layer adjacent to the gate structure by selectively epitaxially growing a source/drain material on the channel layer.

Abstract: Some embodiments include methods of forming memory. A series of photoresist features may be formed over a gate stack, and a placeholder may be formed at an end of said series. The placeholder may be spaced from the end of said series by a gap. A layer may be formed over and between the photoresist features, over the placeholder, and within said gap. The layer may be anisotropically etched into a plurality of first vertical structures along edges of the photoresist features, and into a second vertical structure along an edge of the placeholder. A mask may be formed over the second vertical structure. Subsequently, the first vertical structures may be used to pattern string gates while the mask is used to pattern a select gate. Some embodiments include methods of forming conductive runners, and some embodiments may include semiconductor constructions.

Abstract: A method for stripping an organic mask above a porous low-k dielectric film is provided. A steady state flow of a stripping gas, comprising CO2 and CH4 is provided. The stripping gas is formed into a plasma, wherein the plasma strips at least half the organic mask and protects the porous low-k dielectric film, for a duration of providing the steady state flow of the stripping gas.

Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.

Abstract: Methods for surface interface engineering in semiconductor fabrication are provided herein. In some embodiments, a method of processing a substrate disposed atop a substrate support in a processing volume of a processing chamber includes: generating an ion species from an inductively coupled plasma formed within the processing volume of the processing chamber from a first process gas; exposing a first layer of the substrate to the ion species to form an ammonium fluoride (NH4F) film atop the first layer, wherein the first layer comprises silicon oxide; and heating the substrate to a second temperature at which the ammonium fluoride film reacts with the first layer to selectively etch the silicon oxide.

Abstract: Embodiments of methods for forming features in a silicon containing layer of a substrate disposed on a substrate support are provided herein. In some embodiments, a method for forming features in a silicon containing layer of a substrate disposed on a substrate support in a processing volume of a process chamber includes: exposing the substrate to a first plasma formed from a first process gas while providing a bias power to the substrate support, wherein the first process gas comprises one or more of a chlorine-containing gas or a bromine containing gas; and exposing the substrate to a second plasma formed from a second process gas while no bias power is provided to the substrate support, wherein the second process gas comprises one or more of an oxygen-containing gas or nitrogen gas, and wherein a source power provided to form the first plasma and the second plasma is continuously provided.

Abstract: A structure includes a silicon layer disposed on a buried oxide layer that is disposed on a substrate; at least one transistor device formed on or in the silicon layer, the at least one transistor having metallization; a released region of the silicon layer disposed over a cavity in the buried oxide layer; a back end of line (BEOL) dielectric film stack overlying the silicon layer and the at least one transistor device; a nitride layer overlying the BEOL dielectric film stack; a hard mask formed as a layer of hafnium oxide overlying the nitride layer; and an opening made through the layer of hafnium oxide, the layer of nitride and the BEOL dielectric film stack to expose the released region of the silicon layer disposed over the cavity in the buried oxide layer. The hard mask protects the underlying material during a MEMS/NEMS HF vapor release procedure.

Abstract: A method for manufacturing a liquid discharge includes a process of forming a plurality of blind holes extending from a first surface of the silicon substrate toward a second surface which is a surface opposite to the first surface in the silicon substrate and a process of subjecting the silicon substrate in which the plurality of blind holes are formed to anisotropic etching from the first surface to form a liquid supply port in the silicon substrate, in which, in the process of forming the liquid supply port, the silicon in a region sandwiched by the plurality of blind holes when the silicon substrate is seen from the second surface side is left without being removed by the anisotropic etching to use the left silicon as a beam.

Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.

Abstract: A plasma processing method includes a surface improving step of improving a surface of the photoresist film by performing plasma processing using a hydrogen-containing gas as a processing gas and an etching step of etching the SiON film by performing plasma processing using a processing gas including a gas containing a CHF-based gas and a chlorine-containing gas while using as a mask the photoresist film having the improved surface.

Abstract: During formation of a charge trap separation in a semiconductor device, a polymer deposition is formed in a reactor using a first chemistry. In a following step, a second chemistry can be used to etch the polymer deposition in the reactor. The same or similar second chemistry can be used in a second etching step to expose a first oxide layer in each of the cells of the semiconductor device and to form a flat upper surface. This additional etch step can also be performed by the reactor, thereby reducing the number of machines required in the formation process.

Abstract: Provided is a method of selectively removing a first region from a workpiece which includes the first region formed of silicon oxide and a second region formed of silicon. The method performs a plurality of sequences. Each sequence includes: forming a denatured region by generating plasma of a processing gas that contains hydrogen, nitrogen, and fluorine within a processing container that accommodates the workpiece so as to denature a portion of the first region, and removing the denatured region within the processing container. In addition, a sequence subsequent to a predetermined number of sequences after a first sequence among the plurality of sequences further includes exposing the workpiece to plasma of a reducing gas which is generated within the processing container, prior to the forming of the denatured region.

Abstract: A deposit removing method includes an exposing process of heating and exposing a substrate to oxygen plasma; and a cycle process in which the substrate is exposed to an atmosphere of a mixture gas of a hydrogen fluoride gas and an alcohol gas, and a first period during which a total pressure of the mixture gas or a partial pressure of the alcohol gas is set to be a first total pressure or a first partial pressure and a second period during which the total pressure or the partial pressure is set to be a second total pressure lower than the first total pressure or a second partial pressure lower than the first partial pressure are repeated multiple cycles. A supply amount of the mixture gas from a first region including a central portion of the substrate is larger than that from a second region outside the first region.

Abstract: A method for removing oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A removing oxide process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A direction change of space formed in an etching target layer can be suppressed while maintaining an etching selectivity for the etching target layer against a mask. A semiconductor device manufacturing method MT includes exciting a first gas by supplying the first gas containing a fluorocarbon gas, a fluorohydrocarbon gas and an oxygen gas into a processing chamber 12 (ST2); and exciting a second gas by supplying the second gas containing an oxygen gas and a rare gas into the processing chamber (ST3), and a cycle including the exciting of the first gas (ST2) and the exciting of the second gas (ST3) is repeated multiple times.

Abstract: A method for mitigating line-edge roughness on a semiconductor device. The method includes line-edge roughness mitigation techniques in accordance with embodiments of the present invention.

Abstract: Embodiments of the invention include a method of cleaning a semiconductor substrate of a device structure and a method of forming a silicide layer on a semiconductor substrate of a device structure. Embodiments include steps of converting a top portion of the substrate into an oxide layer and removing the oxide layer to expose a contaminant-free surface of the substrate.

Abstract: Oxides (e.g., native or thermal silicon oxide) are etched from underlying silicon with a mixture of fluorine and oxygen radicals generated by a remote plasma. The oxygen radicals rapidly oxidize any uncovered bare silicon areas, preventing the pitting that can result from fluorine etching bare silicon more rapidly than it etches the surrounding oxide. A very thin (few ?), highly uniform passivation layer remaining on the silicon after the process may be left in place or removed. An oxygen-impermeable layer may be formed in-situ immediately afterward to prevent further oxidation. A pre-treatment with oxygen radicals alone fills pores and gaps in the oxide before etching begins.

Abstract: An exemplary embodiment provides a method which etches a second layer in a base body to be processed having a first layer containing Ni and Si and a second layer containing Si and N which are exposed to a surface thereof. The method according to the exemplary embodiment includes (a) preparing a base body to be processed in a processing chamber, and (b) supplying a first processing gas which contains carbon and fluorine but does not contain oxygen into the processing chamber and generating plasma in the processing chamber.

Abstract: Etching of a thin film stack including a lower thin film layer containing an advanced memory material is carried out in an inductively coupled plasma reactor having a dielectric RF window without exposing the lower thin film layer, and then the etch process is completed in a toroidal source plasma reactor.

Abstract: The molecular etcher carbonyl fluoride (COF2) or any of its variants, are provided for, according to the present invention, to increase the efficiency of etching and/or cleaning and/or removal of materials such as the unwanted film and/or deposits on the chamber walls and other components in a process chamber or substrate (collectively referred to herein as “materials”). The methods of the present invention involve igniting and sustaining a plasma, whether it is a remote or in-situ plasma, by stepwise addition of additives, such as but not limited to, a saturated, unsaturated or partially unsaturated perfluorocarbon compound (PFC) having the general formula (CyFz) and/or an oxide of carbon (COx) to a nitrogen trifluoride (NF3) plasma into a chemical deposition chamber (CVD) chamber, thereby generating COF2. The NF3 may be excited in a plasma inside the CVD chamber or in a remote plasma region upstream from the CVD chamber.

Abstract: A manufacturing method of a semiconductor manufacturing apparatus is provided for etching a multilayer film having a first film and a second film with differing dielectric constants alternatingly stacked on a substrate, and forming a hole with a predetermined shape in the multilayer film. The manufacturing method includes a first step of etching the multilayer film to a first depth using a gas mixture containing a CF based gas at a first flow rate and a bromine-containing gas, a chloride-containing gas, and/or an iodine-containing gas; a second step of etching the multilayer film to a second depth after the first step using a gas mixture containing the CF based gas at a second flow rate and the bromine-containing gas, the chloride-containing gas, and/or the iodine-containing gas; and a third step for over etching the multilayer film after the second step until the hole reaches a base layer.

Abstract: A method of taper-etching a layer to be etched that is made of a dielectric material and has a top surface. The method includes the steps of: forming an etching mask with an opening on the top surface of the layer to be etched; and taper-etching a portion of the layer to be etched, the portion being exposed from the opening, by reactive ion etching so that a groove having two wall faces intersecting at a predetermined angle is formed in the layer to be etched. The step of taper-etching employs an etching gas containing a first gas contributing to the etching of the layer to be etched and a second gas contributing to the deposition of a sidewall protective film, and changes, during the step, the ratio of the flow rate of the second gas to the flow rate of the first gas so that the ratio increases.

Abstract: A method includes the stage of partially removing a first insulator layer to form an opening passing through the first insulator layer by plasma etching using a gas of a first type, and the stage of partially removing a second insulator layer to form an opening passing through the second insulator layer by plasma etching using a gas of a second type. The gas of a first type contains a first component capable of etching the first insulator layer, and a gas of the second type contains a second component different from the first component, capable of etching the second insulator layer and a third component having a higher deposition ability than the second component.

Abstract: A semiconductor device manufacturing method is provided that includes etching with a plasma a multilayer film including a first film and a second film with differing dielectric constants alternately stacked on a substrate using a photoresist layer arranged on the multilayer film as a mask, and forming the multilayer film into a stepped configuration. The semiconductor device manufacturing method includes repetitively performing a first step of etching the first film using the photoresist layer as the mask; a second step of adjusting a pressure within a processing chamber to 6-30 Torr, generating the plasma by applying a first high frequency power for biasing and a second high frequency power for plasma generation to the lower electrode, and etching the photoresist layer using the generated plasma; and a third step of etching the second film using the photoresist layer and the first film as the mask.

Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.