Abstract: A method for etching features in a plurality of silicon based bilayers forming a stack on a wafer in a plasma processing chamber is provided. A main etch gas is flowed into the plasma processing chamber. The main etch gas is formed into a plasma, while providing a first pressure. A wafer temperature of less than 20° C. is maintained. The pressure is ramped to a second pressure less than the first pressure as the plasma etches through a plurality of the plurality of silicon based bilayers. The flow of the main etch gas is stopped after a first plurality of the plurality of bilayers is etched.

Abstract: The present invention provides a dry etching method capable of readily providing rounded top edge portions, called top rounds, at trenches and vias formed by removal of a dummy material. The method of the present invention is a dry etching method for forming trenches or vias by removing a dummy material with its periphery surrounded by an interlayer oxide film, which method includes the steps of etching the dummy material to a predetermined depth, performing isotropic etching after the dummy material etching, and removing remaining part of the dummy material after the isotropic etching.

Abstract: An RFID based thermal bubble type accelerometer includes a flexible substrate, an embedded system on chip (SOC) unit, an RFID antenna formed on the substrate and coupled to a modulation/demodulation module in the SOC unit, a cavity formed on the flexible substrate, and a plurality of sensing assemblies, including a heater and two temperature-sensing elements, disposed along the x-axis direction and suspended over the cavity. The two temperature-sensing elements, serially connected, are separately disposed at two opposite sides and at substantially equal distances from the heater. Two sets of sensing assemblies can be connected in differential Wheatstone bridge. The series-connecting points of the sensing assemblies are coupled to the SOC unit such that an x-axis acceleration can be obtained by a voltage difference between the connecting points. The x-axis acceleration can be sent by the RFID antenna to a reader after it is is modulated and encoded by the modulation/demodulation module.

Abstract: A method for manufacturing a thin film transistor array panel, including: sequentially forming a first silicon layer, a second silicon layer, a lower metal layer, and an upper metal layer on a gate insulating layer and a gate line; forming a first film pattern on the upper metal layer; forming a first lower metal pattern and a first upper metal pattern that includes a protrusion, by etching the upper metal layer and the lower metal layer; forming first and second silicon patterns by etching the first and second silicon layers; forming a second film pattern by ashing the first film pattern; forming a second upper metal pattern by etching the first upper metal pattern; forming a data line and a thin film transistor by etching the first lower metal pattern and the first and second silicon patterns; and forming a passivation layer and a pixel electrode on the resultant.

Abstract: A method for semiconductor processing is provided wherein a workpiece having an underlying body and a plurality of features extending therefrom, is provided. A first set of the plurality of features extend from the underlying body to a first plane, and a second set of the plurality features extend from the underlying body to a second plane. A protection layer overlies each of the plurality of features and an isolation layer overlies the underlying body and protection layer, wherein the isolation has a non-uniform first oxide density associated therewith. The isolation layer anisotropically etched based on a predetermined pattern, and then isotropically etched, wherein a second oxide density of the isolation layer is substantially uniform across the workpiece. The predetermined pattern is based, at least in part, on a desired oxide density, a location and extension of the plurality of features to the first and second planes.

Abstract: STI divot formation is minimized and STI field height mismatch between different regions is eliminated. A nitride cover layer (150) having a thickness less than 150 then a oxide cover layer (160) having a thickness less than 150 is deposited acting as implant buffer after pad oxide removal following the STI CMP process. This nitride or oxide stack is selectively removed by masking prior to gate oxidation of each LV (low voltage) region (GX1), MV (intermediate voltage) region (GX3) and HV (high voltage) region (GX5) respectively followed by a gate poly deposition.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The hardmask is removed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: According to one embodiment, a semiconductor device manufacturing method includes collectively etching layers of a multilayered film including silicon layers and silicon oxide films alternately stacked on a semiconductor substrate. The etching gas of the etching contains at least two types of group-VII elements and one of a group-III element, a group-IV element, a group-V element, and a group-VI element, the energy of ions entering the semiconductor substrate when performing the etching is not less than 100 eV, and an addition ratio of the group-III element, the group-IV element, the group-V element, the group-VI element, and the group-VII element to the group-VII element is 0.5 (inclusive) to 3.0 (inclusive).

Abstract: Etching equipment and methods are disclosed herein for more efficient etching of sacrificial material from between permanent MEMS structures. An etching head includes an elongate etchant inlet structure, which may be slot-shaped or an elongate distribution of inlet holes. A substrate is supported in proximity to the etching head in a manner that defines a flow path substantially parallel to the substrate face, and permits relative motion for the etching head to scan across the substrate.

Abstract: A plasma etching method includes plasma-etching a silicon oxide layer through a mask using a process gas, the process gas containing oxygen gas and a fluorohydrocarbon shown by the formula (1), CxHyFz, wherein x is an integer from 4 to 6, y is an integer from 1 to 4, and z is a positive integer, provided that (y+z) is 2x or less. A contact hole having a very small diameter and a high aspect ratio can be formed in a substantially vertical shape without necking by plasma-etching the silicon oxide layer using a single process gas.

Abstract: In sophisticated semiconductor devices, the contact elements connecting to active semiconductor regions having formed thereabove closely spaced gate electrode structures may be provided on the basis of a liner material so as to reduce the lateral width of the contact opening, while, on the other hand, non-critical contact elements may be formed on the basis of non-reduced lateral dimensions. To this end, at least a first portion of the critical contact element is formed and provided with a liner material prior to forming the non-critical contact element.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.

Abstract: A method of etching silicon-containing material is described and includes a SiConi™ etch having a greater or lesser flow ratio of hydrogen compared to fluorine than that found in the prior art. Modifying the flow rate ratios in this way has been found to reduce roughness of the post-etch surface and to reduce the difference in etch-rate between densely and sparsely patterned areas. Alternative means of reducing post-etch surface roughness include pulsing the flows of the precursors and/or the plasma power, maintaining a relatively high substrate temperature and performing the SiConi™ in multiple steps. Each of these approaches, either alone or in combination, serve to reduce the roughness of the etched surface by limiting solid residue grain size.

Abstract: A method for etching a dielectric layer is provided. The dielectric layer is disposed over a substrate and below a patterned mask having a line-space pattern. The method includes (a) providing an etchant gas comprising CF4, COS, and an oxygen containing gas, (b) forming a plasma from the etchant gas, and (c) etching the dielectric layer into the line-space pattern through the mask with the plasma from the etchant gas. The gas flow rate of CF4 may have a ratio greater than 50% of a total gas flow rate of all reactive gas components. The gas flow rate of COS may be between 1% and 50%. The method reduces bowing in etching of the dielectric layer by adding COS to the etchant gas.

Abstract: An apparatus for use with a digital micromirror device includes a hinge layer that is disposed outwardly from a substrate. The hinge layer including a hinge that is capable of at least partially supporting a micromirror that is disposed outwardly from the hinge. In one particular embodiment, the hinge and the substrate are separated by a first air gap. The device also including a first hinge support that is disposed outwardly from the substrate and inwardly from at least a portion of the hinge layer. The first hinge support being capable of transmitting a voltage to the hinge. At least a portion of the hinge support coupled to at least the portion of the hinge layer. In one particular embodiment, the first hinge support is formed in a process step that is different than a process step that forms the hinge layer.

Abstract: A method includes making a target feature of an integrated circuit by providing a main layer over a substrate, depositing a first mask layer over the main layer, patterning the first mask layer, forming sidewall spacers with a width (w) in adjoining sidewalls of the patterned first mask layer and exposing a top area of the patterned first mask layer, selectively removing the first mask layer and exposing a portion of the main layer between the sidewall spacers, depositing a second mask layer over the main layer between the sidewall spacers, selectively removing the sidewall spacers to form an opening and exposing another portion of the main layer in the opening, etching the main layer through the opening to form the target feature.

Abstract: A toughening agent composition for increasing the hydrophobicity of an organosilicate glass dielectric film when applied to said film. It includes a component capable of alkylating or arylating silanol moieties of the organosilicate glass dielectric film via silylation, and an activating agent selected from the group consisting of an amine, an onium compound and an alkali metal hydroxide.

Abstract: A method for etching a line pattern in an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The method includes opening the ARC layer, in which an ARC opening gas comprising CF3I, a fluorocarbon (including hydrofluorocarbon) containing gas, and an oxygen containing gas are provided, a plasma is formed from the ARC opening gas to open the ARC layer, and providing the ARC opening gas is stopped. Line pattern features are etched into the etch layer through the opened ARC layer.

Abstract: A method etching features through a stack of a silicon nitride layer over a silicon layer over a silicon oxide layer in a plasma processing chamber is provided. The silicon nitride layer is etched in the plasma processing chamber, comprising; flowing a silicon nitride etch gas; forming the silicon nitride etch gas into a plasma to etch the silicon nitride layer, and stopping the flow of the silicon nitride etch gas. The silicon layer is, comprising flowing a silicon etch gas, wherein the silicon etch gas comprises SF6 or SiF4, forming the silicon etch gas into a, and stopping the flow of the silicon etch gas. The silicon oxide layer is etched in the plasma processing chamber, comprising flowing a silicon oxide etch gas, forming the silicon oxide etch gas into a plasma, and stopping the flow of the silicon oxide etch gas.

Abstract: A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film.

Abstract: Methods and apparatus for performing end point determination. A method includes receiving a wafer into an etch tool chamber for performing an RIE etch; beginning the RIE etch to form vias in the wafer; receiving in-situ measurements of one or more physical parameters of the etch tool chamber that are correlated to the RIE etch process; providing a virtual metrology model for the RIE etch in the chamber; inputting the received in-situ measurements to the virtual metrology model for the RIE etch in the chamber; executing the virtual metrology model to estimate the current via depth; comparing the estimated current via depth to a target depth; and when the comparing indicates the current via depth is within a predetermined threshold of the target depth; outputting a stop signal. An apparatus for use with the method embodiment is disclosed.

Abstract: A method is disclosed to fabricate an electro-mechanical device such as a MEMS or NEMS switch. The method includes providing a structure composed of a silicon layer disposed over an insulating layer that is disposed on a silicon substrate. The silicon layer is differentiated into a partially released region that will function as a portion of the electro-mechanical device. The method further includes forming a dielectric layer over the silicon layer; forming a hardmask over the dielectric layer, the hardmask being composed of hafnium oxide; opening a window to expose the partially released region; and fully releasing the partially released region using a dry etching process to remove the insulating layer disposed beneath the partially released region while using the hardmask to protect material covered by the hardmask. The step of fully releasing can be performed using a HF vapor.

Abstract: The etching method includes etching the silicon oxide film by supplying a halogen-containing gas and a basic gas to the substrate so that the silicon oxide film is chemically reacted with the halogen-containing gas and the basic gas to generate a condensation layer; etching silicon by supplying a silicon etching gas, which includes at least one selected from the group consisting of an F2 gas, an XeF2 gas, and a ClF3 gas, to the substrate; and after the etching of the silicon oxide film and the etching of the silicon, heating and removing the condensation layer from the substrate.

Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: There is provided a method for continual preparation of granular polycrystalline silicon using a fluidized bed reactor, enabling a stable, long-term operation of the reactor by effective removal of silicon deposit accumulated on the inner wall of the reactor tube. The method comprises (i) a silicon particle preparation step, wherein silicon deposition occurs on the surface of the silicon particles, while silicon deposit is accumulated on the inner wall of the reactor tube encompassing the reaction zone; (ii) a silicon particle partial discharging step, wherein a part of the silicon particles remaining inside the reactor tube is discharged out of the fluidized bed reactor so that the height of the bed of the silicon particles does not exceed the height of the reaction gas outlet; and (iii) a silicon deposit removal step, wherein the silicon deposit is removed by supplying an etching gas into the reaction zone.

Abstract: An etching method can prevent adverse effects of oxygen plasma from arising under an insulating film when etching the insulating film formed on a substrate. The etching method includes: a first etching step for exposing the insulating film to processing gas that has been turned into a plasma to etch the insulating film to a portion in the thickness direction; a deposition material removing step for exposing the insulating film remaining after completion of the first etching to oxygen plasma to remove deposition material deposited on the surface of the remaining insulating film; and a second etching of exposing the remaining insulating film to processing gas that has been turned into a plasma to etch the remaining insulating film.

Abstract: Provided is a method of setting a thickness of a dielectric, which restrains the dielectric formed in an electrode from being consumed when etching a silicon dioxide film on a substrate by using plasma. In a substrate processing apparatus including an upper electrode facing a susceptor and the dielectric formed of silicon dioxide in the upper electrode, a silicon dioxide film formed on a wafer being etched by using plasma, an electric potential of the plasma facing the dielectric in a case where the dielectric is not formed in the upper electrode is estimated based on a bias power applied to the susceptor and an A/C ratio in a chamber, and the thickness of the dielectric is determined so that an electric potential of the plasma, which is obtained by multiplying the estimated electric potential of the plasma by a capacity reduction coefficient calculated when a capacity of the dielectric and a capacity of a sheath generated around a surface of the dielectric are combined, is 100 eV or less.

Abstract: A plasma processing method performed in a plasma processing apparatus including a processing chamber accommodating a substrate in which a plasma is generated; a mounting table mounting the substrate, which is provided in the processing chamber and to which a plasma attraction high frequency voltage is applied; and a facing electrode provided to face the mounting table in the processing chamber, to which a negative DC voltage is applied, the method including: applying a plasma attraction high frequency voltage to the mounting table for a predetermined period of time; and stopping the application of the plasma attraction high frequency voltage to the mounting table. In the plasma processing method, the application of the plasma attraction high frequency voltage and stopping thereof are alternately repeated.

Abstract: Methods and devices for selective etching in a semiconductor process are shown. Chemical species generated in a reaction chamber provide both a selective etching function and concurrently form a protective coating on other regions. An electron beam provides activation to selective chemical species. In one example, reactive species are generated from a plasma source to provide an increased reactive species density. Addition of other gasses to the system can provide functions such as controlling a chemistry in a protective layer during a processing operation. In one example an electron beam array such as a carbon nanotube array is used to selectively expose a surface during a processing operation.

Abstract: A method for cleaning the surface of a silicon substrate, covered by a layer of silicon oxide includes: a) exposing the surface for 60 to 900 seconds to a radiofrequency plasma, generated from a fluorinated gas, to strip the silicon oxide layer and induce the adsorption of fluorinated elements on the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the fluorinated gas pressure being 10 mTorrs to 200 mTorrs, and the substrate temperature being lower than or equal to 300° C.; and b) exposing the surface including the fluorinated elements for 5 to 120 seconds to a hydrogen radiofrequency plasma, to remove the fluorinated elements from the substrate surface, the power density generated using the plasma being 10 mW/cm2 to 350 mW/cm2, the hydrogen pressure being 10 mTorrs to 1 Torr, and the substrate temperature being lower than or equal to 300° C.

Abstract: A plasma processing method for processing a target substrate uses a plasma processing apparatus which includes a vacuum evacuable processing vessel for accommodating the target substrate therein, a first electrode disposed in the processing vessel and connected to a first RF power supply for plasma generation and a second electrode disposed to face the first electrode. The method includes exciting a processing gas containing fluorocarbon in the processing vessel to generate a plasma while applying a negative DC voltage having an absolute value ranging from about 100 V to 1500 V or an RF power of a frequency lower than about 4 MHz to the second electrode. The target layer is etched by the plasma, thus forming recesses on the etching target layer based on the pattern of the resist layer.

Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a first block on a nanodot material, forming a first spacer on the first block, removing the first block to form a free standing spacer, removing exposed portions of the nanodot material and then the free standing spacer to form nanowires, forming a second block at an angle to a length of the nanowires, forming a second spacer on the second block, forming a second free standing spacer on the nanowires by removing the second block, and removing exposed portions of the nanowires and then the second free standing spacer to form an ordered array of nanodots.

Abstract: A substrate processing method processes a substrate including a processing target film, an organic film provided on the processing target film and having a plurality of line-shaped portions having fine width, and a hard film covering the line-shaped portions and the processing target film exposed between the line-shaped portions. The method includes a first etching step of etching a part of the hard film to expose the organic film and portions of the processing target film between the line-shaped portions; an ashing step of selectively removing the exposed organic film; and a second etching step of etching a part of the remaining hard film.

Abstract: A substrate processing method that can selectively remove deposit produced through dry etching of silicon. A substrate has a silicon base material and a hard mask that is made of a silicon nitride film and/or a silicon oxide film and formed on the silicon base material, the hard mask having an opening to which at least part of the silicon base material is exposed. A trench corresponding to the opening is formed in the silicon base material through dry etching using plasma produced from halogenated gas. After the dry etching, the substrate is heated to a temperature of not less than 200° C., and then hydrogen fluoride gas and helium gas are supplied toward the substrate.

Abstract: There is provided a plasma etching method capable of achieving a sufficient organic film modifying effect by high-velocity electrons. In forming a hole in an etching target film by plasma etching, a first condition of generating plasma within a processing chamber by way of turning on a plasma-generating high frequency power application unit and a second condition of not generating the plasma within the processing chamber by way of turning off the plasma-generating high frequency power application unit are repeated alternately. Further, a negative DC voltage is applied from a first DC power supply such that an absolute value of the applied negative DC voltage during a period of the second condition is greater than an absolute value of the applied negative DC voltage during a period of the first condition.

Abstract: A method of etching exposed silicon-and-nitrogen-containing material on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor and an oxygen-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents react with the exposed regions of silicon-and-nitrogen-containing material. The plasmas effluents react with the patterned heterogeneous structures to selectively remove silicon-and-nitrogen-containing material from the exposed silicon-and-nitrogen-containing material regions while very slowly removing other exposed materials. The silicon-and-nitrogen-containing material selectivity results partly from the presence of an ion suppression element positioned between the remote plasma and the substrate processing region. The ion suppression element reduces or substantially eliminates the number of ionically-charged species that reach the substrate.

Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.

Abstract: A plasma etching method, for plasma-etching a target substrate including at least a film to be etched, an organic film to become a mask of the to-be-etched film, and a Si-containing film which are stacked in order from bottom, includes the first organic film etching step, the treatment step and the second organic film etching step when the organic film is etched to form a mask pattern of the to-be-etched film. In the first organic film etching step, a portion of the organic film is etched. In the treatment step, the Si-containing film and the organic film are exposed to plasma of a rare gas after the first organic film etching step. In the second organic film etching step, the remaining portion of the organic film is etched after the treatment step.

Abstract: A method for forming a deep trench in a semiconductor device includes: forming a hard mask over a substrate, forming a hard mask pattern over the substrate through etching the hard mask to thereby expose an upper portion of the substrate, forming a first trench through a first etching the exposed substrate using a gas containing bromide and a gas containing chloride and forming a second trench through a second etching the first trench using of a gas containing sulfur and fluorine, wherein a depth of the second trench is deeper than a depth of the first trench.

Abstract: Plasma treatment apparatus and method for treatment of a surface of a substrate. A dielectric barrier discharge electrode structure is provided having a treatment space (5) and comprising a first electrode (2) and a second electrode (3), and a power supply (11) connected to the first electrode (2) and the second electrode (3) for generating an atmospheric pressure plasma in the treatment space (5). The plasma treatment apparatus further comprises a magnetic layer (6) provided on a surface of at least the first electrode (2). The first electrode (2) is arranged to receive, in operation, the substrate (1) to be treated and a mask device (7) in contact with the substrate (1), the mask device (7) interacting with the magnetic layer (6).

Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.

Abstract: A method of fabricating a semiconductor device according to one embodiment includes: forming a mask material on a semiconductor substrate comprising first and second regions; forming a pattern of a core on the mask material in the first region; forming a sidewall spacer mask on a side surfaces of the core pattern and subsequently removing the core pattern; transferring a pattern of the sidewall spacer mask to the mask material in the first region after removing the core; and thereafter, carrying out trimming of the pattern of the sidewall spacer mask which is transferred to the mask material in the first region, and formation of a predetermined pattern on the mask material in the second region, simultaneously.

Abstract: Formation of BPSG surface defects upon exposure to atmosphere is prevented by a plasma treatment method for converting boron and/or phosphorus materials separated from silicon near the surface of the doped glass layer to gas phase compounds. The treatment plasma is generated from a treatment process gas containing one of (a) a fluorine compound or (b) a hydrogen compound.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide -containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: A method for etching features in an etch layer is provided. An organic mask layer is etched, using a hard mask as an etch mask. The hard mask is removed, by selectively etching the hard mask with respect to the organic mask and etch layer. Features are etched in the etch layer, using the organic mask as an etch mask.

Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.

Abstract: Method for reducing resist poisoning. The method includes the steps of forming a first structure in a dielectric on a substrate, reducing amine related contaminants from the dielectric and the substrate prior to a formation of a second structure on the substrate such that the amine related contaminates will not diffuse out from either the substrate or the dielectric, wherein the reducing utilizes a plasma treatment which one of chemically ties up the amine related contaminates and binds, traps, or consumes the amine related contaminates during subsequent processing steps, forming the second structure on the substrate, and after the forming of the first structure, preventing poisoning of a resist layer in subsequent processing by the reducing.

Abstract: A method of manufacturing a tunable wavelength optical filter. The method includes steps of forming a first sacrificial oxide film for floating a lower mirror on a semiconductor substrate; sequentially laminating conductive silicon films and oxide films for defining a mirror region on the first sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form a lower mirror; sequentially laminating conductive silicon films and oxide films for defining the mirror region on a second sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form an upper mirror and forming an optical tuning space between the lower mirror and the upper mirror and etching the first sacrificial oxide film and the second sacrificial oxide film such that the lower mirror is floated on the semiconductor substrate.