Abstract: Methods for processing a substrate are described herein. Methods can include positioning a substrate comprising silicon in a processing chamber, delivering a plasma to the surface of the substrate while biasing the substrate, exposing the surface of the substrate to ammonium fluoride (NH4F), and annealing the substrate to a first temperature to sublimate one or more volatile byproducts.

Abstract: A method and system for improved planar deprocessing of semiconductor devices using a focused ion beam system. The method comprises defining a target area to be removed, the target area including at least a portion of a mixed copper and dielectric layer of a semiconductor device; directing a precursor gas toward the target area; and directing a focused ion beam toward the target area in the presence of the precursor gas, thereby removing at least a portion of a first mixed copper and dielectric layer and producing a uniformly smooth floor in the milled target area. The precursor gas causes the focused ion beam to mill the copper at substantially the same rate as the dielectric. In a preferred embodiment, the precursor gas comprises methyl nitroacetate. In alternative embodiments, the precursor gas is methyl acetate, ethyl acetate, ethyl nitroacetate, propyl acetate, propyl nitroacetate, nitro ethyl acetate, methyl methoxyacetate, or methoxy acetylchloride.

Abstract: The present disclosure is directed to a method of manufacturing a semiconductor structure in which a low-k dielectric layer is formed over a semiconductor substrate. Features can be formed proximate to the low-k dielectric layer by plasma etching with a plasma formed of a mixture of a CO2, CO, or carboxyl-containing source gas and a fluorine-containing source gas. The method allows for formation of damascene structures without encountering the problems associated with damage to a low-K dielectric layer.

Abstract: A method of selectively removing fluorocarbon layers from overlying low-k dielectric material is described. These protective plasma treatments (PPT) are delicate alternatives to traditional post-etch treatments (PET). The method includes sequential exposure to (1) a local plasma formed from a silicon-fluorine precursor followed by (2) an exposure to plasma effluents formed in a remote plasma from a fluorine-containing precursor. The remote plasma etch (2) has been found to be highly selective of the residual material following the local plasma silicon-fluorine exposure. The sequential process (1)-(2) avoids exposing the low-k dielectric material to oxygen which would undesirably increase its dielectric constant.

Abstract: The present invention provides a semiconductor structure for testing MIM capacitors. The semiconductor structure comprises: a first metal layer comprising at least a first circuit area and a second circuit area; a second metal layer located below the first metal layer with a first dielectric layer lying therebetween and connected with the second circuit area; a top plate located within the first dielectric layer closer to the first metal layer and connected with the first circuit area; a bottom plate located within the first dielectric layer closer to the second metal layer and separated from the top plate with an insulation layer therebetween and connected with the second circuit area. The second metal layer is connected with the substrate through a first electric pathway so as to form a second electric pathway from the top plate to the substrate when an electric leakage region exists in the insulation layer.

Abstract: The present invention provides a method of removing oxides. First, a substrate having the oxides is loaded into a reaction chamber, which includes a susceptor setting in the bottom portion of the chamber, a shower head setting above the susceptor, and a heater setting above the susceptor. Subsequently, an etching process is performed. A first thermal treatment process is then carried out. Finally, a second thermal treatment process is carried out, and a reaction temperature of the second thermal treatment process is higher than a reaction temperature of the first thermal treatment process.

Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.

Abstract: A method for reducing capacitances between semiconductor devices is provided. A plurality of contact structures is formed in a dielectric layer. A mask is formed to cover the contact structures wherein the mask has mask features for exposing parts of the dielectric layer wherein the mask features have widths. The widths of the mask features are shrunk with a sidewall deposition. Gaps are etched into the dielectric layer through the sidewall deposition. The gaps are closed to form pockets in the gaps.

Abstract: An etching method can selectively etch a second region formed of silicon oxide in a target object with respect to a first region formed of silicon in the target object. The etching method includes (a) processing the target object with plasma of a first processing gas containing fluorocarbon and fluorohydrocarbon by generating the plasma of the first processing gas with a microwave, and (b) after the processing of the target object with the plasma of the first processing gas, processing the target object with plasma of a second processing gas containing fluorocarbon by generating the plasma of the second processing gas with the microwave.

Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates up and down the sides of the trench. One disclosed method includes a sequential introduction of (1) a hydrogen-containing precursor and then (2) a fluorine-containing precursor into a substrate processing region. The temperature of the substrate is low during each of the two steps in order to allow the reaction to proceed and form solid residue by-product. A second disclosed method reverses the order of steps (1) and (2) but still forms solid residue by-product. The solid residue by-product is removed by raising the temperature in a subsequent sublimation step regardless of the order of the two steps.

Abstract: The invention is directed to providing a dry etching agent having little effect on the global environment but having the required performance. Provided is a dry etching agent containing, each at a specific vol %: (A) a fluorine-containing unsaturated hydrocarbon represented by the formula CaFbHc (in the formula, a, b and c are each positive integers and satisfy the correlations of 2?a?5, c<b?1, 2a+2>b+c and b?a+c, excluding the case where a=3, b=4 or c=2); (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2, COF2, F2, NF3, Cl2, Br2, I2, and YFn (where Y is Cl, Br or I and n is an integer of 1 to 5); and (C) at least one kind of gas selected from the group consisting of N2, He, Ar, Ne, Xe, and Kr.

Abstract: An etching method and apparatus for etching a silicon oxide film selectively with respect to a silicon nitride film formed on a substrate are provided. A processing gas containing a plasma excitation gas and a CHF-based gas is introduced into a processing chamber such that a flow rate ratio of the CHF-based gas to the plasma excitation gas is 1/15 or higher. By generating a plasma in the processing chamber, the silicon oxide film is etched selectively with respect to the silicon nitride film formed on the substrate in the processing chamber.

Abstract: A method for manufacturing a semiconductor structure comprising complementary bipolar transistors, wherein for manufacture of a PNP-type structure, an emitter layer having a surface oxide layer is present on top of an NPN-type structure, the emitter layer comprising lateral and vertical surfaces, and wherein for removal of the oxide layer, an ion etching step is applied, wherein for the on etching step a plasma for providing ions is generated in a vacuum chamber by RF coupling and the generated ions are accelerated by an acceleration voltage between the plasma and a wafer comprising the semiconductor structure, and wherein the plasma generation and the ion acceleration are controlled independently from each other.

Abstract: Methods and apparatus for processing using a remote plasma source are disclosed. The apparatus includes an outer chamber enclosing a substrate support, a remote plasma source, and a showerhead. A substrate heater can be mounted in the substrate support. A transport system moves the substrate support and is capable of positioning the substrate. The plasma system may be used to generate activated hydrogen species. The activated hydrogen species can be used to etch/clean semiconductor oxide surfaces such as silicon oxide or germanium oxide.

Abstract: A plasma processing apparatus includes a gas distribution member which supplies a process gas and radio frequency (RF) power to a showerhead electrode. The gas distribution member can include multiple gas passages which supply the same process gas or different process gases at the same or different flow rates to one or more plenums at the backside of the showerhead electrode. The gas distribution member provides a desired process gas distribution to be achieved across a semiconductor substrate processed in a gap between the showerhead electrode and a bottom electrode on which the substrate is supported.

Abstract: A dry etching agent according to the present invention contains (A) a fluorinated propyne represented by the chemical formula: CF3C?CX where X is H, F, Cl, Br, I, CH3, CFH2 or CF2H; and either of: (B) at least one kind of gas selected from the group consisting of O2, O3, CO, CO2, COCl2 and COF2; (C) at least one kind of gas selected from the group consisting of F2, NF3, Cl2, Br2, I2 and YFn where Y is Cl, Br or I; and n is an integer of 1 to 5; and (D) at least one kind of gas selected from the group consisting of CF4, CHF3, C2F6, C2F5H, C2F4H2, C3F8, C3F4H2, C3ClF3H and C4F8. This dry etching agent has a small environmental load and a wide process window and can be applied for high-aspect-ratio processing without special operations such as substrate excitation.

Abstract: A method for forming a pattern according to an embodiment, includes forming above a first film film patterns of a second film; forming film patterns of the first film by etching the first film using the film patterns of the second film as a mask; converting the film patterns of the second film into film patterns whose width are narrower than the film patterns of the first film by performing a slimming process; forming film patterns of a third film on both sidewalls of the film patterns of the first film and the film patterns of the second film after the slimming process; and etching the first film using the film patterns of the third film as a mask after the film patterns of the second film being removed.

Abstract: A dry etch method, apparatus, and system for etching a high-k material comprises sequentially contacting the high-k material with a vapor phase reducing agent, and a volatilizing etchant in a cyclical process. In some preferred embodiments, the reducing agent and/or volatilizing etchant is plasma activated. Control over etch rate and/or selectivity are improved by the pulsed process, where, in some embodiments, each step in the cyclical process has a self-limited extent of etching. Embodiments of the method are useful in the fabrication of integrated devices, as well as for cleaning process chambers.

Abstract: A transistor component includes an active transistor region arranged in the semiconductor body. And insulation region surrounds the active transistor region in the semiconductor body in a ring-shaped manner. A source zone, a drain zone, a body zone and a drift zone are disposed in the active transistor region. The source zone and the drain zone are spaced apart in a lateral direction of the semiconductor body and the body zone is arranged between the source zone and the drift zone and the drift zone is arranged between the body zone and the drain zone. A gate and field electrode is arranged over the active transistor region. The dielectric layer has a first thickness in a region near the body zone and a second thickness in a region near the drift zone.

Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates up and down the sides of the trench. One disclosed method includes a sequential introduction of (1) a hydrogen-containing precursor and then (2) a fluorine-containing precursor into a substrate processing region. The temperature of the substrate is low during each of the two steps in order to allow the reaction to proceed and form solid residue by-product. A second disclosed method reverses the order of steps (1) and (2) but still forms solid residue by-product. The solid residue by-product is removed by raising the temperature in a subsequent sublimation step regardless of the order of the two steps.

Abstract: A method for manufacturing a magnetic sensor that allows the sensor to be constructed with a very narrow track width and with smooth, well defined side walls. A tri-layer mask structure is deposited over a series of sensor layers. The tri-layer mask structure includes an under-layer, a Si containing hard mask deposited over the under-layer and a photoresist layer deposited over the Si containing hard mask. The photoresist layer is photolithographically patterned to define a photoresist mask. A first reactive ion etching is performed to transfer the image of the photoresist mask onto the Si containing hard mask. The first reactive ion etching is performed in a chemistry that includes CF4, CHF3, O2, and He. A second reactive ion etching is then performed in an oxygen chemistry to transfer the image of the Si containing hard mask onto the under-layer, and an ion milling is performed to define the sensor.

Abstract: Insulating layers can be formed over a semiconductor device region and etched in a manner that substantially reduces or prevents the amount of etching of the underlying channel region. A first insulating layer can be formed over a gate region and a semiconductor device region. A second insulating layer can be formed over the first insulating layer. A third insulating layer can be formed over the second insulating layer. A portion of the third insulating layer can be etched using a first etching process. A portion of the first and second insulating layers beneath the etched portion of the third insulating layer can be etched using at least a second etching process different from the first etching process.

Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.

Abstract: The invention relates to a method of etching a layer of porous dielectric material, characterized in that the etching is performed in a plasma formed from at least one silicon-based gas mixed with oxygen (O2) and/or nitrogen (N2) so as to grow a passivation layer all along said etching, at least on flanks of the layer of porous dielectric material and wherein the silicon-based gas is taken from all the compounds of the type SixHy for which the ratio x/y is equal or greater than 0.3 or is taken from all the compounds of the following types: SixFy and SixCly, where x is the proportion of silicon (Si) in the gas and y is the proportion of fluorine (F) or chlorine (Cl) or hydrogen (H) in the gas.

Abstract: A method of etching silicon oxide from a trench is described which allows more homogeneous etch rates across a varying pattern on a patterned substrate. The method also provides a more rectilinear profile following the etch process. Methods include a sequential exposure of gapfill silicon oxide. The gapfill silicon oxide is exposed to a local plasma treatment prior to a remote-plasma dry etch which may produce salt by-product on the surface. The local plasma treatment has been found to condition the gapfill silicon oxide such that the etch process proceeds at a more even rate within each trench and across multiple trenches. The salt by-product may be removed by raising the temperature in a subsequent sublimation step.

Abstract: A method of etching silicon oxide from a multiple trenches is described which allows more homogeneous etch rates among trenches. The surfaces of the etched silicon oxide within the trench following the etch may also be smoother. The method includes two dry etch stages followed by a sublimation step. The first dry etch stage removes silicon oxide quickly and produces large solid residue granules. The second dry etch stage remove silicon oxide slowly and produces small solid residue granules in amongst the large solid residue granules. Both the small and large solid residue are removed in the ensuing sublimation step. There is no sublimation step between the two dry etch stages.

Abstract: A method for fabricating a dual damascene structure includes the following steps. At first, a dielectric layer, a dielectric mask layer and a metal mask layer are sequentially formed on a substrate. A plurality of trench openings is formed in the metal mask layer, and a part of the metal mask layer is exposed in the bottom of each of the trench openings. Subsequently, a plurality of via openings are formed in the dielectric mask layer, and a part of the dielectric mask layer is exposed in a bottom of each of the via openings. Furthermore, the trench openings and the via openings are transferred to the dielectric layer to form a plurality of dual damascene openings.

Abstract: A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.

Abstract: A method for forming a semiconductor device. A substrate having thereon at least one small pattern and at least one large pattern is provided. A sacrificial layer is deposited to cover the small pattern and the large pattern. A chemical mechanical polishing is performed to planarize the sacrificial layer. The sacrificial layer is then dry etched to a thickness that is smaller than a height of the small pattern and the large pattern, thereby revealing an oxide hard mask of the small pattern and the large pattern. The oxide hard mask is then selectively removed.

Abstract: A plasma etching method includes etching an amorphous carbon film by a plasma of an oxygen-containing gas using, as a mask, an SiON film having a predetermined pattern formed on a target object, etching a silicon oxide film by a plasma of a processing gas using the amorphous carbon film as a mask while removing the SiON film remaining on the etched amorphous carbon film by the plasma of the processing gas. The plasma etching method further includes modifying the amorphous carbon film by a plasma of a sulfur-containing gas or a hydrogen-containing gas while applying a negative DC voltage to an upper electrode containing silicon after the SiON film is removed from the amorphous carbon film, and etching the silicon oxide film again by the plasma of the processing gas using the modified amorphous carbon film as a mask.

Abstract: Provided are a plasma processing method and a plasma processing apparatus which may form a protective film on the surface of an etching stop layer and suppress clogging of openings of holes when etching an oxide layer are provided. The plasma processing method forms a plurality of holes having different depths in multi-layered films that include an oxide layer, a plurality of etching stop layers made of tungsten, and a mask layer. The plasma processing method includes an etching process in which a processing gas is supplied to generate plasma such that etching is performed from the top surface of the oxide layer to the plurality of etching stop layers so as to form hole having different depths in the oxide layer. Here, the processing gas includes a fluorocarbon-based gas, a rare gas, oxygen, and nitrogen.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.

Abstract: A method for improving the uniformity of high-frequency discharge plasma by means of frequency modulation is disclosed. In a plasma discharge chamber, there is a pair of parallel electrodes. A high-frequency power supply is adopted to feed the electrodes. The frequency range of the electromagnetic field is 13.56 MHz˜160 MHz. Discharge gas is input to form plasma. The frequency of the fed-in high-frequency electromagnetic field is under automatic tuning control, and keeps changing cyclically without stop in the course of plasma discharge. The range of the frequency change may fall into either a portion of or the entire range of 13.56 MHz˜160 MHz and makes the locations with higher plasma density on the plane in parallel with the electrodes and in the plasma discharge space changed cyclically. In a time slot longer than one frequency change cycle, the average plasma density between the parallel electrodes is uniform.

Abstract: A method of suppressing the etch rate for exposed silicon-and-oxygen-containing material on patterned heterogeneous structures is described and includes a two stage remote plasma etch. Examples of materials whose selectivity is increased using this technique include silicon nitride and silicon. The first stage of the remote plasma etch reacts plasma effluents with the patterned heterogeneous structures to form protective solid by-product on the silicon-and-oxygen-containing material. The plasma effluents of the first stage are formed from a remote plasma of a combination of precursors, including a nitrogen-containing precursor and a hydrogen-containing precursor. The second stage of the remote plasma etch also reacts plasma effluents with the patterned heterogeneous structures to selectively remove material which lacks the protective solid by-product. The plasma effluents of the second stage are formed from a remote plasma of a fluorine-containing precursor.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a remote plasma etch formed from a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with a nitrogen-and-hydrogen-containing precursor. Reactants thereby produced etch the patterned heterogeneous structures with high silicon oxide selectivity while the substrate is at high temperature compared to typical Siconi™ processes. The etch proceeds without producing residue on the substrate surface. The methods may be used to remove silicon oxide while removing little or no silicon, polysilicon, silicon nitride or titanium nitride.

Abstract: A method of etching exposed silicon oxide on patterned heterogeneous structures is described and includes a gas phase etch created from a remote plasma etch. The remote plasma excites a fluorine-containing precursor. Plasma effluents from the remote plasma are flowed into a substrate processing region where the plasma effluents combine with water vapor. Reactants thereby produced etch the patterned heterogeneous structures to remove two separate regions of differing silicon oxide at different etch rates. The methods may be used to remove low density silicon oxide while removing less high density silicon oxide.

Abstract: An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.

Abstract: A method for fabricating a carbon hard mask layer includes: loading a substrate with a pattern target layer into a chamber; performing a primary thermal treatment on the substrate; depositing a carbon hard mask layer over the pattern target layer by using CxHy gas to perform the primary thermal treatment; performing a secondary thermal treatment on the substrate on which the carbon hard mask layer is deposited; and performing an oxygen treatment on the carbon hard mask layer.

Abstract: One method disclosed herein includes the steps of forming a ULK material layer, forming a hard mask layer above the ULK material layer, forming a patterned photoresist layer above the hard mask layer, performing at least one etching process to define an opening in at least the ULK material layer for a conductive structure to be positioned in at least the ULK material layer, forming a fill material such that it overfills the opening, performing a process operation to remove the patterned photoresist layer and to remove the fill material positioned outside of the opening, removing the fill material from within the opening and, after removing the fill material from within the opening, forming a conductive structure in the opening.

Abstract: The present invention is a plasma etching gas comprising a fluorocarbon having 3 or 4 carbon atoms, the fluorocarbon including at least one unsaturated bond and/or ether linkage, and including a bromine atom, and a plasma etching method comprising subjecting a silicon oxide film on a substrate to plasma etching through a mask using a process gas, the process gas being the plasma etching gas. This plasma etching gas exhibits excellent etching selectivity, and has a short atmospheric lifetime and a low environmental impact. This plasma etching method makes it possible to selectively subject a silicon oxide film to plasma etching at a high etching rate without causing an increase in surface roughness.

Abstract: A method for fabricating a semiconductor chip module and a semiconductor chip package is disclosed. One embodiment provides a first layer, a second layer, and a base layer. The first layer is disposed on the base layer, and the second layer is disposed on the first layer. A plurality of semiconductor chips is applied above the second layer, and the second layer with the applied semiconductor chips is separated from the first layer.

Abstract: A method for etching a dielectric layer disposed below a patterned organic mask with features, with hardmasks at bottoms of some of the organic mask features is provided. An etch gas is provided. The etch gas is formed into a plasma. A bias RF with a frequency between 2 and 60 MHz is provided that provides pulsed bias with a pulse frequency between 10 Hz and 1 kHz wherein the pulsed bias selectively deposits on top of the organic mask with respect to the dielectric layer.

Abstract: A processing gas is introduced to remove an oxide film on the surface of a silicon substrate 5. F radicals are allowed to act on the surface of the silicon substrate to etch a silicon layer. Then, NH3 gas, N2 gas and NF3 gas are introduced, allowing NHxFy to act on the oxidized surface of the silicon substrate 5, thereby forming (NH4)2SiF6. The resulting (NH4)2SiF6 is sublimated to remove by-products (SiOF, SiOH) on the surface of the silicon substrate 5.

Abstract: There is provided a method for manufacturing a SiC semiconductor device achieving improved performance. The method for manufacturing the SiC semiconductor device includes the following steps. That is, a SiC semiconductor is prepared which has a first surface having at least a portion into which impurities are implanted. By cleaning the first surface of the SiC semiconductor, a second surface is formed. On the second surface, a Si-containing film is formed. By oxidizing the Si-containing film, an oxide film constituting the SiC semiconductor device is formed.

Abstract: A method for forming an opening in a semiconductor device is provided, including: providing a semiconductor substrate with a silicon oxide layer, a polysilicon layer and a silicon nitride layer sequentially formed thereover; patterning the silicon nitride layer, forming a first opening in the silicon nitride layer, wherein the first opening exposes a top surface of the polysilicon layer; performing a first etching process, using gasous etchants including hydrogen bromide (HBr), oxygen (O2), and fluorocarbons (CxFy), forming a second opening in the polysilicon layer, wherein a sidewall of the polysilicon layer adjacent to the second opening is substantially perpendicular to a top surface of the silicon oxide layer, wherein x is between 1-5 and y is between 2-8; removing the silicon nitride layer; and performing a second etching process, forming a third opening in the silicon oxide layer exposed by the second opening.

Abstract: There is provided a plasma processing apparatus capable of optimizing a plasma process in response to various requirements of a micro processing by effectively controlling a RF bias function. In this plasma processing apparatus, a high frequency power RFH suitable for generating plasma of a capacitively coupling type is applied to an upper electrode 48 (or lower electrode 16) from a third high frequency power supply 66, and two high frequency powers RFL1 (0.8 MHz) and RFL2 (13 MHz) suitable for attracting ions are applied to the susceptor 16 from first and second high frequency power supplies 36 and 38, respectively, in order to control energy of ions incident onto a semiconductor wafer W from the plasma. A control unit 88 controls a total power and a power ratio of the first and second high frequency powers RFL1 and RFL2 depending on specifications, conditions or recipes of an etching process.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: Provided are methods and systems for removing a native silicon oxide layer on a wafer. In a non-sequential approach, a wafer is provided with a native silicon oxide layer on a polysilicon layer. An etchant including a hydrogen-based species and a fluorine-based species is introduced, exposed to a plasma, and flowed onto the wafer at a relatively low temperature. The wafer is then heated to a slightly elevated temperature to substantially remove the native oxide layer. In a sequential approach, a wafer is provided with a native silicon oxide layer. A first etchant including a hydrogen-based species and a fluorine-based species is flowed onto the wafer. Then the wafer is heated to a slightly elevated temperature, a second etchant is flowed towards the wafer, and the second etchant is exposed to a plasma to complete the removal of the native silicon oxide layer and to initiate removal of another layer such as a polysilicon layer.

Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.