Silicon Oxide Or Glass Patents (Class 438/723)
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Patent number: 8288287Abstract: The invention provides an etching method for realizing trench etching without causing any damages to the side walls of the trench while maintaining a high-etching rate. The plasma etching method relates to forming a groove or a hole by forming a silicon trench to a silicon substrate or a silicon substrate having a silicon oxide dielectric layer via a mixed gas plasma containing a mixed gas of SF6 and O2 or a mixed gas of SF6, O2 and SiF4 and having added thereto a gas containing hydrogen within the range of 5 to 16% (percent concentration) of the total gas flow rate of the mixed gas.Type: GrantFiled: March 24, 2008Date of Patent: October 16, 2012Assignee: Hitachi High-Technologies CorporationInventors: Kazuo Takata, Yutaka Kudou, Satoshi Tani
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Patent number: 8257599Abstract: In a thermal head manufacturing method, at least one concave portion is formed on a surface of a first substrate, and a second substrate comprised of a first layer and a second layer that is denser and harder than the first layer is provided. The first and second substrates are bonded to one another so that the second layer of the second substrate covers the concave portion of the first substrate. The first layer of the second substrate is then etched until a surface of the second layer of the second substrate is exposed. At least one heating resistor is formed on the exposed surface of the second layer of the second substrate after the etching step so that the heating resistor is disposed over the concave portion of the first substrate.Type: GrantFiled: December 3, 2009Date of Patent: September 4, 2012Assignee: Seiko Instruments Inc.Inventors: Norimitsu Sanbongi, Toshimitsu Morooka, Keitaro Koroishi, Noriyoshi Shoji, Yoshinori Sato
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Patent number: 8252696Abstract: Methods for etching dielectric layers comprising silicon and nitrogen are provided herein. In some embodiments, such methods may include providing a substrate having a dielectric layer comprising silicon and nitrogen disposed thereon, forming reactive species from a process gas comprising hydrogen (H2) and nitrogen trifluoride (NF3) using a remote plasma; and etching the dielectric layer using the reactive species. In some embodiments, an oxide layer is disposed adjacent to the dielectric layer. In some embodiments, the flow rate ratio of the process gas can be adjusted such that an etch selectivity of the dielectric layer to at least one of the oxide layer or the substrate is between about 0.8 to about 4.Type: GrantFiled: October 7, 2008Date of Patent: August 28, 2012Assignee: Applied Materials, Inc.Inventors: Xinliang Lu, Haichun Yang, Zhenbin Ge, Nan Lu, David T. Or, Chien-Teh Kao, Mei Chang
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Patent number: 8246846Abstract: A method for fabricating integrated MEMS switches and filters includes forming cavities in a silicon substrate, metalizing a first pattern on a quartz substrate to form first switch and filter elements, bonding the quartz substrate to the silicon substrate so that the first switch and filter elements are located within one of the cavities, thinning the quartz substrate, forming conductive vias in the quartz substrate, metalizing a second pattern on a second surface of the quartz substrate to form second switch and filter elements, etching the quartz substrate to separate MEMS switches from filters, forming protrusions on a host substrate, metalizing a third metal pattern on the host substrate to form metal anchors and third switch elements, compression bonding the metal anchors on the host substrate to second switch and filter elements, forming signal lines to integrate the MEMS switches and filters and removing the silicon substrate.Type: GrantFiled: September 24, 2010Date of Patent: August 21, 2012Assignee: HRL Laboratories, LLCInventors: David T. Chang, Tsung-Yuan Hsu
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Patent number: 8236701Abstract: A plasma processing apparatus includes a processing chamber arranged in a vacuum vessel. A wafer placed on a sample stage in the processing chamber is processed using a plasma formed in the processing chamber. Before etching the film layers provided on the wafer composed of a metal substance and an underlying oxide film or a material having a high dielectric constant, another wafer, provided on a surface thereof a film composed of a metal of the same kind as the metal substance, is processed and particles of the metal are deposited on an inner wall of said processing chamber.Type: GrantFiled: February 26, 2009Date of Patent: August 7, 2012Assignee: Hitachi High-Technologies CorporationInventors: Masahiro Sumiya, Motohiro Tanaka, Kousa Hirota
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Patent number: 8211805Abstract: The invention provides a method for forming a via. A first dielectric layer is formed on a substrate. A conductive structure is formed in the first dielectric layer. A second dielectric layer is formed on the first dielectric layer and conductive structure. A first etching step is performed by using a first etching mixture to form a first via in the second dielectric layer. A second etching step is performed by using a second etching mixture to form a second via under the first via. The second via exposes at least a top surface of the conductive structure. An etching rate of the second etching step is slower than the first etching step.Type: GrantFiled: February 13, 2009Date of Patent: July 3, 2012Assignee: Vanguard International Semiconductor CorporationInventors: Wen-Shun Lo, Hsing-Chao Liu
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Patent number: 8211796Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: GrantFiled: October 27, 2011Date of Patent: July 3, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 8211806Abstract: A method of manufacturing an integrated circuit with a small pitch comprises providing a second material layer patterned to form at least two features with an opening between the features. The second material layer is formed over a first material layer and the first material layer is over a substrate. The method also comprises providing a first oxide layer to form a first sidewall surrounding each of the features, and providing a second oxide layer over the first sidewalls and the first material layer. A second sidewall is formed surrounding each of the features. The method further comprises providing a conductive layer over the second oxide layer and removing the conductive layer, the second sidewalls and the first material underneath the second sidewalls.Type: GrantFiled: August 29, 2007Date of Patent: July 3, 2012Assignee: MACRONIX International Co., Ltd.Inventors: Chia-Wei Wu, Ling-Wu Yang
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Patent number: 8198147Abstract: In a replacement gate approach for forming high-k metal gate electrodes in semiconductor devices, a tapered configuration of the gate openings may be accomplished by using a tensile stressed dielectric material provided laterally adjacent to the gate electrode structure. Consequently, superior deposition conditions may be achieved while the tensile stress component may be efficiently used for the strain engineering in one type of transistor. Furthermore, an additional compressively stressed dielectric material may be applied after providing the replacement gate electrode structures.Type: GrantFiled: August 11, 2010Date of Patent: June 12, 2012Assignee: GlobalFoundries, Inc.Inventors: Frank Feustel, Kai Frohberg, Thomas Werner
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Patent number: 8187974Abstract: Methods of manufacturing semiconductor devices and methods of optical proximity correction methods are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes determining an amount of reactive ion etch (RIE) lag of a RIE process for a material layer of the semiconductor device, and adjusting a size of at least one pattern for a feature of the material layer by an adjustment amount to partially compensate for the amount of RIE lag determined.Type: GrantFiled: December 19, 2007Date of Patent: May 29, 2012Assignee: Infineon Technologies AGInventors: O Seo Park, Wai-Kin Li
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Patent number: 8187981Abstract: A substrate processing method includes preparing a substrate having a low-k interlayer dielectric film as a to-be-etched film and a photoresist film, formed on the low-k interlayer insulating film, serving as an etching mask with a predetermined circuit pattern; etching the low-k interlayer insulating film through the photoresist film to form grooves and/or holes in the low-k interlayer insulating film; ashing the photoresist film by using hydrogen radicals generated by bring a hydrogen-containing gas into contact with a catalyst of a high temperature; and recovering damage to the low-k interlayer insulating film due to the ashing by supplying a specific recovery gas. The method further includes recovering damage to the low-k interlayer insulating film due to the etching by supplying a specific recovery gas.Type: GrantFiled: October 11, 2007Date of Patent: May 29, 2012Assignee: Tokyo Electron LimitedInventors: Kazuhiro Tomioka, Nobuyoshi Kobayashi, Isamu Sakuragi, Kazuhiro Kubota
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Patent number: 8187486Abstract: Etching of nitride and oxide layers with reactant gases is modulated by etching in different process regimes. High etch selectivity to silicon nitride is achieved in an adsorption regime where the partial pressure of the etchant is lower than its vapor pressure. Low etch selectivity to silicon nitride is achieved in a condensation regime where the partial pressure of the etchant is higher than its vapor pressure. By controlling partial pressure of the etchant, very high etch selectivity to silicon nitride may be achieved.Type: GrantFiled: December 13, 2007Date of Patent: May 29, 2012Assignee: Novellus Systems, Inc.Inventors: Xinye Liu, Chiukin Steven Lai
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Patent number: 8187980Abstract: An etching method for forming a groove by etching a silicon layer of a substrate by using a mask which has a first region where an opening with a first opening width is formed and a second region where an opening with a second opening width larger than the first opening width is formed, the method includes: mounting the substrate on a mounting table in a processing chamber; converting a processing gas containing Cl2 gas, HBr gas, and one of CO gas and CO2 gas into a plasma; and etching the silicon layer by the plasma.Type: GrantFiled: January 29, 2008Date of Patent: May 29, 2012Assignee: Tokyo Electron LimitedInventor: Kosuke Ogasawara
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Patent number: 8187971Abstract: A method of manufacturing a semiconductor device is described. The method comprises performing a gas cluster ion beam (GCIB) pre-treatment and/or post-treatment of at least a portion of a silicon-containing substrate during formation of a silicide region.Type: GrantFiled: September 1, 2010Date of Patent: May 29, 2012Assignee: TEL Epion Inc.Inventors: Noel Russell, John J. Hautala, John Gumpher
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Patent number: 8177990Abstract: Disclosed is a method of etching a substrate having a layered structure in which a photoresist mask with a pattern, a coating film made of silicon oxide, and an organic film are laminated in that order from the top. Before etching the coating film of silicon oxide, a deposit is deposited on the photoresist mask by using plasma generated from a hydrocarbon gas such as CH4 gas so as to narrow the size of openings in the pattern of the photoresist mask. The pattern of the photoresist mask is well transferred to the organic film through the coating film, and a pattern with openings having a high aspect ratio can be formed in the organic film and toppling of the pattern in the organic film can be prevented. The organic film with the transferred pattern is used as an etch mask for etching the underlying layer.Type: GrantFiled: March 29, 2007Date of Patent: May 15, 2012Assignee: Tokyo Electron LimitedInventors: Ryou Mochizuki, Jun Yashiro
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Patent number: 8173549Abstract: A first mask layer pattern including a plurality of parallel line portions is formed on an etch target layer on a semiconductor substrate. A sacrificial layer is formed on the first mask layer pattern and portions of the etch target layer between the parallel line portions of the first mask layer pattern. A second mask layer pattern is formed on the sacrificial layer, the second mask layer pattern including respective parallel lines disposed between respective adjacent ones of the parallel line portions of the first mask layer pattern, wherein adjacent line portions of the first mask layer pattern and the second mask layer pattern are separated by the sacrificial layer. A third mask layer pattern is formed including first and second portions covering respective first and second ends of the line portions of the first mask layer pattern and the second mask layer pattern and having an opening at the line portions of the first and second mask layer patterns between the first and second ends.Type: GrantFiled: June 3, 2009Date of Patent: May 8, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Young-ho Lee, Jae-hwang Sim, Jae-kwan Park, Jong-min Lee, Mo-seok Kim, Hyon-woo Kim
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Patent number: 8153019Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, prevents higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.Type: GrantFiled: August 6, 2007Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Nishant Sinha, J. Neil Greeley
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Patent number: 8153502Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.Type: GrantFiled: May 16, 2006Date of Patent: April 10, 2012Assignee: Micron Technology, Inc.Inventors: Li Li, Ronald Weimer, Richard Stocks, Chris Hill
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Publication number: 20120077347Abstract: A method for selectively etching a substrate is described. The method includes preparing a substrate comprising a silicon nitride layer overlying a silicon-containing contact region, and patterning the silicon nitride layer to expose the silicon-containing contact region using a plasma etching process in a plasma etching system. The plasma etching process uses a process composition having as incipient ingredients a process gas containing C, H and F, and a non-oxygen-containing additive gas, wherein the non-oxygen-containing additive gas includes H, or C, or both H and C, and excludes a halogen atom.Type: ApplicationFiled: September 28, 2010Publication date: March 29, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Andrew W. METZ, Hongyun COTTLE
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Patent number: 8138096Abstract: In a plasma etching method, a substrate including an underlying film, an insulating film and a resist mask is plasma etched to thereby form a number of holes in the insulating film including a dense region and a sparse region by using a parallel plate plasma etching apparatus for applying a plasma-generating high frequency electric power to a space between an upper and a lower electrode and a biasing high frequency electric power to the lower electrode. The plasma etching method includes mounting the substrate on a mounting table; supplying a first process gas containing carbon and fluorine to form the holes in the insulating film to a depth close to the underlying film; and supplying a second process gas including an inert gas and another gas contain carbon and fluorine to have the holes reach the underlying film while applying a negative DC voltage to the upper electrode.Type: GrantFiled: February 4, 2008Date of Patent: March 20, 2012Assignee: Tokyo Electron LimitedInventor: Ryoichi Yoshida
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Patent number: 8133814Abstract: Methods are provided for fabricating a semiconductor device. One embodiment includes forming an insulator layer overlying a semiconductor substrate and depositing a layer of polycrystalline silicon overlying the insulator layer. Conductivity determining impurity ions are implanted into at least an upper portion of the layer of polycrystalline silicon. At least the upper portion of the layer of polycrystalline silicon is etched using a first anisotropic etch chemistry to expose an edge portion of the upper portion. An oxide barrier is formed on the edge portion and a further portion of the layer of polycrystalline silicon is etched using the first anisotropic etch chemistry. Then a final portion of the layer of polycrystalline silicon is etched using a second anisotropic etch chemistry.Type: GrantFiled: December 3, 2010Date of Patent: March 13, 2012Assignee: GLOBALFOUNDRIES Inc.Inventors: Steffen Laufer, Gunter Grasshoff
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Patent number: 8129282Abstract: In a plasma etching method, a substrate, on which an oxide film as a target layer to be etched, a hard mask layer, and a patterned photoresist are sequentially formed, is loaded into the processing chamber and mounted on a lower electrode. A processing gas containing CxFy (x is 3 or less and y is 8 or less), C4F8, a rare gas and O2 is supplied and a plasma of the processing gas is generated by applying a high frequency power to an upper or a lower electrode. Further, a high frequency power for bias is applied to the lower electrode, and a DC voltage is applied to the upper electrode.Type: GrantFiled: July 6, 2007Date of Patent: March 6, 2012Assignee: Tokyo Electron LimitedInventors: Kosei Ueda, Hikoichiro Sasaki
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Patent number: 8124534Abstract: A process including forming a silicon layer over a semiconductor wafer having features thereon and then selectively ion implanting in the silicon layer to form ion implanted regions. The step of selectively ion implanting is repeated as many times as necessary to obtain a predetermined number and density of features. Thereafter, the silicon layer is etched to form openings in the silicon layer that were formerly occupied by the ion implanted regions. The opened areas in the silicon layer form a mask for further processing of the semiconductor wafer.Type: GrantFiled: July 22, 2008Date of Patent: February 28, 2012Assignee: International Business Machines CorporationInventors: Jin Wallner, Thomas A. Wallner, Ying Zhang
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Patent number: 8124536Abstract: A method for manufacturing a capacitor electrode by removing a silicon oxide film on a surface of a substrate, including: transforming the silicon oxide film into a reaction product by supplying a gas containing a halogen element to chemically react with the silicon oxide film while controlling temperature of the substrate to a first process temperature; and removing the silicon oxide film transformed to the reaction product while controlling the temperature of the substrate to a second process temperature higher than the first process temperature. The silicon oxide film is a BPSG film.Type: GrantFiled: November 28, 2007Date of Patent: February 28, 2012Assignee: Tokyo Electron LimitedInventor: Eiichi Nishimura
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Patent number: 8119537Abstract: A method is provided for selectively etching native oxides or other contaminants to metal nitrides and metal oxides during manufacture of a semiconductor device. The method utilizes a substantially non-aqueous etchant which includes a source of fluorine ions. In a preferred embodiment, the etchant comprises H2SO4 and HF. The etchant selectively etches native and doped oxides or other contaminants without excessively etching metal nitrides or metal oxides on the substrate or on adjacent exposed surfaces.Type: GrantFiled: June 17, 2005Date of Patent: February 21, 2012Assignee: Micron Technology, Inc.Inventors: Kevin R. Shea, Kevin J. Torek
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Patent number: 8114778Abstract: A method of forming minute patterns in a semiconductor device, and more particularly, a method of forming minute patterns in a semiconductor device having an even number of insert patterns between basic patterns by double patterning including insert patterns between a first basic pattern and a second basic pattern which are transversely separated from each other on a semiconductor substrate, wherein a first insert pattern and a second insert pattern are alternately repeated to form the insert patterns, the method includes the operation of performing a partial etching toward the second insert pattern adjacent to the second basic pattern, or the operation of forming a shielding layer pattern, thereby forming the even number of insert patterns.Type: GrantFiled: October 15, 2010Date of Patent: February 14, 2012Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-yong Park, Jae-kwan Park, Yong-sik Yim, Jae-hwang Sim
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Patent number: 8114732Abstract: A method and system for forming a non-volatile memory structure. The method includes providing a semiconductor substrate and forming a gate dielectric layer overlying a surface region of the semiconductor substrate. A polysilicon gate structure is formed overlying the gate dielectric layer. The method subjects the polysilicon gate structure to an oxidizing environment to cause formation of a first silicon oxide layer overlying the polysilicon gate structure and formation of an undercut region underneath the polysilicon gate structure. An aluminum oxide material is formed overlying the polysilicon gate structure filling the undercut region. In a specific embodiment, the aluminum oxide material has a nanocrystalline silicon material sandwiched between a first aluminum oxide layer and a second aluminum oxide layer. The aluminum oxide material is subjected to a selective etching process while maintaining the aluminum oxide material in an insert region in a portion of the undercut region.Type: GrantFiled: February 11, 2010Date of Patent: February 14, 2012Assignee: Semiconductor Manufacturing International (Shanghai) CorporationInventor: Mieno Fumitake
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Patent number: 8114781Abstract: A substrate processing method capable of selectively removing a nitride film. Oxygen plasma containing plasmarized oxygen gas is made to be in contact with a silicon nitride film, which is made of SiN, of a wafer to thereby cause the silicon nitride film to be changed to a silicon monoxide film. The silicon monoxide film is selectively etched by hydrofluoric acid generated from HF gas supplied toward the silicon monoxide film.Type: GrantFiled: June 27, 2007Date of Patent: February 14, 2012Assignee: Tokyo Electron LimitedInventors: Eiichi Nishimura, Koichi Yatsuda
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Patent number: 8093156Abstract: To provide a method for manufacturing a semiconductor device, which the method is capable of efficient mass production of high-performance semiconductor devices by, upon manufacture of a semiconductor device, eliminating unwanted features (e.g., side lobes) created together with a resist pattern by thickening the resist pattern, to reduce the burden in designing photomasks and to increase depth of focus. The method of the present invention for manufacturing a semiconductor device includes at least: forming a resist pattern on a work surface and applying over a surface of the resist pattern a resist pattern thickening material to thereby thicken the resist pattern to eliminate an unwanted feature created together with the resist pattern.Type: GrantFiled: January 22, 2007Date of Patent: January 10, 2012Assignee: Fujitsu Semiconductor LimitedInventors: Yuji Setta, Hajime Yamamoto
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Patent number: 8093155Abstract: A method for controlling striations and CD loss in a plasma etching method is disclosed. During the etching process, the substrate of semiconductor material to be etched is exposed first to plasma under a low power strike and subsequently to a conventional high power strike. CD loss has been found to be reduced by about 400 Angstroms and striations formed in the contact holes are reduced.Type: GrantFiled: December 2, 2008Date of Patent: January 10, 2012Assignee: Micron Technology, Inc.Inventors: Li Li, Bradley J. Howard
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Patent number: 8088691Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.Type: GrantFiled: February 26, 2009Date of Patent: January 3, 2012Assignee: Micron Technology, Inc.Inventors: Mark Kiehlbauch, Ted Lyle Taylor
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Publication number: 20110318935Abstract: Provided is a method of setting a thickness of a dielectric, which restrains the dielectric formed in an electrode from being consumed when etching a silicon dioxide film on a substrate by using plasma. In a substrate processing apparatus including an upper electrode facing a susceptor and the dielectric formed of silicon dioxide in the upper electrode, a silicon dioxide film formed on a wafer being etched by using plasma, an electric potential of the plasma facing the dielectric in a case where the dielectric is not formed in the upper electrode is estimated based on a bias power applied to the susceptor and an A/C ratio in a chamber, and the thickness of the dielectric is determined so that an electric potential of the plasma, which is obtained by multiplying the estimated electric potential of the plasma by a capacity reduction coefficient calculated when a capacity of the dielectric and a capacity of a sheath generated around a surface of the dielectric are combined, is 100 eV or less.Type: ApplicationFiled: June 29, 2011Publication date: December 29, 2011Applicant: TOKYO ELECTRON LIMITEDInventors: Jun OYABU, Takashi KITAZAWA
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Patent number: 8070973Abstract: Apparatus including: a substrate layer having a substantially planar top surface; an optically conductive peak located and elongated on, and spanning a first thickness measured in a direction generally away from, the top surface; the optically conductive peak having first and second lateral walls each including distal and proximal lateral wall portions, the proximal lateral wall portions intersecting the top surface; and first and second sidewall layers located on the distal lateral wall portions, the sidewall layers not intersecting the top surface and spanning a second thickness that is less than the first thickness measured in the same direction.Type: GrantFiled: September 29, 2008Date of Patent: December 6, 2011Assignee: Alcatel LucentInventors: Young-Kai Chen, Andreas Bertold Leven, Yang Yang
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Patent number: 8062973Abstract: A semiconductor device manufacturing method has conducting first heating processing at a first heating temperature in an inert atmosphere under a first pressure in a first process chamber to silicide an upper part of the source-drain diffusion layer and form a silicide film; conducting second heating processing at a second heating temperature in an oxidizing atmosphere under a second pressure in a second process chamber to selectively oxidize at least a surface of the metal film on the element isolating insulation film and form a metal oxide film; conducting third heating processing at a third heating temperature which is higher than the first heating temperature and the second heating temperature in an atmosphere in a third process chamber to increase a concentration of silicon in the silicide film; and selectively removing the metal oxide film and an unreacted part of the metal film on the element isolating insulation film.Type: GrantFiled: January 25, 2010Date of Patent: November 22, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Takaharu Itani, Koji Matsuo, Kazuhiko Nakamura
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Patent number: 8043972Abstract: Methods for accurate and conformal removal of atomic layers of materials make use of the self-limiting nature of adsorption of at least one reactant on the substrate surface. In certain embodiments, a first reactant is introduced to the substrate in step (a) and is adsorbed on the substrate surface until the surface is partially or fully saturated. A second reactant is then added in step (b), reacting with the adsorbed layer of the first reactant to form an etchant. The amount of an etchant, and, consequently, the amount of etched material is limited by the amount of adsorbed first reactant. By repeating steps (a) and (b), controlled atomic-scale etching of material is achieved. These methods may be used in interconnect pre-clean applications, gate dielectric processing, manufacturing of memory devices, or any other applications where removal of one or multiple atomic layers of material is desired.Type: GrantFiled: July 16, 2008Date of Patent: October 25, 2011Assignee: Novellus Systems, Inc.Inventors: Xinye Liu, Joshua Collins, Kaihan A. Ashtiani
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Patent number: 8034719Abstract: To fabricate high aspect ratio metal structures, a two-layer structure is provided on a conductive layer. The two-layer structure includes a first layer adjacent the conductive layer and a second layer adjacent the first layer where the second layer is etchable by a Deep Reactive Ion Etching (DRIE) process. Using the DRIE process, at least one selected region of the second layer is completely etched away with the selected region being at least partially aligned with a region of the conductive layer such that the first layer is then exposed thereover. The first layer so-exposed is then removed to expose the region of the conductive layer thereunder. Metal is electroplated onto the exposed conductive layer and any remaining portions of the two-layer structure are then removed.Type: GrantFiled: December 8, 2005Date of Patent: October 11, 2011Assignee: The United States of America as represented by the Secretary of the NavyInventors: Daniel L. Jean, Michael Deeds, Allen Keeney
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Patent number: 8030156Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.Type: GrantFiled: December 4, 2009Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventor: Russell A. Benson
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Publication number: 20110230052Abstract: A method of etching silicon oxide from a narrow trench and a wide trench (or open area) is described which allows the etch in the wide trench to progress further than the etch in the narrow trench. The method includes two dry etch cycles. The first dry etch cycle involves a low intensity or abbreviated sublimation step which leaves solid residue in the narrow trench. The remaining solid residue inhibits etch progress in the narrow trench during the second dry etch cycle allowing the etch in the wide trench to overtake the etch in the narrow trench.Type: ApplicationFiled: December 2, 2010Publication date: September 22, 2011Applicant: Applied Materials, Inc.Inventors: Jing Tang, Nitin Ingle, Dongqing Yang, Shankar Venkataraman
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Patent number: 8021565Abstract: A surface treatment method includes: removing a fluorocarbon-containing reaction product from a surface of a workpiece by oxygen gas plasma processing. The workpiece includes a plurality of layers. The fluorocarbon-containing reaction product is deposited by successively etching the layers of the workpiece. The method further includes after removing the reaction product, removing an oxide-containing reaction product from the surface of the workpiece using hydrogen fluoride gas.Type: GrantFiled: March 24, 2008Date of Patent: September 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Katsuaki Aoki, Naoya Hayamizu, Kei Hattori, Yukihiro Oka, Hidemi Kanetaka, Makoto Hasegawa
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Patent number: 8012877Abstract: Exemplary embodiments provide a method for fabricating an integrated circuit (IC) device with reduced streak defects. In one embodiment, the IC device structure can be formed having a first pad oxide-based layer on a front side of a semiconductor substrate and having an oxide-nitride-based structure on a backside of the semiconductor substrate. The IC device structure can be etched to remove a nitride-related material from the backside oxide-nitride-based structure, and further to remove the first pad oxide-based layer from the front side of the semiconductor substrate. On the removed front side of the semiconductor substrate a second pad oxide-based layer can be formed, e.g., for forming an isolation structure for device component or circuitry isolation.Type: GrantFiled: November 19, 2008Date of Patent: September 6, 2011Assignee: Texas Instruments IncorporatedInventor: Scott Cuong Nguyen
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Patent number: 8008209Abstract: A technique is described whereby temperature gradients are created within a semiconductor wafer. Temperature sensitive etching and/or deposition processes are then employed. These temperature sensitive processes proceed at different rates in regions with different temperatures. To reduce pinch off in etching processes, a temperature sensitive etch process is selected and a temperature gradient is created between the surface and subsurface of a wafer such that the etching process proceeds more slowly at the surface than deeper in the wafer. This reduces “crusting” of solid reaction products at trench openings, thereby eliminating pinch off in many cases. Similar temperature-sensitive deposition processes can be employed to produce void-free high aspect ratio conductors and trench fills.Type: GrantFiled: October 24, 2007Date of Patent: August 30, 2011Assignee: International Business Machines CorporationInventors: Michael R. Sievers, Kaushik A. Kumar, Andres F. Munoz, Richard Wise
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Patent number: 8008212Abstract: Fabrication methods for integrating CMOS and BJT devices are presented. A semiconductor substrate having a first region and a second region are provided, wherein the first region includes a CMOS device, and the second region includes a BJT device. A dielectric layer is conformably deposited on the semiconductor substrate. Part of the dielectric layer is removed, thereby forming sidewall spacers on a gate structure of the CMOS device and remaining a thin dielectric layer on the BJT device. The remaining thin dielectric layer is completely removed, completing integration of the CMOS device and the BJT device.Type: GrantFiled: November 25, 2008Date of Patent: August 30, 2011Assignee: Vanguard International Semiconductor CorporationInventors: Chien-Hsien Song, Yung-Lung Chou, Yu-Hsun Chen, Cheng-Che Tsai
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Patent number: 8003543Abstract: A method of forming hard mask employs a double patterning technique. A first hard mask layer is formed on a substrate, and a first sacrificial pattern is formed on the first hard mask layer by photolithography. Features of the first sacrificial pattern are spaced from one another by a first pitch. A second hard mask layer is then formed conformally on the first sacrificial pattern and the first hard mask layer so as to delimit recesses between adjacent features of the first sacrificial pattern. Upper portions of the second hard mask layer are removed to expose the first sacrificial pattern, and the exposed first sacrificial pattern and the second sacrificial pattern are removed. The second hard mask layer and the first hard mask layer are then etched to form a hard mask composed of residual portions of the first hard mask layer and the second hard mask layer.Type: GrantFiled: April 14, 2010Date of Patent: August 23, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Cha-won Koh, Han-ku Cho, Jeong-lim Nam, Gi-sung Yeo, Joon-soo Park, Ji-young Lee
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Patent number: 7998876Abstract: A method of producing a semiconductor element includes the steps of forming a wiring portion layer on a substrate; forming an interlayer insulation layer over the substrate and the wiring portion layer, in which a third insulation film, a second insulation film, and a first insulation film are laminated in this order from the substrate; forming a mask pattern on the first insulation film; removing a contact hole forming area of the first insulation film through a wet etching process; removing a contact hole forming area of the second insulation film through an etching process; removing a contact hole forming area of the third insulation film through an etching process; and a contact hole forming step of forming a contact hole in the interlayer insulation layer so that a surface of the wiring portion layer is exposed.Type: GrantFiled: March 11, 2010Date of Patent: August 16, 2011Assignee: Oki Semiconductor Co., Ltd.Inventor: Toshiyuki Orita
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Publication number: 20110195578Abstract: A method and manufacture for charge storage layer separation is provided. A layer, such as a polymer layer, is deposited on top of an ONO layer so that the polymer layer is planarized, or approximately planarized. The ONO includes at least a first region and a second region, where the first region is higher than the second region. For example, the first region may be the portion of the ONO that is over the source/drain region, and the second region may be the portion of the ONO that is over the shallow trench. Etching is performed on the polymer layer to expose the first region of the ONO layer, leaving the second region of the ONO unexposed. The etching continues to occur to etch the exposed ONO at the first region so that the ONO layer is etched away in the first region and the second region remains unexposed.Type: ApplicationFiled: February 10, 2010Publication date: August 11, 2011Applicant: SPANSION LLCInventors: Angela T. Hui, Gang Xue
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Patent number: 7988873Abstract: A method of forming a mask pattern for fabricating a semiconductor device. A first region and a second region, having an intersecting third region, are defined in the semiconductor substrate. An inorganic mask layer is etched in the first region to a predetermined thickness, and etched in the second region to another predetermined thickness. While the inorganic mask layer is etched in the first and second region, an organic mask layer is exposed in the third region. The organic mask layer exposed in the third region is removed to form a mask pattern. Consequently, double exposure is performed using the organic mask layer and the inorganic mask layer, so that a fine feature size that closely follows a desired layout can be formed, damage to the organic mask layer by ashing is prevented, and adhesiveness between the organic mask layer and the inorganic mask layer can be improved.Type: GrantFiled: June 26, 2007Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Hyong-Soo Kim, Sang-Hyeop Lee
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Patent number: 7989333Abstract: Methods of forming integrated circuit devices include forming a gate electrode on a substrate and forming a nitride layer on a sidewall and upper surface of the gate electrode. The nitride layer is then anisotropically oxidized under conditions that cause a first portion of the nitride layer extending on the upper surface of the gate electrode to be more heavily oxidized relative to a second portion of the nitride layer extending on the sidewall of the gate electrode. A ratio of a thickness of an oxidized first portion of the nitride layer relative to a thickness of an oxidized second portion of the nitride layer may be in a range from about 3:1 to about 7:1.Type: GrantFiled: May 19, 2009Date of Patent: August 2, 2011Assignee: Samsung Electronics Co., Ltd.Inventors: Jae-Hwa Park, Jong-Min Baek, Gil-Heyun Choi, Hee-Sook Park
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Patent number: 7985691Abstract: An organic/inorganic hybrid film represented by SiCxHyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.Type: GrantFiled: April 23, 2010Date of Patent: July 26, 2011Assignee: Panasonic CorporationInventors: Kenshi Kanegae, Shinichi Imai, Hideo Nakagawa
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Patent number: 7981308Abstract: A method of etching a device in one embodiment includes providing a silicon carbide substrate, forming a silicon nitride layer on a surface of the silicon carbide substrate, forming a silicon carbide layer on a surface of the silicon nitride layer, forming a silicon dioxide layer on a surface of the silicon carbide layer, forming a photoresist mask on a surface of the silicon dioxide layer, and etching the silicon dioxide layer through the photoresist mask.Type: GrantFiled: December 31, 2007Date of Patent: July 19, 2011Assignee: Robert Bosch GmbHInventor: Gary Yama
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Patent number: 7977390Abstract: A method for etching features in a dielectric layer is provided. A mask is formed over the dielectric layer. A protective silicon-containing coating is formed on exposed surfaces of the mask. The features are etched through the mask and protective silicon-containing coating. The features may be partially etched before the protective silicon-containing coating is formed.Type: GrantFiled: August 22, 2006Date of Patent: July 12, 2011Assignee: Lam Research CorporationInventors: Bing Ji, Erik A. Edelberg, Takumi Yanagawa, Zhisong Huang, Lumin Li