Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.

Abstract: To smooth silicon sliders that have been parted from each other on a wafer by DRIE, an isotropic etch using fluorine either in a gas or in an aqueous solution is performed prior to separating the individual sliders from the wafer.

Abstract: A method for fabricating a semiconductor device includes: providing a substrate structure including a bit line and a capacitor formed apart from each other at a different level; forming first, second, and third insulation layers over the bit line, the second insulation layer being a first etch stop layer; forming a second etch stop layer over a top electrode of the capacitor; forming a fourth insulation layer over the third insulation layer and the second etch stop layer; and performing a plurality of etch steps to expose an upper surface of the bit line and an upper surface of the capacitor.

Abstract: A method of manufacturing a tunable wavelength optical filter. The method includes steps of forming a first sacrificial oxide film for floating a lower mirror on a semiconductor substrate; sequentially laminating conductive silicon films and oxide films for defining a mirror region on the first sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form a lower mirror; sequentially laminating conductive silicon films and oxide films for defining the mirror region on a second sacrificial oxide film in a multi-layer and laminating another conductive silicon film to form an upper mirror and forming an optical tuning space between the lower mirror and the upper mirror and etching the first sacrificial oxide film and the second sacrificial oxide film such that the lower mirror is floated on the semiconductor substrate.

Abstract: A semiconductor device and a method for fabricating the same in which a protective oxide layer is formed on an insulating interlayer gap are disclosed. An example semiconductor device includes a semiconductor substrate having lower structures, an insulating interlayer on the semiconductor substrate to cover the lower structures, and an SiH4-oxide layer on the insulating interlayer. The SiH4-oxide has hydrogen constituents removed by displacement to prevent an amorphous material layer from being formed on the insulating interlayer. The example semiconductor device includes a contact hole in the insulating interlayer and the SiH4-oxide layer for exposing predetermined portions of the lower structures. Additionally, the example semiconductor device includes a contact plug formed inside the contact hole to electrically connect the lower structures with a metal line.

Abstract: A method is provided which includes forming a hardmask feature adjacent to a patterned sacrificial structure of a semiconductor topography, selectively removing the patterned sacrificial structure to expose a lower layer and etching exposed portions of the lower layer in alignment with the hardmask feature. In some embodiments, forming the hardmask feature may include conformably depositing a hardmask material above the patterned sacrificial structure and lower layer as well as blanket etching the hardmask material such that upper surfaces of the patterned sacrificial structure and portions of the lower layer are exposed and portions of the hardmask material remain along sidewalls of the patterned sacrificial structure. The method may be applied to produce an exemplary semiconductor topography including a plurality of gate structures each having a width less than approximately 70 nm, wherein a variation of the widths among the plurality of gate structures is less than approximately 10%.

Abstract: The present invention relates to a self-aligning patterning method which can be used to manufacture a plurality of multi-layer thin film transistors on a substrate. The method comprises firstly forming a patterned mask 20 on the surface of a sacrificial layer 18 which is part of a multi-layer structure 10 which comprises the substrate 12, a conductive layer 14, an insulating layer 16 and the sacrificial layer 18. Unpatterned areas are then etched to remove the corresponding areas of the sacrificial layer, the insulating layer 16 and the conductive layer 14 thereby leaving voids. A layer of dielectric 22 is then deposited over the etched multi-layer structure to at least substantially fill the voids. The deposited dielectric is then etched in order to at least partially expose the sides of the remaining areas 28 of the sacrificial layer. Conductive material 30 is then deposited on the surface of the etched dielectric.

Abstract: An etching method, for etching a silicon nitride film on an underlying silicon oxide film by using a hard mask whose principal component is a silicon oxide, includes a step of etching the hard mask by using the resist film as a mask to form a mask pattern therein; a step of ashing the resist film; a step of oxidizing the hard mask; a main etching step of etching the silicon nitride film by using the patterned hard mask as a mask; and a step of overetching the silicon nitride film at a high selectivity of the silicon nitride film to the silicon oxide film. The main etching step is performed after the step of forming the mask pattern in the hard mask and before the overetching step at a selectivity of the silicon nitride film to the silicon oxide film smaller than that in the overetching step.

Abstract: A method for fabricating a CMOS image sensor forms silicon nitride (SiN) layer on a pad. Microlenses, having a minimum height and footprint according to a desired packing density of the lenses, are fabricated of an oxide film and a nitride film deposited on the silicon nitride. Since the lenses have a low height, a refractive index of the lenses may be improved. A sidewall spacer type inner lens may be additionally formed below a main lens curvature to aid in overcoming problems caused by a single-lens structure.

Abstract: A plasma processing method is conducted while a thickness of a resist film being monitored, thereby preventing the thickness of the resist film from being reduced. The plasma processing method includes steps of supplying a processing gas into an airtight processing chamber, and plasma-processing a target layer formed on an object to be processed by using a resist film as a mask. The method includes a main etching process (first process) of plasma-processing the target layer while the thickness of the resist film being monitored until the reduction rate of the thickness of the resist film reaches a predetermined value, and an over-etching process (second process) of plasma-processing the target layer in a changed process condition in which selectivity against the resist film is higher than in the first process.

Abstract: A semiconductor device may be manufactured by a method that includes forming an etch stop layer on a semiconductor substrate, sequentially forming a first interlayer insulating layer, a first diffusion barrier, a second interlayer insulating layer, and a second diffusion barrier on the etch stop layer, forming a via hole exposing the etch stop layer by etching the second diffusion barrier, the second interlayer insulating layer, the first diffusion barrier, and the first interlayer insulating layer, forming a first trench overlapping the via hole by etching the second diffusion barrier and the second interlayer insulating layer, forming a second trench continuous to the first trench by etching the first diffusion barrier and part of the first interlayer insulating layer, and removing the etch stop layer exposed through the via hole, wherein the first and second trenches are etched under different dry etching conditions.

Abstract: A method to anisotropically etch an oxide/silicide/poly sandwich structure on a silicon wafer substrate in situ, is disclosed, using a single parallel plate plasma reactor chamber and a single inert cathode, with a variable gap between cathode and anode. This method has an oxide etch step and a silicide/poly etch step. The fully etched sandwich structure has a vertical profile at or near 90° from horizontal, with no bowing or notching.

Abstract: A method of removing an oxide layer from an article. The article may be located in a reaction chamber into which an interhalogen compound reactive with the oxide layer is introduced. A temperature of the reaction chamber may be modified so as to remove the oxide layer. The interhalogen compound may form volatile by-product gases upon reaction with the oxide layer. Unreacted interhalogen compound and volatile by-product gases may then be removed from the reaction chamber.

Abstract: A method of etching a sacrificial oxide layer covering an etch-stop silicon nitride underlayer, involves exposing the sacrificial oxide to anhydrous HF at a temperature of less than about 100° C. and/or at vacuum level lower than 40 Torr; and subsequently performing an in-situ vacuum evaporation of etch by-products at a temperature of more than about 100° C. and at vacuum level lower than the 40 Torr without exposure to ambient air.

Abstract: In processing an integrated circuit structure including a contact arrangement that is initially covered by a stop layer, a first plasma is used to etch to form openings through an overall insulation layer covered by a patterned layer of photoresist such that one contact opening is associated with each contact. Stripping of the patterned layer of photoresist and related residues is performed. After stripping, the stop layer is removed from the contacts. In one feature, the stop layer is removed from the contacts by etching the stop layer using a plasma that is generated from a plasma gas input that includes hydrogen and essentially no oxygen. In another feature, the photoresist is stripped after the stop layer is removed. Stripping the patterned layer of photoresist and the related residues is performed, in this case, using a plasma that is formed predominantly including hydrogen without oxygen.

Abstract: Described herein are methods of forming a thin silicon dioxide layer having a thickness of less than eight angstroms on a semiconductor substrate to form the bottom layer of a gate dielectric. A silicon dioxide layer having a thickness of less than eight angstroms may be formed by two different methods. In one method, a sulfuric acid solution is applied to a semiconductor substrate to grow a silicon dioxide layer of less than eight angstroms. The growth of the silicon dioxide layer by the sulfuric acid solution is self-limiting. In another method, a hydrogen peroxide containing solution is applied to a semiconductor substrate for a time sufficient to grow a silicon dioxide layer having a thickness of greater than eight angstroms and then applying an etching solution to etch the silicon dioxide layer down to a thickness of less than eight angstroms.

Abstract: For a surface processing apparatus using a plasma, a mixed gas of a fluorine-containing gas and an oxygen gas is used as an ashing gas. A mixed gas of an oxygen gas and a fluorine-containing gas is introduced as an ashing gas. This allows the following steps to be carried out at the same time: removal of the silicon component left on the mask material surface and the mask material in the area including the cured mask layer and the like; and the removal of the carbon-based, and silicon-based deposits deposited on the inner wall of a vacuum chamber. In addition, the removal of the mask material is performed under low pressure, and in the subsequent step to a step using a mixed gas of a fluorine-containing gas and an oxygen gas, a plasma of only an oxygen gas is used. As a result, it becomes possible to reduce the damages (etching) to the film layer after etching.

Abstract: A method of producing a semiconductor device is disclosed, in which a through hole is formed in the upper surface of a semiconductor substrate from the lower surface thereof, and an opening of a desired size is formed in a desired position on the upper surface of the substrate. A guide that functions as an etching stopper is formed in the semiconductor substrate. An opening having a width W2 is formed in the guide. The opening faces an opening in a mask used in the formation of a through hole, and the width W2 thereof is narrower than a width W4 of the opening in the mask. The direction in which etching progresses is controlled by the opening formed in the guide as etching is conducted from a lower surface of the substrate to an upper surface of the substrate, and thus deviations in the width W1 and position of an opening in the upper surface of the substrate can be controlled.

Abstract: In a first step and a thirst step, etching gases are used which contain fluorocarbon gases having C/F atom number ratios higher than that in a second step. A hole is formed to a midpoint in a silicon oxide film in the first step, the hole is formed until a base SiN film begins to be exposed or immediately before it is exposed in the second step, and overetching is performed in the third step. This enables even a hole having a fine diameter and a high aspect ratio to be formed in an excellent shape.

Abstract: The invention provides a plasma etching method that does not create any difference in profile between sparse and dense portions of the mask pattern in processing a device having a space width equal to or smaller than 100 nm. An added gas having a high C/F ratio such as C4F8 gas capable of increasing the generation of CF2 radicals that may become sidewall protection film components having a small attachment coefficient is added to the etching gas in order to form sidewall protection films on dense pattern portions, and in addition, Xe gas is added in order to suppress dissociation effect by lowering the electron temperature.

Abstract: A cluster tool is provided for the implementing of a clustered and integrated surface pre-cleaning of the surface of semiconductor devices. More particularly, there is provided a cluster tool and a method of utilization thereof in an integrated semiconductor device surface pre-cleaning, which is directed towards a manufacturing aspect in which a chamber for performing a dry processing chemical oxide removal (COR) on the semiconductor device surface is clustered with other tools, such as a metal deposition tool for silicide or contact formation, including the provision of a vacuum transfer module in the cluster tool.

Abstract: Plasma etch processes incorporating helium-based etch chemistries can remove dielectric a semiconductor applications. In particular, high density plasma chemical vapor etch-enhanced (deposition-etch-deposition) gap fill processes incorporating etch chemistries which incorporate helium as the etchant that can effectively fill high aspect ratio gaps while reducing or eliminating dielectric contamination by etchant chemical species.

Abstract: A method for forming a via hole and a trench for a dual damascene interconnection comprises forming a via hole through an inter-metal insulating film to expose a portion of a surface of an etch stop film on a lower metal film, forming a photoresist film on an entire surface of the resultant structure and in the via hole, exposing a top surface and a side surface of the inter-metal insulating film by recessing the photoresist film using a development process for the photoresist film, forming a bottom antireflective coating film on the exposed surfaces of the inter-metal insulating film and the photoresist film, forming a mask pattern on the bottom antireflective coating film, forming a trench by an etching process using the mask pattern as an etch mask, and completely removing the photoresist film within the via hole.

Abstract: A method for etching a deep trench in a substrate. A multi-layer hard mask structure is formed overlying the substrate, which includes a first hard mask layer and at least one second hard mask layer disposed thereon. The first hard mask layer is composed of a first boro-silicate glass (BSG) layer and an overlying first undoped silicon glass (USG) layer and the second is composed of a second BSG layer and an overlying second USG layer. A polysilicon layer is formed overlying the multi-layer hard mask structure and then etched to form an opening therein. The multi-layer hard mask structure and the underlying substrate under the opening are successively etched to simultaneously form the deep trench in the substrate and remove the polysilicon layer. The multi-layer hard mask structure is removed.

Abstract: A method for etching features into a dielectric layer over a substrate and existent below a polymeric hard mask is provided. The substrate is placed in a plasma processing chamber. Mask features are etched into the polymeric hard mask and necks are formed inadvertently. A plasma treatment process performed before the dielectric etch step process can selectively etch away the necks. As a result, neckless features are created into the polymeric hardmask. Features etched into the underneath dielectric layer through the neckless polymeric hard mask have straight profiles.

Abstract: Contact areas comprising doped semiconductor material at the bottom of contact holes are cleaned in a hot hydrogen plasma and exposed in situ during and/or separately from the hot hydrogen clean to a plasma containing the same dopant species as in the semiconductor material so as to partially, completely, or more than completely offset any loss of dopant due to the hot hydrogen clean. A protective conductive layer such as a metal silicide is then formed over the contact area in situ. The resulting integrated circuit has contacts with interfaces such as a silicide interfaces to contact areas having a particularly favorable dopant profile and concentration adjacent the silicide interfaces.

Abstract: An interlevel dielectric layer, such as a silicon oxide layer, is selectively etched using a plasma etch chemistry including a silicon species and a halide species and also preferably a carbon species and an oxygen species. The silicon species can be generated from a silicon compound, such as SixMyHz, where “Si” is silicon, “M” is one or more halogens, “H” is hydrogen and x?1, y?0 and z?0. The carbon species can be generated from a carbon compound, such as C?M?H?, where “C” is carbon, “M” is one or more halogens, “H” is hydrogen, and ??1, ??0 and ??0. The oxygen species can be generated from an oxygen compound, such as O2, which can react with carbon to form a volatile compound.

Abstract: A dry etch process is described for selectively etching silicon nitride from conductive oxide material for use in a semiconductor fabrication process. Adding an oxidant in the etch gas mixture could increase the etch rate for the silicon nitride while reducing the etch rate for the conductive oxide, resulting in improving etch selectivity. The disclosed selective etch process is well suited for ferroelectric memory device fabrication using conductive oxide/ferroelectric interface having silicon nitride as the encapsulated material for the ferroelectric.

Abstract: A method for removing photoresist is described. A substrate having a photoresist to be removed thereon is provided, and then an ashing process is performed to remove most of the photoresist. The substrate is then subjected to a surface treatment that provides sufficient energy for the extra electrons caused by the ashing process to escape from the substrate, and the remaining photoresist and polymer are stripped with stripping solvents after the surface treatment.

Abstract: Methods deposit a film on a substrate disposed in a substrate processing chamber. The substrate has a gap formed between adjacent raised surfaces. Flows of first precursor deposition gases are provided to the substrate processing chamber. A first high-density plasma is formed from the flows of first deposition gases to deposit a first portion of the film over the substrate and within the gap with a first deposition process that has simultaneous deposition and sputtering components until after the gap has closed. A sufficient part of the first portion of the film is etched back to reopen the gap. Flows of second precursor deposition gases are provided to the substrate processing chamber. A second high-density plasma is formed from the flows of second precursor deposition gases to deposit a second portion of the film over the substrate and within the reopened gap with a second deposition process that has simultaneous deposition and sputtering components.

Abstract: A method for SAC etching is provided involving a) etching a Si wafer having a nitride present thereon with a first etching gas containing a first perfluorocarbon and carbon monoxide, and b) etching the resultant Si wafer having an initially etched nitride photoresist thereon with a second etching gas containing a second perfluorocarbon in the substantial absence of carbon monoxide, wherein the etching steps a) and b) are performed at high RF power and low pressure compared to conventional processes to provide higher selectivity etching and a larger process window for SAC etching, as well as the ability to perform SAC etching and island contact etching under the same conditions with high verticality of the island contact and SAC walls.

Abstract: In a method for manufacturing a multi-thickness gate dielectric layer of a semiconductor device, a first dielectric layer is formed on a semiconductor substrate. A second dielectric layer is formed using a different dielectric material from the material constituting the first dielectric layer on the first dielectric layer. A portion of the second dielectric layer is selectively removed so as to selectively expose the first dielectric layer under the second dielectric layer. A portion of the exposed first dielectric layer is selectively removed so as to selectively expose the semiconductor substrate under the exposed first dielectric layer. Thereafter, a third dielectric layer having a thinner thickness than the first dielectric layer is formed on the exposed semiconductor substrate.

Abstract: A substrate (wafer) processing method for producing an ink jet recording head substrate in which the reverse surface thereof, that is, the surface having the larger of the two openings of the ink supply hole, is precisely covered by a protective film to the very edge of the hole, including: a step for forming a protective film on the substrate; a step for etching the surface of the protective film; a step for forming an etching resistant film on the etched surface of the protective film; a step for forming an ink supply hole pattern through the etchant-resistant film and protective film; a step for forming the ink supply hole through the substrate by etching; a step for removing a portion of the protective film left projecting into the ink supply hole while forming the ink supply hole; and a step for removing the etchant-resistant film.

Abstract: A selective dry etch process includes use of an etchant that includes C2HxFy, where x is an integer from three to five, inclusive, where y is an integer from one to three, inclusive, and where x plus y equals six. The etchant etches doped silicon dioxide with selectivity over both undoped silicon dioxide and silicon nitride. Thus, undoped silicon dioxide and silicon nitride may be employed as etch stops in dry etch processes which utilize the C2HxFy-containing etchant. C2HxFy may be employed as either a primary etchant or as an additive to another etchant or etchant mixture.

Abstract: In a plasma processing system, including a plasma processing chamber, a method of optimizing the etch resistance of a substrate material is described. The method includes flowing pre-coat gas mixture into the plasma processing chamber, wherein the pre-coat gas mixture has an affinity for a etchant gas flow mixture; striking a first plasma from the pre-coat gas mixture; and introducing a substrate comprising the substrate material. The method also includes flowing the etchant gas mixture into the plasma processing chamber; striking a second plasma from the etchant gas mixture; and etching the substrate with the second plasma. Wherein the first plasma creates a pre-coat residual on a set of exposed surfaces in the plasma processing chamber, and the etch resistance of the substrate material is maintained.

Abstract: A semiconductor manufacturing process wherein a low-k dielectric layer is plasma etched with selectivity to an overlying mask layer. The etchant gas can be oxygen-free and include a fluorocarbon reactant, a nitrogen reactant and an optional carrier gas, the fluorocarbon reactant and nitrogen reactant being supplied to a chamber of a plasma etch reactor at flow rates such that the fluorocarbon reactant flow rate is less than the nitrogen reactant flow rate. The etch rate of the low-k dielectric layer can be at least 5 times higher than that of a silicon dioxide, silicon nitride, silicon oxynitride or silicon carbide mask layer. The process is useful for etching 0.25 micron and smaller contact or via openings in forming structures such as damascene structures.

Abstract: A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over a second region (e.g., NFET region). A stress layer is over the stress relief layer in the first region and over the devices and substrate/silicide in the second region. The NFET transistor performance is enhanced due to the overall tensile stress in the NFET channel while the degradation in the PFET transistor performance is reduced/eliminated due to the inclusion of the stress relief layer. In a second example embodiment, the stress relief layer is formed over the second region, but not the first region and the stress of the stress layer is reversed.

Abstract: A method for etching features in a silicon oxide based dielectric layer over a substrate, comprising performing an etch cycle. A lag etch partially etching features in the silicon oxide based dielectric layer is performed, comprising providing a lag etchant gas, forming a plasma from the lag etchant gas, and etching the etch layer with the lag etchant gas, so that smaller features are etched slower than wider features. A reverse lag etch further etching the features in the silicon oxide based dielectric layer is performed comprising providing a reverse lag etchant gas, which is different from the lag etchant gas and is more polymerizing than the lag etchant gas, forming a plasma from the reverse lag etchant gas, and etching the silicon oxide based dielectric layer with the plasma formed from the reverse lag etchant gas, so that smaller features are etched faster than wider features.

Abstract: Methods of performing controllable lateral etches into the silicon layer using a plasma-enhanced etch-deposit-etch sequence are disclosed. The first etch step etches into the silicon layer. The deposition step passivates horizontal surfaces, including the bottom of the etched feature. The second etch step increases the lateral undercut, resulting in a low V:L ratio silicon layer etch.

Abstract: A plasma etching is performed on a substrate having a pattern wherein an interval between neighboring openings formed on a resist mask is equal to or less than 200 nm, wherein the etching is performed by converting a processing gas comprising an active species generating gas which includes a compound having carbon and fluorine, and a nonreactive gas which includes xenon gas into a plasma. The nonreactive gas further includes argon gas.

Abstract: Gas switching is used during an etch process to modulate the characteristics of the etch. The etch process comprises a sequence of at least three steps, wherein the sequence is repeated at least once. For example, the first step may result in a high etch rate of oxide (108) while the second step is a polymer coating steps and the third step results in a low etch rate of oxide and high etch rate of another material (114) and/or sputtering.

Abstract: Inwardly-tapered openings are created in an Anti-Reflection Coating layer (ARC layer) provided beneath a patterned photoresist layer. The smaller, bottom width dimensions of the inwardly-tapered openings are used for defining further openings in an interlayer dielectric region (ILD) provided beneath the ARC layer. In one embodiment, the ILD separates an active layers set of an integrated circuit from its first major interconnect layer. Further in one embodiment, a taper-inducing etch recipe is used to create the inwardly-tapered ARC openings, where the etch recipe uses a mixture of CF4 and CHF3 and where the CF4/CHF3 volumetric inflow ratio is substantially less than 5 to 1, and more preferably closer to 1 to 1.

Abstract: Methods for eliminating and/or mitigating bridging and/or leakage caused by the contamination of a dielectric layer with fragments and/or residues of a conductive material are disclosed. The methods involve exposing a semiconductor substrate with a dielectric layer contaminated with fragments and/or residues of conductive materials to one or more conductor and/or dielectric etches. The disclosure by eliminating and/or mitigating metal bridging and/or leakage can provide one or more of the following advantages: high device reliability, decreased manufacturing cost, more efficient metallization, and increased performance.

Abstract: An organic/inorganic hybrid film represented by SiCx?HyOz (x>0, y?0, z>0) is plasma-etched with an etching gas containing fluorine, carbon and nitrogen. During the etching, a carbon component is eliminated from the surface portion of the organic/inorganic hybrid film due to the existence of the nitrogen in the etching gas, to thereby reform the surface portion. The reformed surface portion is nicely plasma-etched with the etching gas containing fluorine and carbon.

Abstract: A process for fabricating a MOSFET device featuring a channel region comprised with a silicon-germanium component is provided. The process features employ an angled ion implantation procedure to place germanium ions in a region of a semiconductor substrate underlying a conductive gate structure. The presence of raised silicon shapes used as a diffusion source for a subsequent heavily doped source/drain region, the presence of a conductive gate structure, and the removal of dummy insulator previously located on the conductive gate structure allow the angled implantation procedure to place germanium ions in a portion of the semiconductor substrate to be used for the MOSFET channel region. An anneal procedure results in the formation of the desired silicon-germanium component in the portion of semiconductor substrate to be used for the MOSFET channel region.

Abstract: Processes, etchants, and apparatus useful for etching an insulating oxide layer of a substrate without damaging underlying nitride features or field oxide regions. The processes exhibit good selectivity to both nitrides and field oxides. Integrated circuits produced utilizing etching processes of the present invention are much less likely to be defective due to photoresist mask misalignment. Etchants used in processes of the present invention comprise a carrier gas, one or more C2+F gases, CH2F2, and a gas selected from the group consisting of CHF3, CF4, and mixtures thereof. The processes can be performed at power levels lower than what is currently utilized in the prior art.

Abstract: A plasma etching method includes the step of performing a plasma etching on a silicon-containing dielectric layer formed on a substrate to be processed by using a plasma, while using an organic layer as a mask. In addition, the plasma is generated from a processing gas at least including a first fluorocarbon gas which is an unsaturated gas; a second fluorocarbon gas which is an aliphatic saturated gas expressed by CmF2m+2 (m=5, 6); and an oxygen gas. Further, a computer-readable storage medium for storing therein a computer executable control program is provided where the control program, when executed, controls a plasma etching apparatus to perform the above plasma etching method.

Abstract: Disclosed is a method of selectively etching nitride in a chemical downstream etching process. The invention begins by placing a wafer having oxide regions and nitride regions in a chamber. Then, the invention performs a chemical downstream etching process using CH2F2 to etch and convert the nitride regions into surface mediated uniform reactive film (SMURF) regions comprising (NH4)2SiF6. This process then rinses the surface of the wafer with water to remove the surface mediated uniform reactive film regions from the wafer, leaving the oxide regions substantially unaffected. The chemical downstream etching process is considered selective because it etches the nitride regions at a higher rate than the oxide regions.

Abstract: A method and system for selectively and uniformly etching a dielectric layer with respect to silicon and polysilicon in a dry plasma etching system are described. The etch chemistry comprises the use of fluorohydrocarbons, such as CH2F2 and CHF3. High etch selectivity and acceptable uniformity can be achieved by selecting a process condition, including the flow rate of CH2F2 and the power coupled to the dry plasma etching system, such that a proper balance of active etching radicals and polymer forming radicals are formed within the etching plasma.

Abstract: To realize etching with a high selection ratio and a high accuracy in fabrication of an LSI, the composition of dissociated species of a reaction gas is accurately controlled when dry-etching a thin film on a semiconductor substrate by causing an inert gas excited to a metastable state in a plasma and a flon gas to interact with each other and selectively obtaining desired dissociated species.