Abstract: A method for fabricating a semiconductor device is provided. The method of fabricating a semiconductor device provides a semiconductor substrate; forming a first insulating layer, a first conductive layer and a chemical mechanical polishing (CMP) stop layer over the semiconductor substrate in sequence; forming openings in the chemical mechanical polishing (CMP) stop layer and the underlying first conductive layer to expose the first insulating layer, thereby leaving a patterned chemical mechanical polishing (CMP) stop layer and a patterned first conductive layer; forming a second insulating layer on the patterned chemical mechanical polishing (CMP) stop layer, filling in the openings; performing a planarization process to remove a portion of the second insulating layer until the patterned chemical mechanical polishing (CMP) stop layer is exposed, thereby leaving a remaining second insulating layer in the openings; removing the patterned chemical mechanical polishing (CMP) stop layer.

Abstract: A plasma etching method and apparatus, a control program and a computer-readable storage medium storing the control program are provided. The method is provided for performing a plasma etching on a silicon oxide film through an amorphous carbon mask, wherein the plasma etching is performed by using an etching gas containing a fluorocarbon gas, an oxygen gas, a helium gas and at least one of an argon gas, a krypton gas and a xenon gas.

Abstract: A method of preventing formation of stringers adjacent a side of a CMOS gate stack during the deposition of mask and poly layers for the formation of a base and emitter of a bi-polar device on a CMOS integrated circuit wafer. The stringers are formed by incomplete removal of a hard mask layer over an emitter poly layer over a nitride mask layer. The method includes overetching the hard mask layer with a first etchant having a higher selectivity for the emitter poly material than for the material of the hard mask, determining an end point for the overetching step by detection of nitride in the etchant and applying a poly etchant that is selective with respect to nitride to remove any residual emitter poly.

Abstract: A pattern forming method includes preparing a target object including silicon with an initial pattern formed thereon and having a first line width; performing a plasma oxidation process on the silicon surface inside a process chamber of a plasma processing apparatus and thereby forming a silicon oxide film on a surface of the initial pattern; and removing the silicon oxide film. The pattern forming method is arranged to repeatedly perform formation of the silicon oxide film and removal of the silicon oxide film so as to form an objective pattern having a second line width finer than the first line width on the target object.

Abstract: In a method for manufacturing a display device having a light emitting element, a first base insulating film, a second base insulating film, a semiconductor layer, and a gate insulating film are formed in this order over a substrate. A gate electrode is formed over the gate insulating film to overlap with at least a part of the semiconductor layer, and a portion to be a pixel portion of the gate insulating film and the second base insulating film is doped with at least one conductive type impurities. An opening portion is formed by selectively etching the gate insulating film and second base insulating film that are each doped with impurities. The first base insulating film is exposed in a bottom face of the opening portion. Subsequently, an insulating film is formed to cover the opening portion, the gate insulating film, and the gate electrode, and a light emitting element is formed over the insulating film to overlap with at least a part of the opening portion.

Abstract: A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.

Abstract: A method for etching a polysilicon gate structure in a plasma etch chamber is provided. The method initiates with defining a pattern protecting a polysilicon film to be etched. Then, a plasma is generated. Next, substantially all of the polysilicon film that is unprotected is etched. Then, a silicon containing gas is introduced and a remainder of the polysilicon film is etched while introducing a silicon containing gas. An etch chamber configured to introduce a silicon containing gas during an etch process is also provided.

Abstract: The invention relates to a method for the selective plasmochemical dry-etching of phosphosilicate glass ((SiO2)xP2O5)y) formed on surfaces of silicon wafers. In this respect, it is the object of the invention to provide a cost-effective, efficient, selective possibility which at least reduces manufacturing losses and with which phosphosilicate glass can be removed from silicon wafers. A procedure is followed in the invention that crystalline silicon wafers, whose surface is provided with phosphosilicate glass, are etched in a selective plasmochemical process. In this connection, a plasma formed using a plasma source and an etching gas are directed at atmospheric pressure to the phosphosilicate glass which can thus be removed.

Abstract: A process for selectively etching a material comprising SiO2 over silicon, the method comprising the steps of: placing a silicon substrate comprising a layer of a material comprising SiO2 within a reactor chamber equipped with an energy source; creating a vacuum within the chamber; introducing into the reactor chamber a reactive gas mixture comprising a fluorine compound, a polymerizable fluorocarbon, and an inert gas, wherein the reactive gas mixture is substantially free of added oxygen; activating the energy source to form a plasma activated reactive etching gas mixture within the chamber; and selectively etching the material comprising SiO2 preferentially to the silicon substrate.

Abstract: Some embodiments of the present invention include apparatuses and methods relating to improved substrate patterning for multi-gate transistors.

Abstract: A difference in etching rate between the coated silicon based insulating film and any of other kinds of silicon-based insulating films is reduced by using nitrogen gas as a part of the etching gas. Therefore, the underlying film may not be exposed to the etching gas for a long time, so that degradation or deterioration of the underlying film can be prevented.

Abstract: This invention relates to a process for selective removal of materials, such as: silicon, molybdenum, tungsten, titanium, zirconium, hafnium, vanadium, tantalum, niobium, boron, phosphorus, germanium, arsenic, and mixtures thereof, from silicon dioxide, silicon nitride, nickel, aluminum, TiNi alloy, photoresist, phosphosilicate glass, boron phosphosilicate glass, polyimides, gold, copper, platinum, chromium, aluminum oxide, silicon carbide and mixtures thereof. The process is related to the important applications in the cleaning or etching process for semiconductor deposition chambers and semiconductor tools, devices in a micro electro mechanical system (MEMS), and ion implantation systems. Methods of forming XeF2 by reacting Xe with a fluorine containing chemical are also provided, where the fluorine containing chemical is selected from the group consisting of F2, NF3, C2F6, CF4, C3F8, SF6, a plasma containing F atoms generated from an upstream plasma generator and mixtures thereof.

Abstract: Some embodiments include methods of recessing multiple materials to a common depth utilizing etchant comprising C4F6 and C4F8. The recessed materials may be within isolation regions, and the recessing may be utilized to form trenches for receiving gatelines. Some embodiments include structures having an island of semiconductor material laterally surrounded by electrically insulative material. Two gatelines extend across the insulative material and across the island of semiconductor material. One of the gatelines is recessed deeper into the electrically insulative material than the other.

Abstract: Embodiments of the invention generally provide a method for depositing films or layers using a UV source during a photoexcitation process. The films are deposited on a substrate and usually contain a material, such as silicon (e.g., epitaxy, crystalline, microcrystalline, polysilicon, or amorphous), silicon oxide, silicon nitride, silicon oxynitride, or other silicon-containing materials. The photoexcitation process may expose the substrate and/or gases to an energy beam or flux prior to, during, or subsequent a deposition process. Therefore, the photoexcitation process may be used to pre-treat or post-treat the substrate or material, to deposit the silicon-containing material, and to enhance chamber cleaning processes.

Abstract: Methods of etching into silicon oxide-containing material with an etching ambient having at least 75 volume percent helium. The etching ambient may also include carbon monoxide, O2 and one or more fluorocarbons. The openings formed in the silicon oxide-containing material may be utilized for fabrication of container capacitors, and such capacitors may be incorporated into DRAM.

Abstract: A method for etching a dielectric layer over a substrate and disposed below a mask is provided. The substrate is placed in a plasma processing chamber. An etchant gas comprising O2 and a sulfur component gas comprising at least one of H2S and a compound containing at least one carbon sulfur bond is provided into the plasma chamber. A plasma is formed from the etchant gas. Features are etched into the etch layer through the photoresist mask with the plasma from the etchant gas.

Abstract: The present invention provides a method for removing sacrificial materials in fabrications of microstructures using a selected spontaneous vapor phase chemical etchants. During the etching process, an amount of the etchant is fed into an etch chamber for removing the sacrificial material. Additional amount of the etchant are fed into the etch chamber according to a detection of an amount or an amount of an etching product so as to maintaining a substantially constant etching rate of the sacrificial materials inside the etch chamber. Accordingly, an etching system is provided for removing the sacrificial materials based on the disclosed etching method.

Abstract: A process for selectively removing photoresist, organic overlayers, and/or polymers/residues from a substrate without altering the surface chemistry and adhesion properties of the underlying substrate layers is provided. Generally, the process includes pretreating the substrate with hydrogen (e.g., by way of a hydrogen-based plasma) prior to deposition of a photoresist layer, and then ashing the substrate with a hydrogen-based plasma to selectively remove the photoresist, organic overlayers, and/or polymers/residues from the substrate during etching, post-etch, rework, etc. The hydrogen-based ashing process of the invention may be used post-etch to remove the residue photoresist, or may be used in a rework stripping process to remove misaligned patterns. The hydrogen-based ashing process following the initial hydrogen surface pretreatment substantially reduces surface chemistry poisoning, while retaining adequate adhesion properties following ashing.

Abstract: In a film formation method for a semiconductor process, a target substrate having a target surface with a natural oxide film is loaded into a reaction chamber, while setting the reaction chamber at a load temperature lower than a threshold temperature at which the natural oxide film starts being stabilized. Then, the natural oxide film is removed by etching, while supplying an etching gas containing chlorine without containing fluorine, and setting the reaction chamber at an etching pressure and an etching temperature lower than the threshold temperature. Then, the reaction chamber is purged. Then, a thin film is formed on the target surface by CVD, while supplying a film formation gas, and setting the reaction chamber at a film formation temperature.

Abstract: A method of smoothening a dielectric layer. First, a substrate is provided. Next, a dielectric layer is formed on the semiconductor substrate. Finally, the dielectric layer is smoothened by a plasma treatment employing a silane based gas and a nitrogen based gas.

Abstract: Provided herein are hardmask compositions that include an organosilane polymer prepared by the reaction of one or more compounds of Formula (I) Si(OR1)(OR2)(OR3)R4 wherein R1, R2 and R3 may each independently be alkyl acetoxy or oxime; and R4 may be hydrogen, alkyl, aryl or arylalkyl; and wherein the organosilane polymer has a polydispersity in a range of about 1.1 to about 2.

Abstract: A film is deposited on a substrate disposed in a substrate processing chamber. The substrate has a trench formed between adjacent raised surfaces. A first portion of the film is deposited over the substrate from a first gaseous mixture flowed into the process chamber by chemical-vapor deposition. Thereafter, the first portion is etched by flowing an etchant gas having a halogen precursor, a hydrogen precursor, and an oxygen precursor into the process chamber. Thereafter, a second portion of the film is deposited over the substrate from a second gaseous mixture flowed into the processing chamber by chemical-vapor deposition.

Abstract: A method for clearing native oxide is described. A substrate is provided, including an exposed portion whereon a native oxide layer has been formed. A clearing process is performed to the substrate using nitrogen trifluoride (NF3) and ammonia (NH3) as a reactant gas, wherein the volumetric flow rate of NF3 is greater than that of NH3.

Abstract: A semiconductor device having a crystalline semiconductor film with production of a cavity suppressed and a manufacturing method thereof A manufacturing method of a semiconductor device according to the invention comprises the steps of forming an amorphous silicon film on a substrate having an insulating surface, adding a metal element such as Ni for promoting crystallization to the amorphous silicon film, applying heat treatment to crystallize the amorphous silicon film, so that a crystalline silicon film is formed on the substrate, removing a silicon oxide film formed on the surface of the crystalline silicon film due to the heat treatment by a solution containing organic solvent and fluoride, and irradiating laser light or strong light to the crystalline silicon film.

Abstract: A method of forming a semiconductor structure comprises providing a semiconductor structure comprising a layer of a dielectric material provided over an electrically conductive feature. An opening is formed in the layer of dielectric material. The opening is located over the electrically conductive feature and has a first lateral dimension. A cavity is formed in the electrically conductive feature. The cavity has a second lateral dimension being greater than the first lateral dimension. The cavity and the opening are filled with an electrically conductive material.

Abstract: A semiconductor device manufacturing method includes a plasma etching process for selectively plasma etching a silicon nitride film against a silicon oxide film formed under the silicon nitride film in a substrate to be processed. The plasma etching process uses an etching gas including a CmFn gas (m, n represent integers of 1 or greater) added to a gaseous mixture of a CHxFy gas (x, y represent integers of 1 or greater) and O2 gas, wherein the flow rate of the CmFn gas is not greater than 10% of that of the O2 gas. The etching gas may further include a rare gas.

Abstract: A two-step method for etching a fuse window on a semiconductor substrate is provided. A semiconductor substrate having thereon a fuse interconnect-wire is formed in a dielectric film stack. The dielectric film stack includes a target dielectric layer overlying said fuse interconnect-wire, an intermediate dielectric layer and a passivation layer. A photoresist layer is formed on the passivation layer with an opening that defines said fuse window. A first dry etching process is performed to non-selectively etch the passivation layer and the intermediate dielectric layer through the opening thereby exposing the target dielectric layer. The thickness of the target dielectric layer after the first dry etching process is then measured. An APC-controlled second dry etching process is performed to etch a portion of the exposed target dielectric layer, thereby reliably forming the fuse window.

Abstract: A method for etching doughnut-type glass substrates, which comprises laminating a plurality of doughnut-type glass substrates each having a circular hole at its center so that the circular holes form a cylindrical hole, and applying an etching treatment to inner peripheral edge surfaces of the plurality of the laminated doughnut-type glass substrates all at once by means of an etching liquid or an etching gas, wherein the etching liquid or the etching gas is supplied from one end of the cylindrical hole, made to flow in the cylindrical hole, and discharged from the other end of the cylindrical hole so that it is not in contact with exposed main surfaces of the doughnut-type glass substrates at both ends of the laminate consisting of the doughnut-type glass substrates.

Abstract: The invention includes etching and contact opening forming methods. In one implementation, a plasma etching method includes providing a bottom powered plasma chamber that includes a plasma generating electrode powerable at different first and second frequencies, with the first frequency being lower than the second frequency. A substrate is positioned over the electrode. A plasma is generated over the substrate with the electrode from a first applied power at the first frequency and a second applied power at the second frequency. A ratio of the first applied power to the second applied power is from 0 to 0.25 or at least 6.0. Material is etched from the substrate with the plasma.

Abstract: A method for fabricating a semiconductor device includes forming an insulation layer over a substrate, etching the insulation layer using a hard mask pattern to form a contact hole, filling the contact hole with a conductive layer, etching the conductive layer to form a plug in the contact hole, removing the remaining hard mask pattern to expose an upper portion of the plug and have the upper portion protrude above the insulation layer, and forming a metal line over the protruding plug and around the upper portion of the plug.

Abstract: A silicon dioxide film removing method is capable of removing a silicon dioxide film, such as a natural oxide film or a chemical oxide film, at a temperature considerably higher than a room temperature. The silicon dioxide film removing method of removing a silicon dioxide film formed on a workpiece in a processing vessel 18 that can be evacuated uses a mixed gas containing HF gas and NH3 gas for removing the silicon dioxide film. The silicon dioxide film can be efficiently removed from the surface of the workpiece by using the mixed gas containing HF gas and NH3 gas.

Abstract: A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

Abstract: A process for etching a insulating layer to produce an opening having an aspect ratio of at least 15:1 by supplying a first gaseous etchant having at least fifty (50) percent He to a plasma etch reactor, and exposing the insulating layer to a plasma of the first gaseous etchant. Use of the first gaseous etchant reduces the occurrence of twisting in openings in insulating layers having an aspect ratio of at least 15:1.

Abstract: A plasma etch process for etching a dielectric material employing two primary etchants at low flows and pressures, and a relatively low temperature environment within the etch chamber. The two primary etchant gases are CHF3 and CH2F2, delivered at flow rates on the order of between about 10 sccm and 40 sccm for CHF3 and between about 10 sccm and 40 sccm for CH2F2. Small quantities, on the order of 10 sccm or less, of other gases such as C2HF5 and CF4 may be added.

Abstract: A layer structure and process for providing sublithographic structures are provided. A first auxiliary layer is formed over a surface of a carrier layer. A lithographically patterned second auxiliary layer structure is formed on a surface of the first auxiliary layer. The first auxiliary layer is anisotropically etched using the patterned second auxiliary layer structure as mask to form an anisotropically patterned first auxiliary layer structure. The anisotropically patterned first auxiliary layer structure is isotropically etched back using the patterned second auxiliary layer structure to remove subsections below the second auxiliary layer structure and to form an isotropically patterned first auxiliary layer structure. A mask layer is formed over the carrier layer including the subsections beneath the second auxiliary layer structure and is anisotropically etched down to the carrier layer to form the sublithographic structures.

Abstract: Methods of filling trenches/gaps defined by circuit elements on an integrated circuit substrate are provided. The methods include forming a first high-density plasma layer on an integrated circuit substrate including at least one trench thereon using a first reaction gas. The first high-density plasma layer is etched using an etch gas including nitrogen fluoride gas (NF3). A second high-density plasma layer is formed on the etched first high-density plasma layer using a second reaction gas including nitrogen fluoride.

Abstract: The present invention generally comprises a method and apparatus for supplemental pumping, gas feed, and/or RF current for a process. When depositing amorphous silicon, the amount of process gases, RF current, and vacuum may be less than the amount of process gases, RF current, and vacuum necessary to deposit microcrystalline silicon. When a single chamber is used to deposit both amorphous and microcrystalline silicon, coupling a supplemental power supply, a supplemental gas source, and a supplemental vacuum pump to the chamber may be beneficial. The supplemental power supply, vacuum pump, and gas source, may be coupled with the chamber when the microcrystalline silicon is deposited and uncoupled when amorphous silicon is deposited. In a cluster tool arrangement, the supplemental power supply, vacuum pump, and gas source may serve multiple chambers that each deposit both amorphous and microcrystalline silicon.

Abstract: A method is disclosed for applying a plasma etch process to facet a masking layer in a semiconductor device by creating sloped surfaces in the masking layer. The masking layer is plasma etched with a plasma that has a high sputter etch component. The plasma etch process removes material from vertical edges of the masking layer to form a sloped surface at each vertical edge of the masking layer. A layer of conductive material is then applied to the masking layer. When the layer of conductive material is subsequently removed by an overetch process the sloped profile of the masking layer facilitates the removal of stringers of conductive material without using an excessively lengthy overetch.

Abstract: Example embodiments of the present invention relate to an etching solution, a method of forming a pattern using the same, a method of manufacturing a multiple gate oxide layer using the same and a method of manufacturing a flash memory device using the same. Other example embodiments of the present invention relate to an etching solution having an etching selectivity between a polysilicon layer and an oxide layer, a method of forming a pattern using an etching solution using the same, a method of manufacturing a multiple gate oxide layer using the same, and a method of manufacturing a flash memory device using the same. An etching solution including hydrogen peroxide (H2O2) and ammonium hydroxide (NH4OH) by a volume ratio of about 1:2 to about 1:10 mixed in water. In a method of forming a pattern and methods of manufacturing a multiple gate oxide layer and a flash memory device, a polysilicon layer may be formed on a substrate.

Abstract: A method of forming a contact plug in a semiconductor device includes the steps of forming a plurality of select lines and a plurality of word lines on a semiconductor substrate; forming a first etching stop layer on the select lines and the word lines; forming a second etching stop layer on the first etching stop layer; forming an insulating layer on the second etching stop layer; removing the insulating layer placed between the select lines, the second etching stop layer and the first etching stop layer to form a contact hole through which a portion of the semiconductor substrate is exposed; and filling the contact hole with conductive material to form a contact plug, and so the nitride layer is thinly formed and the high dielectric layer is then formed to form the etching stop layer. Due to the above, a layer stress caused by the nitride layer can be minimized, and it is possible to resolve a problem of exposing the semiconductor substrate caused by a damage of the etching stop layer.

Abstract: A method of forming a first hard mask pattern including a plurality of first line patterns formed on the etch target layer in a first direction and having a first pitch. A third layer is formed on sidewalls and an upper surface of the first hard mask pattern, such that the third layer includes a top surface having a recess formed between two adjacent first line patterns. A second hard mask pattern including a plurality of second line patterns each extending in the first direction within the recess is formed. Then, the third layer is anisotropically etched to selectively expose an etch target layer between the first line patterns and the second line patterns. Then, the etch target layer is anisotropically etched using the first hard mask pattern and the second hard mask pattern as an etch mask.

Abstract: Methods for opening a hard mask and a silicon-on-insulator substrate in a single process chamber are disclosed. In one embodiment, the method includes patterning a photoresist over a stack including an anti-reflective coating (ARC) layer, a silicon dioxide (SiO2) based hard mask layer, a silicon nitride pad layer, a silicon dioxide (SiO2) pad layer and the SOI substrate, wherein the SOI substrate includes a silicon-on-insulator layer and a buried silicon dioxide (SiO2) layer; and in a single process chamber: opening the ARC layer; etching the silicon dioxide (SiO2) based hard mask layer; etching the silicon nitride pad layer; etching the silicon dioxide (SiO2) pad layer; and etching the SOI substrate. Etching all layers in a single chamber reduces the turn-around-time, lowers the process cost, facilitates process control and/or improve a trench profile.

Abstract: A method for forming, in a semiconductor substrate, wells and/or trenches having different destinations, including the steps of at least partly simultaneously etching cavities according to the pattern of the trenches and/or wells; closing the openings of the cavities with at least one first non-conformal thick layer, and selectively opening the first thick layer according to the subsequent processings.

Abstract: Methods for enhancing trench capacitance and a trench capacitor so formed are disclosed. In one embodiment a method includes forming a first portion of a trench; depositing a dielectric layer in the first portion; performing a reactive ion etching including a first stage to etch the dielectric layer and form a micro-mask on a bottom surface of the first portion of the trench and a second stage to form a second portion of the trench having a rough sidewall; depositing a node dielectric; and filling the trench with a conductor. The rough sidewall enhances trench capacitance without increasing processing complexity or cost.

Abstract: A plasma etching method for performing an etching process for forming on an insulating film formed on a substrate a hole shape having a ratio of depth to opening width of more than 20. The hole shape is formed on the insulating film by converting processing gas containing at least C4F6 gas and C6F6 gas into a plasma. A flow rate ratio of the C4F6 gas to the C6F6 gas (C4F6 gas flow rate/C6F6 gas flow rate) ranges from 2 to 11.

Abstract: A method and system for treating a dielectric film includes exposing at least one surface of the dielectric film to a CxHy containing material, wherein x and y are each integers greater than or equal to a value of unity. The dielectric film can include a low dielectric constant film with or without pores having an etch feature formed therein following dry etch processing. As a result of the etch processing or ashing, exposed surfaces in the feature formed in the dielectric film can become damaged, or activated, leading to retention of contaminants, absorption of moisture, increase in dielectric constant, etc. Damaged surfaces, such as these, are treated by performing at least one of healing these surfaces to, for example, restore the dielectric constant (i.e., decrease the dielectric constant) and cleaning these surfaces to remove contaminants, moisture, or residue.

Abstract: A salicide process contains providing a silicon substrate that comprises at least a predetermined salicide region, performing a cluster ion implantation process to form an amorphized layer in the predetermined salicide region of the silicon substrate near, forming a metal layer on the surface of the amorphized layer, and reacting the metal layer with the amorphized layer to form a silicide layer on the surface of the silicon substrate.

Abstract: In a method of fabricating a semiconductor optical device, insulating structures for an alignment mark for use in electron beam exposure are formed on a primary surface of a first group III-V semiconductor region. After forming the insulating structures, a second group III-V semiconductor region is grown on the first group III-V semiconductor region to form an epitaxial wafer. The height of the insulating structures is larger than thickness of the second group III-V semiconductor region. After forming the second group III-V semiconductor region, alignment for the electron beam exposure is performed. After the alignment, a resist is exposed to an electron beam to form a resist mask. The resist mask has a pattern for a diffraction grating, and the resist is on the epitaxial wafer.

Abstract: A method for forming fine patterns of a semiconductor device is disclosed. The method includes forming an etch film on a substrate, forming a protection film on the etch film, forming a hard mask layer on the protection film, and forming a plurality of first mask patterns characterized by a first pitch on the hard mask layer. The method further comprises forming a plurality of second mask patterns, forming hard mask patterns exposing portions of the protection film by etching the hard mask layer using the first and second mask patterns as an etch mask, and removing the first and second mask patterns. The method still further comprises exposing portions of the etch film and forming a plurality of fine patterns characterized by a second pitch equal to half of the first pitch by etching the etch film using at least the hard mask patterns as an etch mask.

Abstract: A process of etching openings in a dielectric layer includes supporting a semiconductor substrate in a plasma etch reactor, the substrate having a dielectric layer and a patterned photoresist and/or hardmask layer above the dielectric layer; supplying to the plasma etch reactor an etchant gas comprising (a) a fluorocarbon gas (CxFyHz, where x?1, y?1, and z?0), (b) a silane-containing gas, hydrogen or a hydrocarbon gas (CxHy, where x?1 and y?4), (c) an optional oxygen-containing gas, and (d) an optional inert gas, wherein the flow rate ratio of the silane-containing gas to fluorocarbon gas is less than or equal to 0.1, or the flow rate ratio of the hydrogen or hydrocarbon gas to fluorocarbon gas is less than or equal to 0.5; energizing the etchant gas into a plasma; and plasma etching openings in the dielectric layer with enhanced photoresist/hardmask to dielectric layer selectivity and/or minimal photoresist distortion or striation.