Using Specified Electrode/susceptor Configuration (e.g., Of Multiple Substrates Using Barrel-type Susceptor, Planar Reactor Configuration, Etc.) To Generate Plasma Patents (Class 438/729)
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Patent number: 6165907Abstract: A plasma etching method includes the steps of forming an etching mask on a work piece, forming a patterned film, made of a material having an etching rate of 80% or more to 120% or less based on an etching rate for the work piece, on the work piece having the etching mask thereon, and etching the work piece and the patterned film formed thereon at the same time by use of a reactive gas plasma, wherein the film is formed with such a thickness that the thickness of a remaining portion of the film is equal to zero or more after the work piece is etched to a desired depth.Type: GrantFiled: May 2, 1997Date of Patent: December 26, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Ikuo Yoneda, Hideki Kanai, Shinichi Ito
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Patent number: 6165910Abstract: In a plasma processing chamber, a method for etching through a selected portion of an oxide layer of a wafer's layer stack to create a self-aligned contact opening is described. The wafer stack includes a substrate, a polysilicon layer disposed above the substrate, a nitride layer disposed above said polysilicon layer and the oxide layer disposed above the nitride layer. The method for etching includes etching through the oxide layer of the layer stack with a chemistry and a set of process parameters. The chemistry essentially includes C.sub.2 HF.sub.5 and CH.sub.2 F.sub.2 and the set of process parameters facilitate etching through the oxide layer without creating a spiked etch and etching the oxide layer through to the substrate without substantially damaging the nitride layer.Type: GrantFiled: December 29, 1997Date of Patent: December 26, 2000Assignee: Lam Research CorporationInventors: Janet M. Flanner, Linda N. Marquez, Joel M. Cook, Ian J. Morey
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Patent number: 6156629Abstract: A method of etching polysilicon using an oxide hard mask using a three step etch process. Steps one and two are performed insitu in a high density plasma (e.g., TCP--transformer coupled plasma) oxide etcher. Step 3, the polysilicon etch is performed in a different etcher (e.g., poly RIE etcher). A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30.Type: GrantFiled: October 1, 1998Date of Patent: December 5, 2000Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Hun-Jan Tao, Yuan-Chang Huang
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Patent number: 6156667Abstract: The reliability of a plasma processing chamber has been increased using a heat moderating material to facilitate controlling heat removal from dielectric parts of the plasma chamber. The heat moderating material performs at least one of the functions: moderating heat transfer rate and functioning as a heat spreader. The heat moderating material allows removal of heat from the dielectric so that the dielectric maintains temperatures that result in negligible corrosion to the dielectric and the dielectric maintains temperature gradients that minimize thermal stress induced breakage of the dielectric.Type: GrantFiled: January 24, 2000Date of Patent: December 5, 2000Assignee: Litmas, Inc.Inventor: Russell F. Jewett
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Patent number: 6151532Abstract: The invention provides a method for predicting a process surface profile that a given plasma process will create on a process substrate. The prediction is based on a test surface profile, the experimental outcome of a test process which is in general different from the plasma process of interest. In another aspect, the invention provides a technique for defining a plasma process that will produce a desired surface profile. Thus, in related aspects, the invention also provides apparatus for predicting a process surface profile and determining process values, a method of configuring a plasma reactor, a method of making semiconductor devices requiring limited empirical calibration, and a device made according to the method.Type: GrantFiled: March 3, 1998Date of Patent: November 21, 2000Assignee: Lam Research CorporationInventors: Maria E. Barone, Richard A. Gottscho, Vahid Vahedi
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Patent number: 6136720Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.Type: GrantFiled: February 29, 2000Date of Patent: October 24, 2000Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, Guy T. Blalock
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Patent number: 6133153Abstract: A plasma, formed from a mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2, is used to etch a self-aligned contact, the self-aligned contact being an opening in the oxide layer, the opening being aligned with an opening in an underlying nitride layer and extending to a substrate underlying the nitride. The mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2 provides a high ratio of oxide etch rate to nitride etch rate so that the etching is completed without substantially damaging the nitride layer. For thicker oxide layers a preliminary etch step using C.sub.2 F.sub.6 and C.sub.2 HF.sub.5 may be performed prior to using the mixture of C.sub.4 F.sub.8 and CH.sub.2 F.sub.2.Type: GrantFiled: March 30, 1998Date of Patent: October 17, 2000Assignee: Lam Research CorporationInventors: Linda N. Marquez, Janet M. Flanner
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Patent number: 6127275Abstract: A process for fabricating a product 28, 119. The process comprises the steps of subjecting a substrate to a composition of entities, at least one of the entities emanating from a species generated by a gaseous discharge excited by a high frequency field in which the vector sum of phase and anti-phase capacitive coupled voltages from the inductive coupling structure substantially balances.Type: GrantFiled: November 30, 1999Date of Patent: October 3, 2000Assignee: Daniel L. FlammInventor: Daniel L. Flamm
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Patent number: 6126779Abstract: A plasma enhanced gas reactor including a reaction chamber having a pair of field-enhancing electrodes each of which has an axial passage through it by one of which a reactant gas is admitted to the reaction chamber, and by the other of which reaction products are removed from the reaction chamber.Type: GrantFiled: November 7, 1997Date of Patent: October 3, 2000Assignee: AEA Technology PLCInventors: Robert Frew Gillespie, Stephen Ivor Hall, David Raybone, Fiona Winterbottom
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Patent number: 6120640Abstract: A plasma etch reactor having interior surfaces facing the plasma composed of boron carbide, preferably principally composed of B.sub.4 C. The boron carbide may be a bulk sintered body or may be a layer of boron carbide coated on a chamber part. The boron carbide coating may be applied by thermal spraying, such as plasma spraying, by chemical vapor deposition, or by other layer forming technique such as a surface converting reaction. The boron carbide is highly resistant to high-density plasma etchants such as BCl.sub.3. The plasma sprayed coating is advantageously applied to only a portion of an anodized aluminum wall. The boron carbide may be sprayed over the exposed portion of the aluminum over which the anodization has been removed. A band of the aluminum substrate at the transition between the anodization and the boron carbide is roughened prior to anodization so that the boron carbide sticks to the correspondingly roughened surface of the anodization.Type: GrantFiled: December 19, 1996Date of Patent: September 19, 2000Assignee: Applied Materials, Inc.Inventors: Hong Shih, Nianci Han, Steve S. Y. Mak, Gerald Zheyao Yin
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Patent number: 6117349Abstract: A composite shadow ring for use in a plasma etch chamber that has a longer service life and can be readily replaced at a lower cost and a method for using such ring are disclosed. The composite shadow ring is constructed by a larger outer ring and a smaller inner ring which may be fabricated of quartz. The smaller inner ring has an upper planar surface for partially supporting an edge of an wafer and for exposing substantially to the gas plasma in the etch chamber. When the upper planar surface of the smaller inner ring is corroded by the gas plasma, the inner ring may be turned upside-down and reused, or when both sides have been corroded it can be readily replaced at a low cost without replacing the more expensive outer ring. The present invention composite shadow ring therefore presents a substantially lower cost shadow ring for use in an etching process than that possible with the conventional quartz shadow rings.Type: GrantFiled: August 28, 1998Date of Patent: September 12, 2000Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu Chih Huang, Cherng Chang Tsuei, Shuan Yu Chang
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Patent number: 6112696Abstract: A constriction in the exhaust side of a discharge chamber containing oxygen isolates the oxygen supply from the rest of the system. A constriction of equal size or larger is used in the supply of another gas, thereby enabling mixtures of oxygen and other gases to be used in a downstream plasma system. In one embodiment of the invention, the gases are dissociated separately and then combined in a mixing chamber. In another embodiment, oxygen is dissociated and then a lighter gas is added and the mixture is dissociated. In a preferred embodiment of the invention, the lighter gas is selected from the group consisting of water vapor and nitrogen.Type: GrantFiled: February 17, 1998Date of Patent: September 5, 2000Assignee: Dry Plasma Systems, Inc.Inventor: Georges J. Gorin
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Patent number: 6114252Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.Type: GrantFiled: November 5, 1999Date of Patent: September 5, 2000Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, Guy T. Blalock
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Patent number: 6101970Abstract: An inductively coupled type dry etching apparatus has an RF antenna disposed on a dielectric wall forming the ceiling of a process chamber. The process chamber is divided into a plasma generating space and a processing space by the partition of an intermediate electrode. A susceptor is arranged in the processing space, for mounting a semiconductor wafer thereon. The partition has openings for the plasma generating space and the processing space to communicate with each other. The partition is formed of a plurality of conductive beams radially arranged. The conductive beams extend in directions perpendicular to the direction of an electric field generated by the RF antenna, and have warps to absorb thermal stress.Type: GrantFiled: September 29, 1998Date of Patent: August 15, 2000Assignees: Tokyo Electron Yamanashi Limited, Japan Science and Technology CorporationInventor: Chishio Koshimizu
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Patent number: 6093457Abstract: A plasma processing method includes controlling a pressure of an interior of a vacuum chamber to a specified pressure by exhausting the interior of the vacuum chamber while supplying gas into the interior of vacuum chamber. While the pressure of the interior of the vacuum chamber is being controlled, high-frequency power is supplied to one end of a first conductor which is opened at another end, and which is configured as a vortex. Also, grounding one end of a second conductor which is opened at another end and which is configured as a vortex. Finally, electromagnetic waves from the first conductor and the second conductor radiate into the vacuum chamber, generating plasma in the vacuum chamber and processing a substrate placed on an electrode within the vacuum chamber.Type: GrantFiled: March 26, 1998Date of Patent: July 25, 2000Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tomohiro Okumura, Ichiro Nakayama
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Patent number: 6090303Abstract: In an apparatus for producing an electromagnetically coupled planar plasma comprising a chamber having a dielectric shield in a wall thereof and a planar coil outside of said chamber and adjacent to said window coupled to a radio frequency source, the improvement whereby a scavenger for fluorine is mounted in or added to said chamber. When a silicon oxide is etched with a plasma of a fluorohydrocarbon gas, the fluorine scavenger reduces the free fluorine radicals, thereby improving the selectivity and anisotropy of etching and improving the etch rate while reducing particle formation.Type: GrantFiled: December 5, 1996Date of Patent: July 18, 2000Assignee: Applied Materials, Inc.Inventors: Kenneth S. Collins, Jeffrey Marks
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Patent number: 6080676Abstract: A dry etch process is presented wherein a semiconductor substrate is introduced into a reaction chamber between a first electrode and a second electrode. The semiconductor substrate may be positioned on the first electrode. A main flow of gas that includes an argon flow at an argon flow rate and a fluorocarbon flow at a fluorocarbon flow rate is established into the reaction chamber. RF power at a low frequency may then be applied to the first electrode for creating a fluorine-deficient plasma. An oxide layer arranged above the semiconductor substrate is exposed to the fluorine-deficient plasma for etching, in a single step, a portion of the oxide layer.Type: GrantFiled: September 17, 1998Date of Patent: June 27, 2000Assignee: Advanced Micro Devices, Inc.Inventors: Thien T. Nguyen, Mark I. Gardner, Charles E. May
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Patent number: 6076481Abstract: One or more mismatching portions in which a characteristic impedance of a high frequency transmission cable of a cathode electrode is changed in a traveling direction of an incident wave of the high frequency are provided on the cathode electrode for use in plasma processing, whereby the plasma processing can form a high-quality deposited film having an extremely uniform film thickness and a homogeneous film quality on a substrate at high speed, can effectively form a semiconductor device, can also form the high-quality deposited film having the extremely uniform film thickness and the homogeneous film quality in the axial direction and the circumferential direction of the cylindrical substrate on the surfaces of a plurality of cylindrical substrates at high speed, and can effectively form the semiconductor device.Type: GrantFiled: April 1, 1997Date of Patent: June 20, 2000Assignee: Canon Kabushiki KaishaInventors: Atsushi Yamagami, Satoshi Takaki
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Patent number: 6078035Abstract: Microwave radiation, perhaps with microwave absorbing materials, is utilized to provide heating of partially formed integrated circuits in a variety of circumstances.Type: GrantFiled: December 22, 1995Date of Patent: June 20, 2000Assignee: Lucent Technologies Inc.Inventors: Sailesh Chittipeddi, Stephen Knight
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Patent number: 6074953Abstract: Plasma processing tools, dual-source plasma etchers, and etching methods are described. In one embodiment, a processing chamber is provided having an interior base and an interior sidewall joined with the base. A generally planar inductive source is mounted proximate the chamber. A dielectric liner is disposed within the chamber over the interior sidewall with the liner being received over less than an entirety of the interior sidewall. In a preferred embodiment, the interior sidewall has a groundable portion and the dielectric liner has a passageway positioned to expose the groundable interior sidewall portion. Subsequently, a plasma developed within the chamber is disposed along a grounding path which extends to the exposed interior sidewall. In another preferred embodiment, the dielectric liner is removably mounted within the processing chamber.Type: GrantFiled: August 28, 1998Date of Patent: June 13, 2000Assignee: Micron Technology, Inc.Inventors: Kevin G. Donohoe, Guy T. Blalock
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Patent number: 6069088Abstract: The present invention relates to a method for prolonging life time of a dry etching chamber. A neck portion of the dry etching chamber, according to the present invention, is divided three sections, namely a first section, a second section and a third section in sequence from top of the neck portion to bottom thereof and each section has the same area. A first phase of a two-phase connection method, according to the present invention, then proceeds as the following. The first section is surrounded by an electrode coil connected to a rf power and the second section is surrounded by an electrode coil connected to the ground, not touching the electrode coil connected to the rf power, so that a plasma field within the dry etching chamber can be produced to perform a dry etching. The dry etching can be applied in production line until before life time of the first section comes to an end, i.e. about 95 % of life time of the dry etching chamber disclosed in prior art.Type: GrantFiled: March 11, 1999Date of Patent: May 30, 2000Assignee: Mosel Vitelic IncorporatedInventors: Wen-Peng Chiang, Wen-Pin Hsieh
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Patent number: 6056848Abstract: A plasma reactor and methods for processing semiconductor substrates are described. An induction coil inductively couples power into the reactor to produce a plasma. A thin electrostatic shield is interposed between the induction coil and plasma to reduce capacitive coupling. The shield is electromagnetically thin such that inductive power passes through the shield to sustain the plasma while capacitive coupling is substantially attenuated. Reducing capacitive coupling reduces modulation of the plasma potential relative to the substrate and allows for more controllable processing.Type: GrantFiled: September 10, 1997Date of Patent: May 2, 2000Assignee: CTP, Inc.Inventor: Jean-Fran.cedilla.ois Daviet
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Patent number: 6051151Abstract: An apparatus and method of producing a negative ion plasma for use in manufacturing of microelectronic devices, particularly etching of microelectronic patterns in semiconductor wafers. A negative ion plasma is produced from a hot electron plasma formed by a RF or UHF plasma source. The negative ion plasma includes positive ions, negative ions and relatively cold electrons, such electrons having an effective electron temperature or average energies less than that for maintaining the plasma. The fields producing the hot plasma are isolated from the negative ion plasma in a cold plasma region by a magnetic filter. The magnetic filter confines the plasmas to provide plasma uniformity at a work piece being etched by the negative ion plasma. The magnetic filter further prevents hot electrons originating in the hot electron plasma from diffusing into the negative ion plasma, while allowing positive ions and cold electrons to diffuse from the hot plasma to the negative ion plasma.Type: GrantFiled: November 12, 1997Date of Patent: April 18, 2000Assignee: International Business Machines CorporationInventors: John H. Keller, Dennis K. Coultas
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Patent number: 6036878Abstract: The present invention is embodied in a method of operating an inductively coupled plasma reactor for processing a semiconductor wafer, the reactor including a vacuum chamber for containing the wafer, a process gas source, a semiconductor window electrode facing an interior portion of the chamber, an inductive power radiator on an exterior side of the semiconductor window electrode, the inductive field having a skin depth generally decreasing with the frequency of the RF inductive field and with the density of the plasma in the chamber and generally increasing with the pressure inside the vacuum chamber, the inductive coupling of the RF field tending to approach extinguishment as the skin depth approaches the spacing between the wafer and the window electrode, a method for maintaining an intermediate plasma density inside the chamber without extinguishing the inductive coupling of the RF field, the method including operating the reactor at a selected flow rate of the process gas, a selected chamber pressure anType: GrantFiled: February 13, 1998Date of Patent: March 14, 2000Assignee: Applied Materials, Inc.Inventor: Kenneth Collins
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Patent number: 6022484Abstract: A semiconductor processing station which utilizes a processing head and processing base which are complementary to enclose a processing chamber. The processing head shown has a rotor with two portions both of which rotate. The rotor has axial movable portions which include a piece holder. The piece holder supports a wafer or other semiconductor piece being processed. The piece holder can be axially extended and retracted relative to a thin membrane which acts as a cover to prevent chemicals from reaching the back side of the wafer during processing.Type: GrantFiled: March 23, 1998Date of Patent: February 8, 2000Assignee: Semitool, Inc.Inventors: Martin C. Bleck, Timothy J. Reardon, Eric J. Bergman
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Patent number: 6017825Abstract: A method in a plasma processing system having a top electrode and a bottom electrode for etching through a portion of a selected layer of a layer stack of a wafer. The method includes the step of etching at least partially through the selected layer while providing a first radio frequency (RF) signal having a first RF frequency to the top electrode. The method further includes the step of providing a second RF signal having a second RF frequency lower than the first RF frequency to the bottom electrode.Type: GrantFiled: March 29, 1996Date of Patent: January 25, 2000Assignee: Lam Research CorporationInventors: Sung Ho Kim, David R-Chen Liu
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Patent number: 6010636Abstract: An improved anode design, incorporating domes, for plasma reactors enhances plasma density at the anode. The domes give rise to a high-divergence, three-dimensional electric field distribution that accelerates electrons to a focused central region in the dome, thereby increasing ionization and dissociation. The enhanced plasma density increases the reaction rate at a substrate opposite the anode.Type: GrantFiled: December 29, 1995Date of Patent: January 4, 2000Assignee: Lam Research CorporationInventors: John F. Donohue, Al Sampson
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Patent number: 6008130Abstract: A plasma confinement ring comprising a first generally planar surface; a second generally planar surface; an aperture extending between the first and second surfaces, the aperture including an annular surface, and a curved surface extending between the annular surface and the first planar surface.Type: GrantFiled: August 14, 1997Date of Patent: December 28, 1999Assignee: VLSI Technology, Inc.Inventors: David E. Henderson, Ian Harvey
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Patent number: 6001267Abstract: A plasma enhanced chemical processing reactor and method. The reactor includes a plasma chamber including a first gas injection manifold and a source of electromagnetic energy. The plasma chamber is in communication with a process chamber which includes a wafer support and a second gas manifold. The reactor also includes a vacuum system for exhausting the reactor. The method includes the steps of generating a plasma within the plasma chamber, introducing at least one gaseous chemical into the process chamber proximate to the wafer support, applying r.f. gradient to induce diffusion of the plasma to the area proximate the wafer support, and exhausting the reactor in a substantially symmetrical manner.Type: GrantFiled: February 21, 1997Date of Patent: December 14, 1999Assignee: Watkins-Johnson CompanyInventors: Ron van Os, William J. Durbin, Richard H. Matthiesen, Dennis C. Fenske, Eric D. Ross
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Patent number: 6001699Abstract: A method for forming contacts with vertical sidewalls, high aspect ratios, improved salicide and photoresist etch selectivity at submicron dimensions. In one currently preferred embodiment, an opening is formed in a dual oxide layer by etching the undoped oxide layer at a first rate and then etching the doped oxide layer at a second rate. The etch process is performed in a low density parallel plate reactor. The process parameters of the etch are fixed in ranges which optimize the etch process and allow greater control over the critical dimensions of the opening. For example, the oxide layer is etched at a pressure in the range of approximately 100-300 mTorr and with an etch chemistry having a CHF.sub.3 :CF.sub.4 gas flow ratio in the range of approximately 3:1-1:1, respectively.Type: GrantFiled: January 23, 1996Date of Patent: December 14, 1999Assignee: Intel CorporationInventors: Phi L. Nguyen, Mark A. Fradkin, Gilroy J. Vandentop
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Patent number: 5997962Abstract: A wafer is subjected to a plasma process, using plasma generated while a process gas is fed into a process room, and a plus DC voltage is applied to an electrostatic chuck in order to attract and hold the wafer on the electrostatic chuck by an electrostatic force. A minus DC voltage is applied to the electrostatic chuck while nitrogen gas is fed into the process room in order to cause DC discharge after the processed wafer is separated from the electrostatic chuck and before a next wafer is attracted and held on the electrostatic chuck. By doing so, plus electric charge in the gas is attracted to the electrostatic chuck, so that the surface of the electrostatic chuck is charged with plus electric charge, thereby preventing its attracting function from being deteriorated.Type: GrantFiled: June 28, 1996Date of Patent: December 7, 1999Assignee: Tokyo Electron LimitedInventors: Masahiro Ogasawara, Ryo Nonaka, Yoshiyuki Kobayashi
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Patent number: 5990016Abstract: A dry etching method and apparatus improves the uniformity of etching a wafer in the manufacture of a semiconductor device. The dry etching apparatus has a susceptor supporting the wafer, a cooling system installed in the susceptor, an upper RF (radio frequency) electrode which may incorporate a gas diffuser for spraying reactive gas toward the wafer, and an RF power source for producing an electric field used to react the gas and generate plasma. The gap between the upper RF electrode and the susceptor is configured to accommodate for distortions in the wafer or other processing requirements. In addition, the nozzles of the gas diffuser can be configured to spray different amounts of gas to also enhance the etching uniformity. Finally, one of the electrodes may be divided into concentric sections. In this case, the RF power source can generate electric fields of different intensities at the sections.Type: GrantFiled: December 23, 1997Date of Patent: November 23, 1999Assignee: Samsung Electronics Co., Ltd.Inventors: Byong-dong Kim, Jung-kyu Lee, Sung-il Kim
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Patent number: 5980769Abstract: A plasma etching method and apparatus are provided in which a distance between an ejection opening (20a) in a plasma generator (2) for ejecting an active species gas and a surface of an object to be etched can be changed to thereby shorten the time required for a surface flattening operation and reduce the cost of equipment as well. To this end, the ejection opening (20a) of a predetermined diameter is disposed in confrontation with a desired convex of the object to be etched in the form of a wafer (110). The active species gas in the form of an F gas (G) is ejected from the ejection opening (20a) to the convex to thereby flatten it through etching. A distance between the ejection opening and the convex is changed by means of a Z drive mechanism (4) to provide an etching area corresponding to an area of the convex, thus performing effective flattening of the wafer (110).Type: GrantFiled: November 6, 1997Date of Patent: November 9, 1999Assignee: Speedfam Co., Ltd.Inventors: Michihiko Yanagisawa, Shinya Iida
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Patent number: 5976993Abstract: A layer of reduced stress is formed on a substrate using an HDP-CVD system by delaying or interrupting the application of capacitively coupled RF energy. The layer is formed by introducing a process gas into the HDP system chamber and forming a plasma from the process gas by the application of RF power to an inductive coil. After a selected period, a second layer of the film is deposited by maintaining the inductively-coupled plasma and biasing the plasma toward the substrate to enhance the sputtering effect of the plasma. In a preferred embodiment, the deposited film is a silicon oxide film, and biasing is performed by application of capacitively coupled RF power from RF generators to a ceiling plate electrode and wafer support electrode.Type: GrantFiled: March 28, 1996Date of Patent: November 2, 1999Assignee: Applied Materials, Inc.Inventors: K. V. Ravi, Kent Rossman, Turgut Sahin, Pravin Narwankar
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Patent number: 5961850Abstract: A plasma processing apparatus and method controls the temperature of those portions in the processing chamber to which reaction products or gaseous reaction products generated during plasma processing adhere, thereby minimizing the generation of foreign matter and ensuring high yields. A plasma processing gas is supplied to the plasma generation chamber 10 whose pressure is maintained at a predetermined value. Provided in the plasma generation chamber are a specimen mount 11 on which to mount an object to be processed and an evacuation mechanism 16 that evacuates the plasma generation chamber.Type: GrantFiled: March 14, 1996Date of Patent: October 5, 1999Assignee: Hitachi, Ltd.Inventors: Yoshiaki Satou, Tadamitsu Kanekiyo, katsuyoshi Kudo
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Patent number: 5955381Abstract: The quartz shadow ring of a conventional plasma etching apparatus is desirably coated with material which inhibits the liberation of oxygen into the plasma. Investigation has shown that the liberated oxygen degrades etching uniformity across the wafer.Type: GrantFiled: March 3, 1998Date of Patent: September 21, 1999Assignee: Lucent Technologies Inc.Inventors: Donald Stephen Bitting, Thomas Craig Esry, David Huibregtse, Paul Edward Wheeler
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Patent number: 5955383Abstract: A method and apparatus to improve process control during plasma etching of semiconductor substrates. Improvements are directed towards controlling the rate of etching when using consumable electrodes. Consumable electrode materials are used to increase selectivity in certain plasma etching processes as in via. contact. or in SOG etch. A consumable electrode material has a significant effect on processing time due to changing gap dimension between electrodes. This invention teaches how to adjust for process variables by using feedback from two strategically placed pressure manometers.Type: GrantFiled: January 22, 1997Date of Patent: September 21, 1999Assignee: Taiwan Semiconductor Manufacturing Company Ltd.Inventor: Yuan-Ko Hwang
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Patent number: 5945008Abstract: The present invention provides a method for plasma control, in which an electric field is generated in the direction perpendicular to the surface of an object to be processed in plasma atmosphere generated in a processing chamber and another electric field is generated in the direction parallel to the surface, and the direction of ion or electron in plasma atmosphere is controlled by controlling the composite electric field composed of both the electric fields. The invention provides also an apparatus for plasma control provided with a perpendicular electric field generating means for generating an electric field in the direction perpendicular to the surface of the object, and a parallel electric field generating means for generating an electric field in the direction parallel to the surface of the object.Type: GrantFiled: September 26, 1995Date of Patent: August 31, 1999Assignee: Sony CorporationInventors: Toshiro Kisakibaru, Akira Kojima, Yasushi Kato, Isao Honbori, Satoshi Bannai, Tomohiro Chiba, Toshitaka Kawashima
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Patent number: 5945353Abstract: In a plasma processing method and apparatus for carrying out plasma processing by supplying a high-frequency power of 20 MHz to 450 MHz to cause discharge to take place between a first electrode serving also as a film forming substrate and a second electrode provided so as to surround the first electrode, the high-frequency power is supplied from its power source to the second electrode at two points at least. In plasma processing apparatuses as typified by plasma CVD apparatuses to which the high-frequency power of a frequency from 20 MHz to 450 MHz is supplied, this method and apparatus can effectively decrease unevenness in plasma processing in the peripheral direction of the film formed, can promise a high plasma processing rate and can improve the characteristics of a deposited film during deposited film formation.Type: GrantFiled: October 1, 1997Date of Patent: August 31, 1999Assignee: Canon Kabushiki KaishaInventors: Junichiro Hashizume, Shigenori Ueda, Shinji Tsuchida
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Patent number: 5916455Abstract: A low pressure plasma ignition method and apparatus includes an ignition cylinder which passes through an anode of a vacuum chamber, where the outlet of the ignition cylinder forms a nozzle. A coil is arranged around the cylinder and a plasma-generating gas supply pipe passes through an upper part of the cylinder. A plasma-generating gas, such as Argon gas, is supplied to the ignition cylinder in this structure, such that a high density plasma is formed in the ignition cylinder that is expelled into the vacuum chamber while the pressure is reduced through the nozzle. In the vacuum chamber, the expelled plasma becomes a seed plasma, such that a low pressure plasma is readily generated in the vacuum chamber.Type: GrantFiled: July 8, 1996Date of Patent: June 29, 1999Assignee: Applied Materials, Inc.Inventor: Hiromi Kumagai
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Patent number: 5904487Abstract: An electrode reshaping process and apparatus is provided for use in a semiconductor etching device. A wafer is place between upper and lower electrodes of the semiconductor etching device. The apparatus and method selectively adjusts the shape of an upper electrode in the semiconductor etching device to compensate for non-uniformities inherent in the etching device. One or more motors attached to the upper electrode provide the electrode shaping forces in accordance with information provided by etch rate variation models stored in a host computer. With the shape of the upper electrode adjusted, the wafer can be etched more uniformally.Type: GrantFiled: October 8, 1996Date of Patent: May 18, 1999Assignee: Advanced Micro Devices, Inc.Inventors: Michael R. Conboy, Elfido Coss, Jr.
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Patent number: 5904571Abstract: An apparatus and method in a plasma processing chamber for reducing charging of a wafer is described. A plasma generating element is configured to cause a plasma including ions and free radicals to be formed in a plasma generating region. A plasma diffusion region is configured so that plasma generated in the plasma generating region can diffuse through the plasma diffusion region. A conductive grid is positioned within the plasma diffusion region between the wafer and the plasma generating region. The conductive grid includes a mesh which is configured to trap a portion of the ions so that a portion of the ions are prevented from diffusing through the diffusion region to reach the wafer.Type: GrantFiled: June 28, 1996Date of Patent: May 18, 1999Assignee: Lam Research Corp.Inventors: Roger Patrick, Phillip L. Jones, Kambiz Fallahpour, Yun-Yen Yang, Wen-Ben Chou
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Patent number: 5891348Abstract: An apparatus (20) for uniformly processing substrates (25) having a surface with a center (80) and a peripheral edge (85). The apparatus (20) comprises (i) a process chamber (30) having a gas distributor (55) for distributing process gas in the process chamber (30); (ii) a support (75) for supporting a substrate (25) in the process chamber (30); (iii) a plasma generator for forming a plasma from the process gas in the process chamber (30); and (iv) a focus ring (90) in the process chamber (30). The focus ring (90) comprises (a) a wall (95) surrounding the substrate (25) to substantially contain the plasma on the substrate surface, and (b) a channel (100) in the wall (95). The channel (100) has an inlet (105) adjacent to, and extending substantially continuously around the peripheral edge (85) of the substrate surface.Type: GrantFiled: January 26, 1996Date of Patent: April 6, 1999Assignee: Applied Materials, Inc.Inventors: Yan Ye, Gerald Zheyao Yin, Diana Xiaobing Ma, Steve S. Y. Mak
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Patent number: 5882414Abstract: The present invention provides a method and apparatus for introducing gases into a processing chamber and cleaning isolated surfaces thereof. In one embodiment, the apparatus provides a gas distribution system which comprises a face plate and a blocker plate located adjacent the face plate wherein the blocker plate is electrically insulated from the face plate. An RF power source is electrically connected to the face plate and a switch that selectively connects the blocker plate to the RF power source or grounds the blocker plate. When the power source is applied to the faceplate and the blocker plate is grounded, an energy potential is formed between the face plate and the blocker plate. The energy potential is sufficient to strike a plasma from cleaning gases introduced into the gas distribution system to clean the apertures and surfaces of both the face plate and the blocker plate.Type: GrantFiled: September 9, 1996Date of Patent: March 16, 1999Assignee: Applied Materials, Inc.Inventors: Gary L. Fong, Quoc Truong, Visweswaren Sivaramakrishman
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Patent number: 5879575Abstract: A method for simultaneously processing a workpiece using a plasma and cleaning the reactor in which processing takes place is disclosed. The plasma generated in the reactor performs simultaneous workpiece processing and reactor cleaning. Reactor cleaning may be accomplished by directing a portion of the plasma at an inner surface of the reactor such as by a power source auxiliary to that used to produce the processing plasma. An apparatus for carrying out a method for simultaneously processing a workpiece with a plasma and cleaning a reactor of etch residues generated from processing is disclosed.Type: GrantFiled: November 21, 1997Date of Patent: March 9, 1999Assignee: Applied Materials, Inc.Inventors: Avi Tepman, Yan Ye
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Patent number: 5879573Abstract: An optimal gap is determined between a lower electrode and an upper electrode in a plasma processing device. A gap is set between the lower electrode and the upper electrode, and a substrate is processed in the plasma processing chamber. The processing results are obtained, and the processing rate and uniformity are determined from the processing results. The processing rate and uniformity are plotted with the gap setting. The steps of setting, processing, obtaining, determining, and plotting are repeated for additional substrates, the gap setting being different for each substrate. The optimal gap setting is selected as the gap setting corresponding to an optimal processing rate and an optimal uniformity.Type: GrantFiled: August 12, 1997Date of Patent: March 9, 1999Assignee: VLSI Technology, Inc.Inventor: Christopher T. Robinett
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Patent number: 5872062Abstract: A method is provided wherein a process suitable for subtractive etching of titanium nitride layers useful in the fabrication of semiconductor integrated circuit devices can be efficiently employed on commercially-available plasma reactor system equipment normally suitable only for subtractive etching of passivation layer materials and the like, resulting in increased efficiency and reduced cost in the manufacturing of such devices.Type: GrantFiled: May 20, 1996Date of Patent: February 16, 1999Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Iman Hsu
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Patent number: 5869402Abstract: A reactive gas is introduced into a vacuum chamber by a gas controller so that a plasma is generated in a plasma generation region. Subsequently, high-frequency power from a high-frequency power source is applied to a sample stage in the vacuum chamber so that ions in the plasma are made incident upon the sample stage, thereby performing dry etching with respect to a sample on the sample stage. In main etching, a value of (pressure of reactive gas)/(frequency of high-frequency power) is reduced so as to reduce a scattering probability, which is the probability of ions being scattered in collision with neutral particles in a sheath region, thereby increasing the energy of ion fluxes and making the incidence directions of the ion fluxes perpendicular to a surface of the sample stage.Type: GrantFiled: May 10, 1995Date of Patent: February 9, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Kenji Harafuji, Masafumi Kubota
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Patent number: 5846885Abstract: In a plasma equipment and a plasma treatment method of a semiconductor device capable of reducing electron shading effect and also suppressing charge damage without affecting various characteristics in plasma process, a distance between a substrate bias electrode and A counter electrode is set less than two times as long as a mean free path of electron. High frequency electric power of 100 kHz to 1 MHz is supplied to the substrate bias electrode, while high frequency electric power of 1 MHz to 100 MHz is supplied to the counter electrode.Type: GrantFiled: August 23, 1996Date of Patent: December 8, 1998Assignee: Fujitsu LimitedInventors: Takeshi Kamata, Hiroshi Arimoto, Makoto Kosugi, Koichi Hashimoto
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Patent number: 5837615Abstract: A trench etching process is disclosed in which a substrate is etched under conditions that promote forward sputtering of mask material in a plasma reactor having at least three electrodes. The forward sputtering impedes etching of trench sidewalls by depositing a protective layer of mask material on the sidewalls of a trench being formed. By controlling the amount of forward sputtering, one can control the trench profile and aspect ratio (depth to width). By employing forward sputter etching in a three or more electrode reactor, trenches of less than one micron in width and having aspect ratios of at least 2.5:1 are formed. Such trenches are used in trench capacitors of high density DRAMs. A disclosed plasma reactor includes a grounded first electrode which forms part of the reactor's enclosure, a coiled second electrode disposed above and separated from the reactor enclosure by a dielectric shield, and a planar third electrode located below the substrate to be etched.Type: GrantFiled: August 14, 1997Date of Patent: November 17, 1998Assignee: LSI Logic CorporationInventor: Michael D. Rostoker