Abstract: An etching method, such as for forming a micromechanical device, is disclosed. One embodiment of the method is for releasing a micromechanical structure, comprising, providing a substrate; providing a sacrificial layer directly or indirectly on the substrate; providing one or more micromechanical structural layers on the sacrificial layer; performing a first etch to remove a portion of the sacrificial layer, the first etch comprising providing an etchant gas and energizing the etchant gas so as to allow the etchant gas to physically, or chemically and physically, remove the portion of the sacrificial layer; performing a second etch to remove additional sacrificial material in the sacrificial layer, the second etch comprising providing a gas that chemically but not physically etches the additional sacrificial material.

Abstract: A method of forming integrated circuitry includes chemical vapor depositing a silicon carbide comprising layer over a substrate at a temperature of no greater than 500° C. Plasma etching is conducted through at least a portion of the silicon carbide comprising layer using a gas chemistry comprising oxygen and hydrogen. Semiconductor processing methods include the above in fabrication of contact openings and in fabrication of MRAM circuitry. Semiconductor processing methods also include fabrication of contact openings using resist and removing silicon carbide comprising material and resist in a common plasma etching step.

Abstract: In a method for producing a bonding wafer by the hydrogen ion delamination method comprising at least a step of bonding a base wafer and a bond wafer having a micro bubble layer formed by gas ion implantation and a step of delaminating them at the micro bubble layer as a border, a peripheral portion of a thin film formed on the base wafer is removed after the delamination step. Preferably, a region of 1-5 mm from the peripheral end of the base wafer is removed. In the production of a bonding wafer by the hydrogen ion delamination method, there can be provided a bonding wafer free from problems such as generation of particles from peripheral portion of the wafer and generation of cracks in the SOI layer.

Abstract: A magnetron reactive ion etching apparatus comprises: an electrode unit including electrodes facing each other through a semiconductor device; a high-frequency power source forming an electric field on the electrode unit; a dipole ring magnet; and a switching mechanism. The dipole ring magnet forms the first magnetic field state, including a magnetic field in a direction perpendicular to a direction of the electric field or in a direction parallel to the semiconductor device, and the second magnetic field state, including a magnetic field whose strength at the periphery of the surface of the semiconductor device is so satisfactory that an electron Larmor radius is larger than the mean free path of electrons. The first magnetic field state is switched to the second magnetic field state at a predetermined timing by the switching mechanism which is controlled by a controller.

Abstract: A method of etching nitride over oxide is provided for the formation of vertical profile nitride spacers with high uniformity while maintaining the integrity of underlying thin oxide layers. The method includes providing a first gas flow including a first fluorocarbon and a second fluorocarbon at a first ratio, applying a first quantity of power to the first gas flow to create a first plasma, etching a first portion of a silicon nitride layer with the first plasma, providing a second gas flow including the first fluorocarbon and the second fluorocarbon at a second ratio greater than the first ratio, applying a second quantity of power to the second gas flow to create a second plasma, and etching a second portion of the silicon nitride layer with the second plasma.

Abstract: A metal-insulator-metal (MIM) capacitor (242/252) structure and method of forming the same. A dielectric layer (214) of a semiconductor device (200) is patterned with a dual damascene pattern having a first pattern (216) and a second pattern (218). The second pattern (218) has a greater depth than the first pattern (216). A conductive layer (226) is formed over the dielectric layer (214) in the first pattern, and a conductive layer is formed over the conductive layer in the first pattern (216). A dielectric layer (232), conductive layer (234), dielectric layer (236) and conductive layer (238) are disposed over the conductive layer (226) of the second pattern (218). Conductive layer (234), dielectric layer (232) and conductive layer (226) form a first MIM capacitor (252). Conductive layer (238), dielectric layer (236) and conductive layer (234) form a second MIM capacitor (242) parallel to the first MIM capacitor (242).

Abstract: A method for fabricating a semiconductor device comprises forming a material layer on a wafer having a plurality of independent pattering regions, and patterning the material layer to form a material pattern. The material layer is patterned such that the material patterns have different line widths in a plurality of the independent patterning regions. Pattering the material layer comprises a plurality of photolithographic processes or a plurality of etching processes, which are separately applied to each of the patterning regions. The photolithographic processes are preferably applied to each of the independent pattering regions using different reticles. The reticles have different line widths and circuit patterns of the same design. The etching processes are preferably applied to each of the independent pattering regions using different etch recipes.

Abstract: A method of treating a silicon surface of a substrate that includes heating the substrate in a process chamber to a temperature, exposing a first area adjacent to the silicon surface to a first gas mixture comprising an etchant, a silicon source gas, and a carrier, exposing a second area adjacent to the silicon surface to a second gas mixture, wherein the second gas mixture is different from the first gas mixture.

Abstract: The cross-sectional area of polysilicon lines is increased by selectively epitaxially growing an upper portion of the polysilicon line in the presence of a dielectric layer exposing the upper portion. Thus, a substantially T-shaped line is obtained, allowing a minimum bottom-CD while insuring a sufficient high conductivity.

Abstract: Semiconductor devices having a contact window and fabrication methods thereof are provided. A lower dielectric layer, conductive patterns and an upper dielectric layer are formed sequentially on a semiconductor substrate. The lower dielectric layer has a higher isotropic etch rate than that of the upper dielectric layer. The upper dielectric layer and the lower dielectric layer are patterned by anisotropic etching to form a trench without exposing the semiconductor substrate. The resultant structure is subject to isotropic etching to expose the substrate and to form a contact window having a wider width in a lower region than in an upper region without damaging the semiconductor substrate.

Abstract: Disclosed herein is a method of etching a trench in silicon overlying a dielectric material which reduces or substantially eliminates notching at the base of the trench, while reducing scalloping on the sidewalls of the trench. The method comprises etching a first portion of a trench by exposing a silicon substrate, through a patterned masking layer, to a plasma generated from a fluorine-containing gas. This etching is followed by a polymer deposition step comprising exposing the substrate to a plasma generated from a gas which is capable of forming a polymer on etched silicon surfaces. The etching and polymer deposition steps are repeated for a number of cycles, depending on the desired depth of the first portion of the trench. The final portion of the trench is etched by exposing the silicon to a plasma generated from a combination of a fluorine-containing gas and a polymer-forming gas.

Abstract: The present invention provides a method of forming, in semiconductor substrates, contact openings having low contact resistance. The method involves, in particular, the introduction of a “soft etch” cleaning step that is used to clean the bottom of the contact openings. The “soft etch” cleaning step uses fluorocarbon chemistry. It is shown that the resulting resistance of the contact openings is reduced.

Abstract: A lower electrode 106 with the temperature at its mounting surface set at 40° C. is provided inside a processing chamber 104 of an etching apparatus 100. After a wafer W is placed on the lower electrode 106, a processing gas with its gas composition and gas flow rate expressed as C4F8: CH2F2: Ar=7:4:500 (sccm) is induced into the processing chamber 104 while sustaining the pressure of the atmosphere inside the processing chamber 104 at 50 (mTorr). High-frequency power at 1500 (W) with the frequency at 13.56 (MHz) is applied to the lower electrode 106 to generate plasma. With the plasma thus generated, a carbon film is formed at shoulder 207 of an SiNx film layer 206 exposed inside a contact hole 210 and, at the same time, accumulation of carbon at the bottom of the contact hole 210 is prevented, to form a contact hole 210 achieving a high aspect ratio while preventing damage to the SiNx film layer.

Abstract: A method of unblinding an alignment mark comprising the following steps. A substrate having a cell area and an alignment mark within an alignment area is provided. An STI trench is formed into the substrate within the cell area. A silicon oxide layer is formed over the substrate, filling the STI trench and the alignment mark. The silicon oxide layer is planarized to form a planarized STI within the STI trench and leaving silicon oxide within the alignment mark to form a blinded alignment mark. A wet chemical etchant is applied within the alignment mark area over the blinded alignment mark to at least partially remove the silicon oxide within the alignment mark. The remaining silicon oxide is removed from within the blinded alignment mark to unblind the alignment mark. A drop etcher apparatus is also disclosed.

Abstract: A method is disclosed of patterning the surface of an object. The method comprises the steps of providing an object comprising a substrate having at least one layer formed thereon; forming a first SAM on the layer according to a desired pattern of a first material capable of binding to the layer; forming a second SAM of a second material on a region of the layer that is not covered by the first SAM, in a configuration that is complementary to the desired pattern; and etching the layer through the first SAM. The first material is selected to prevent the formation of the second SAM on the first SAM and to substantially not block the etching of an underlying region of the layer therethrough.

Abstract: A method for forming edge-defined structures with sub-lithographic dimensions which are used to further form conduction channels and/or storage structures in memory cells. Sacrificial silicon nitride islands are deposited at low temperatures and then patterned and etched by high resolution etching techniques. Polysilicon is next deposited over the sacrificial silicon nitride islands and directionally etched to form edge-defined polysilicon dot and strip structures which are about one tenth the minimum feature size. The edge-defined polysilicon strips and dots are formed between the source and drain region of an NMOS device. Subsequent to the removal of the sacrificial silicon nitride islands, the edge-defined polysilicon strips and dots are used to mask a threshold voltage implantation in a conventional CMOS process. A conduction channel and two adjacent potential minimum dots are formed after the removal of the edge-defined polysilicon strips and dots.

Abstract: The present invention provides a fabrication method for a semiconductor structure having a partly filled trench, having the following steps: provision of a semiconductor structure (1, 5) having a trench (2); filling of the trench (2) with a filling (10) in such a way that the filling (10) projects above a surface (OF) of the semiconductor structure (1, 5) by a first height (h1), the filling (10) covering the trench (2) and the periphery (20) of the trench (2); planarization of the filling (10) in a first etching step in such a way that the filling (10) is essentially planar with the surface (OF) of the semiconductor structure (1, 5); and sinking of the filling (10) in the trench (2) in a second etching step by a predetermined depth (T) proceeding from the surface of the semiconductor structure (1, 5); essentially the same plasma power and the same etchant composition being used for the first and second etching steps.

Abstract: A method of fabricating an SON structure semiconductor device is described. There is formed, on a silicon substrate, a stack of layers comprising first and second successive combinations. Each successive combination has a bottom silicon-germanium alloy (Site) layer and a top silicon layer. In a conventional way, a gate dielectric layer, a gate, spacers, source and drain regions, and an external passivating layer are formed by ionic implantation. A vertical hole is formed in the gate as far as the bottom Site layer to etch a part of the Site layers to form tunnels. The walls of the hole and the tunnels are then internally passivated so that the tunnels can remain empty or be filled.

Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to said first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example HeO2) flow rate of from about 12 sccm to about 15.6 sccm.

Abstract: A method of aligning a second layer to a first layer of a semiconductor structure by forming a first layer of a wafer having a distinguished feature via a first etching process that employs a first ionized gas generating machine. Forming a second layer having a circuit pattern via a second etching process that employs a second ionized gas generating machine, wherein the forming the second layer includes minimizing relative shifting between the distinguished feature located at an edge of the wafer for the first layer and the second circuit pattern located at the edge of the wafer for the second layer.

Abstract: Insulating films 21 through 24 of CF films (fluorine-contained carbon films) are formed on a substrate (not shown). In addition, Cu wiring layers 25 and 26 are formed on the CF films 21 and 23 via an adhesion layer 29 which comprises a Ti layer and a TiC layer. By forming the insulating films 21 through 24 of CF films, Cu in the wiring layers is prevented from diffusing into the insulating films 21 through 24. The relative dielectric constant of the CF film is smaller than the relative dielectric constant of a BCB film.

Abstract: A method for forming an opening through an interlayer to expose an underlying surface that retains high etch selectivity while having a relatively large process window to accommodate process variations. The method etches an interlayer under a first etching condition that forms a protective layer over portions of exposed surfaces of the opening during the etch process. The formation of the protective layer continues until an etch stop condition is produced, stopping further etching of the interlayer under the first condition prior to exposing the underlying surface. The method continues with etching through the protective layer under a second etching condition to expose a residual interlayer, and etching the exposed residual interlayer under the second etching condition to expose the underlying surface.

Abstract: A method for forming bottle trenches. The method comprises providing a substrate formed with a pad stack layer on the top, and a deep trench with protective layer on the upper portions of sidewalls thereof, implanting ions into the lower portions of sidewalls and bottom of the trench not covered by the protective layer to amorphize the atomic structure of the sidewalls and bottom, oxidizing the amorphous sidewalls and bottom of the trench to form a bottle-shaped oxide layer thereon, and removing the bottle-shaped oxide layer.

Abstract: A manufacturing method for a COF semiconductor device according to the present invention comprises:

Abstract: The invention provides a method for forming a capacitor that enables to form HSG-Si on the entire surface of the exposed surface of a cylindrical bottom electrode. A core pattern is formed on the cylinder core layer on a semiconductor substrate, and an amorphous silicon film is formed so as to cover the core pattern. The amorphous silicon film on the cylinder core layer is removed so that the amorphous silicon film remains on the inside wall of the core pattern, and a bottom electrode comprising the amorphous silicon film is formed on the inside wall of the core pattern. The cylinder core layer that is the component of the core pattern is etching-removed, and then the natural oxide film generated on the surface of the bottom electrode and the amorphous silicon surface layer that is the component of the bottom electrode is etching-removed. Thereafter, HSG-Si is formed on the surface of the bottom electrode.

Abstract: A semiconductor device manufacturing method that makes it possible to assure the required size of flat areas at the wiring overlay nitride film and to form an SAC structure in which the selectivity is not lowered at corners is provided. The method comprises a first etching process in which an insulating film 106 is etched under conditions for forming a vertical opening (vertical conditions) to open up the insulating film 106 to a point near a wiring overlay nitride film 105, a second etching process in which the insulating film 106 is opened until 105 becomes exposed by etching the insulating film 106 a under conditions assuring a high ratio of selectivity relative to the wiring overlay nitride film 105 (SAC conditions (1)) and a third etching process in which an insulating film 106a located between a first electrode G and a second electrode G is removed by etching the insulating film under conditions with a low ratio of selectivity relative to the wiring overlay nitride film 105 (SAC conditions (2)).

Abstract: Three fundamental and three derived aspects of the present invention are disclosed. The three fundamental aspects each disclose a process sequence that may be integrated in a full process. The first aspect, designated as “latent masking”, defines a mask in a persistent material like silicon oxide that is held abeyant after definition while intervening processing operations are performed. The latent oxide pattern is then used to mask an etch. The second aspect, designated as “simultaneous multi-level etching (SMILE)”, provides a process sequence wherein a first pattern may be given an advanced start relative to a second pattern in etching into an underlying material, such that the first pattern may be etched deeper, shallower, or to the same depth as the second pattern. The third aspect, designated as “delayed LOCOS”, provides a means of defining a contact hole pattern at one stage of a process, then using the defined pattern at a later stage to open the contact holes.

Abstract: The present invention relates to a method of manufacturing a semiconductor device. The method includes forming an etch stopper of a nitride-series material having a high etch select ratio for an interlayer insulating film of an oxide-series material is formed on a lower unit device. Therefore, plasma-introduced damage of the lower unit device can be prevented upon a metal contact process for connecting the lower unit device and an upper metal line.

Abstract: Provided is a method for forming a self aligned contact (SAC) of a semiconductor device that can minimize the loss of gate electrodes and hard mask. The method includes the steps of: providing a semiconductor substrate on which a plurality of conductive patterns are formed; forming a first insulation layer along the profile of the conductive patterns on the substrate; forming a second insulation layer on the substrate and simultaneously forming voids between the conductive patterns; forming a third insulation layer on the first insulation layer; and forming contact holes that expose the surface of the substrate between the conductive patterns by etching the third insulation layer and the second insulation layer covering the voids.

Abstract: A method of making a semiconductor structure includes etching an anti-reflective coating layer at a pressure of 10 millitorr or less; etching a nitride layer with a first nitride etch plasma having a first F:C ratio; and etching the nitride layer with a second nitride etch plasma having a second F:C ratio. The first F:C ratio is greater than the second F:C ratio.

Abstract: In forming an opening or space in a substrate, a layer of photoresist is provided on the substrate, and the photoresist is patterned to provide photoresist bodies having respective adjacent sidewalls. A polymer layer is provided on the resulting structure through a low temperature conformal CVD process. The polymer layer is anisotropically etched to form spacers on the respective adjacent sidewalls of the photoresist bodies. The substrate is then etched using the spacers as a mask.

Abstract: A dual damascene process is provided on a semiconductor substrate, having a conductive structure and a low-k dielectric layer covering the conductive structure. A first hard mask and a second hard mask are sequentially formed on the low-k dielectric layer, in which at least the hard mask contacting the low-k dielectric layer is of metallic material. Next, a first opening is formed in the second hard mask over the conductive structure, and a second opening is then formed in the first hard mask under the first opening. Afterward, the low-k dielectric layer that is not covered by the first hard mask is removed, thus a via hole is formed. Thereafter, the first hard mask that is not covered by the second hard mask is removed, and then the exposed low-k dielectric layer is removed. Thereby, a trench is formed over the via hole.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: A process for manufacturing components in a multi-layer wafer, including the steps of: providing a multi-layer wafer comprising a first semiconductor material layer, a second semiconductor material layer (, and a dielectric material layer arranged between the first and the second semiconductor material layer; and removing the first semiconductor material layer initially by mechanically thinning the first semiconductor material layer, so as to form a residual conductive layer, and subsequently by chemically removing the residual conductive layer. In one application, the multi-layer wafer is bonded to a first wafer of semiconductor material, with the second semiconductor material layer facing the first wafer, after micro-electromechanical structures have been formed in the second semiconductor material layer of the multi-layer wafer.

Abstract: A polysilicon layer (30) is formed on a dielectric region (20). An optional metal silicide layer (50) can be formed on the polysilicon layer. A dielectric layer (60) is formed over the metal silicide layer and a conductive layer (70) formed over the dielectric layer. The formed layers are etched by a combination of multi-step dry and wet process to form high precision integrated circuit capacitors.

Abstract: A method for making a semiconductor device is described. That method includes forming a sacrificial layer on a substrate, then forming a layer of photoresist on the sacrificial layer. After the photoresist layer is patterned, to form a patterned photoresist layer that has a first opening, part of the sacrificial layer is removed to generate an etched sacrificial layer that has a second opening that is substantially smaller than the first opening.

Abstract: A metalization process forms metal contacts having defined profiles for contact between microelectromechanical (MEMS) devices or chemical sensors with semiconductor devices. Gold contacts may be used for connecting the MEMS devices or chemical sensors to integrated CMOS devices. Gold contacts are deposited over a photoresist via having sidewalls for forming upwardly extending flanges. The metal contacts to the underlying semiconductor device, are formed using a polymethylmethacrylate (PMMA) etch back process for exposing and dissolving the gold metalization layer save the metal contact under a surviving portion of the etched back PMMA layer in a dimple of the gold layer over the photoresist via. The photoresist layer serves to form deep well gold contacts having upwardly extending flanges for connection to the MEMS devices or chemical sensors and to the integrated semiconductor devices.

Abstract: According to one embodiment of the invention, a method of forming a semiconductor device is provided. The method includes providing a first mask that defines a densely populated plurality of hole patterns. The first mask overlies a layer of dielectric material. The method also includes defining at least one isolated hole pattern in the first mask by covering one or more of the defined densely populated hole patterns using a second mask. The method also includes forming a plurality of densely populated holes in the dielectric material and at least one isolated hole by etching, according to one or more of the plurality of hole patterns that are not covered by the second mask, the layer of dielectric material.

Abstract: A method for forming a self-aligned contact hole includes forming a plurality of conductive structures on a semiconductor substrate, each conductive structure including a conductive film pattern and a protection pattern formed on the conductive film pattern, forming a first insulation film to fill a space between adjacent conductive structures, successively etching the first insulation film and the protection patterns until each of the protection patterns has an exposed level upper surface, forming a second insulation film on the resultant structure, and selectively etching portions of the second insulation film and the first insulation film using a photolithography process to form the self-aligned contact hole exposing a portion of the semiconductor substrate between adjacent conductive structures.

Abstract: Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.

Abstract: A thin-film magnetic head includes a top pole layer that defines a write track width. The top pole layer is formed as follows. A high saturation flux density material such as FeN or FeCo is sputtered to form a film to be patterned. A magnetic layer having a specific pattern is formed on this film to be patterned. Using the magnetic layer as a mask, the film is etched through reactive ion etching. The film is thereby patterned and a pole portion layer is formed. Next, cross-sectional surfaces of the pole portion layer obtained through the reactive ion etching are slightly etched to remove deposits.

Abstract: The present invention discloses a method for fabricating a semiconductor device. In a process for forming metal interconnection contact holes on both a gate electrode including an Si-rich SiON film as a mask insulating film in a peripheral circuit region and on a semiconductor substrate, the metal interconnection contact hole is formed according to a three-step etching process using a photoresist film pattern exposing the intended locations of a metal interconnection contacts as an etching mask. Accordingly, contact properties are improved by preventing damage to the semiconductor substrate, thereby reducing leakage current and improving yield.

Abstract: A method for fabricating an MOM capacitor (10) includes forming a first conductive layer (18) on an insulating support (12, 14), depositing a dielectric film (20) on the conductive layer, and patterning the dielectric film to define the capacitor feature. The dielectric film may comprise a stack of oxide and nitride layers (22, 24, 26). The dielectric is etched anisotropically with a fluorocarbon plasma to remove unwanted dielectric material (38) around the capacitor feature. Sidewalls (40), built up during the anisotropic etch as a result of sputtering the first conductive layer during the necessary overetch, are removed in a low power, higher pressure etch with an SF6 plasma, which is substantially isotropic in character. The process allows a sidewall-free capacitor to be formed in a single reactor without the need for solvent cleaning to remove the sidewall material.

Abstract: Fabricating a dual-trench alternating phase shift mask (PSM) is disclosed. A chromium layer over a quartz layer of the PSM is patterned according to a semiconductor design. The quartz layer is dry etched a first number of times through a first photoresist layer applied over the chromium layer and patterned according to the deep trenches of the alternating PSM design by using beam writing. This initially forms deep trenches of the PSM. The quartz layer is dry etched a second number of times through a second photoresist layer applied over the chromium layer and patterned according to the deep trenches and the shallow trenches of the alternating PSM design by using backside ultraviolet exposure. This completely forms shallow trenches and the deep trenches of the PSM. The second photoresist layer is then removed.

Abstract: A method of etching a semiconductor device preventing tapering of a gate electrode edge includes a main etching of an electrode or wiring material supported by a dielectric film at a semiconductor substrate surface to expose the dielectric film. After the main etching step, residues of the electrode or the wiring material by sequentially etching utilizing a first gas mixture including a halogen-containing gas and an additive gas suppressing etching of the dielectric film by the halogen-containing gas, and in a second gas mixture gas including the halogen-containing gas and the additive gas and having the additive gas amount in a larger concentration than the first gas mixture.

Abstract: A method or process for etching a trench in an IC structure is disclosed. The IC structure might be comprised of a plurality of different component materials arranged proximate to one another, all of which need to be etched down to a target level. A first etching chemistry is applied which preferentially etches a one type of component material. A second etching chemistry is applied which preferentially etches another type of component material. The method or process toggles back and forth between the etching chemistries until the target level is reached. The toggling techniques serves to maintain the profiles of the different component materials. One component material might also be embedded, as a collar or otherwise, around another component material. The toggling technique can serve to modulate the height, level, or shape of one material relative to another material. The toggling steps can be performed in situ or ex situ.

Abstract: There is provided a semiconductor device manufacturing method which comprises a step of forming titanium silicide layers (conductive patterns) on a silicon substrate (semiconductor substrate), a step of forming a cover insulating film (underlying insulating film), a step of forming a laminated film containing an alumina film (metal oxide film) on the cover insulating film, a first etching step of forming first holes in the laminated film by etching the laminated film, a cleaning step of cleaning the first holes, and a second etching step of forming second holes in the cover insulating film by etching the cover insulating film via the first holes under second etching conditions after the cleaning step.

Abstract: One embodiment of the present invention provides a process for selective etching during semiconductor manufacturing. The process starts by receiving a silicon substrate with a first layer composed of a first material, which is covered by a second layer composed of a second material. The process then performs a first etching operation that etches some but not all of the second layer, so that a portion of the second layer remains covering the first layer. Next, the system performs a second etching operation to selectively etch through the remaining portion of the second layer using a selective etchant. The etch rate of the selective etchant through the second material is faster than an etch rate of the selective etchant through the first material, so that the second etching operation etches through the remaining portion of the second layer and stops at the first layer.

Abstract: Densely disposed patterns constituting a semiconductor integrated circuit device are divided into a first mask pattern and a second mask pattern 28B such that a phase shifter S can be disposed, and a predetermined pattern is transferred on a semiconductor substrate by multiple-exposure thereof. The second mask pattern 28B has a main light transferring pattern 26c1, a plurality of auxiliary light transferring patterns 26c2 disposed thereabout, and a phase shifter S disposed in the main light transferring pattern 26c1. The auxiliary light transferring patterns 26c2 are disposed such that respective distances from a center of each thereof to a center of the main light transferring pattern 26c1 are substantially equal. With this arrangement, a densely disposed pattern is transferred with sufficient process transfer margin.

Abstract: There is disclosed a method of forming a metal wiring in a semiconductor device. The method includes forming a seed layer on a semiconductor substrate in which given structures including a lower metal wiring are formed, forming a photosensitive film pattern so that the seed layer can be exposed in the lower wiring portion, filling a metal layer by electroplating method in the pattern portion of the photosensitive film, removing the photosensitive film pattern, forming a diffusion barrier layer spacer on the sidewall of the metal layer, and forming an insulating film on the entire structure. Therefore, the present invention can solve poor contact with a lower wiring that is caused by shortage of processional margin in the process of forming an upper metal wiring in a higher-integration semiconductor device.