Abstract: Methods for manufacturing semiconductor devices with contact bodies extended in a direction of a bit line to increase the contact area between a contact body and a storage electrode is provided. In one aspect a method includes forming gate lines on a semiconductor substrate, forming a first insulating layer to cover the gate lines, forming first contact pads and second contact pads, which are electrically connected to the semiconductor substrate between the gate lines, by penetrating the first insulating layer. Further, a second insulating layer is formed to cover the first contact pads and the second contact pads, and bit lines are formed across over the gate lines and are electrically connected to the second contact pads by penetrating the second insulating layer. In addition, a third insulating layer is formed to cover the bit lines and is selectively etched to form a band-type opening that crosses the bit lines and exposes the first contact pads.

Abstract: A method of fabricating a flash memory cell having a split gate structure. A sacrificial layer is formed on a floating gate layer formed on a semiconductor substrate. The sacrificial layer is etched to form an opening exposing a portion of the floating gate layer. A gate interlayer insulating layer pattern is formed inside the opening. After removing the sacrificial layer pattern and etching the floating gate layer (using the gate interlayer insulating layer pattern as an etch mask), a floating gate is formed under the gate interlayer insulating layer pattern. A control gate is formed overlapping a portion of the floating gate.

Abstract: A method for patterning a magnetic memory cell junction is provided herein, which includes etching exposed portions of a stack of layers to a level spaced above a tunneling barrier layer of the stack of layers. In addition, the method may include implanting dopants into exposed portions of the stack of layers. For example, the method may include oxidizing and/or nitriding the exposed portions of the stack of layers. In some embodiments, the steps of etching and implanting dopants may form an upper portion of the magnetic cell junction. Alternatively, the method may include alternating the steps of etching and implanting dopants throughout the thickness of the exposed portions of the stack of layers. In either case, the stack of layers may include a magnetic layer which includes a material adapted to prevent the introduction of dopants underlying the tunneling barrier layer during the step of implanting.

Abstract: An exemplary method for making a memory structure having different-sized memory cell layers comprises forming at least two layers of ferromagnetic materials, forming at least one mask layer above the ferromagnetic materials, patterning the at least one mask layer, etching the ferromagnetic materials using the at least one mask layer as a first etch transfer mask, laterally reducing a planar dimension of the at least one mask layer to be narrower than the ferromagnetic materials, and etching a layer of the ferromagnetic materials using the reduced at least one mask layer as a second etch transfer mask, such that the ferromagnetic layer being etched becomes a different lateral size than another ferromagnetic layer of the ferromagnetic materials.

Abstract: A method includes performing a first etch process to form a via hole in a dual-damascene integrated circuit structure comprising a first dielectric layer and a second dielectric layer. The via hole extends at least substantially through the first and second dielectric layers. The method further includes filling at least a portion of the via hole with a plug material to form a plug within the via hole, and performing a second etch process through the first dielectric layer and the portion of the plug adjacent the first dielectric layer to form a trench in the first dielectric layer. The second etch process is performed using an RF power of less than 1,000 Watts and using an etching chemistry that includes CF4 and N2. For example, second etch process may use an etching chemistry of CF4/N2/Ar, which may additionally include one or both of CO and O2.

Abstract: A low-k dielectric film is deposited on the wafer. A metal layer is then deposited over the low-k dielectric film. A resist pattern is formed over the metal layer. The resist pattern is then transferred to the underlying metal layer to form a metal pattern. The resist pattern is stripped off. A through hole is plasma etched into the low-k dielectric film by using the metal pattern as a hard mask. The plasma etching causes residues to deposit within the through hole. A first wet treatment is then performed to soften the residues. A plasma dry treatment is carried out to crack the residues. A second wet treatment is performed to completely remove the residues.

Abstract: A method for manufacturing a micro-structural unit is provided. By the method, micro-machining is performed on a material substrate including first through third conductive layers and two insulating layers, one of which is interposed between the first and the second conductive layers, and the other between the second and the third conductive layers. The method includes several etching steps performed on the layers of the material substrate that are different in thickness.

Abstract: Dual trench depths are achieved on the same wafer by forming an initial trench having a depth corresponding to the difference in final depths of the shallow and deep trenches. A second mask is used to open areas for the deep trenches over the preliminary trenches and for the shallow trenches at additional locations. Etching of the shallow and deep trenches then proceeds simultaneously.

Abstract: A high selectivity and etch rate with innovative approach of inductively coupled plasma source. Preferably, the invention includes a method using plasma chemistry that is divided into main etch step of (e.g., Cl2+HBr+C4F8) gas combination and over etch step of (e.g., HBr+Ar). The main etch step provides a faster etch rate and selectivity while the over etch step will decrease the etch rate and ensure the stringer and residue removal without attacking the under layer.

Abstract: A process for the wet chemical treatment of semiconductor wafers, in which the semiconductor wafers are treated with treatment liquids, has the semiconductor wafers firstly treated with an aqueous HF solution, then treated with an aqueous O3 solution and finally treated with water or an aqueous HCl solution, these treatments forming a treatment sequence.

Abstract: A method is provided for plasma ashing to remove photoresist remnants and etch residues that are formed during preceding plasma etching of dielectric layers. The ashing method uses a two-step plasma process involving an oxygen-containing gas, where low or zero bias is applied to the substrate in the first cleaning step to remove significant amount of photoresist remnants and etch residues from the substrate, in addition to etching and removing detrimental fluoro-carbon residues from the chamber surfaces. An increased bias is applied to the substrate in the second cleaning step to remove the remains of the photoresist and etch residues from the substrate. The two-step process reduces the memory effect commonly observed in conventional one-step ashing processes. A method of endpoint detection can be used to monitor the ashing process.

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract: A method for etching a polysilicon layer comprises the steps of providing a semiconductor wafer substrate assembly having at least first and second features therein in spaced relation to each other which define an opening therebetween. A blanket polysilicon is formed over the wafer assembly and within the opening. A patterned photoresist layer is formed over the polysilicon layer, then the polysilicon layer within the opening is etched with a first etch. Subsequent to the first etch, the polysilicon with the opening is etched with a second etch comprising a halogen-containing gas flow rate of from about 35 sccm to about 65 sccm and an oxygen-containing gas (for example He—O2) flow rate of from about 12 sccm to about 15.6 sccm.

Abstract: A method for providing whisker-free aluminum metal lines or aluminum alloy lines in integrated circuits includes the following steps: providing a substrate; providing a whisker-containing layer made of aluminum metal or an aluminum alloy on the substrate; back-etching and/or resputtering the whisker-containing layer such that the whiskers are essentially removed; and structuring the whisker-free layer into the lines.

Abstract: A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material.

Abstract: A method for etching a high aspect ratio feature through a mask into a layer to be etched over a substrate is provided. The substrate is placed in a process chamber, which is able to provide RF power at a first frequency, a second frequency different than the first frequency, and a third frequency different than the first and second frequency. An etchant gas is provided to the process chamber. A first etch step is provided, where the first frequency, the second frequency, and the third frequency are at power settings for the first etch step. A second etch step is provided, where the first frequency, the second frequency, and the third frequency are at a different power setting.

Abstract: A method of fabricating a sharp protrusion on an underlayer is disclosed. A tip layer is deposited on an underlayer and then a mask layer is deposited on the tip layer. The mask layer is patterned with a beam-and-hat pattern that is used to form a beam-and-hat mask in the mask layer. Portions of the tip layer that are not covered by the beam-and-hat mask are isotropically etched to form a tip including a vertex. Beam portions of the beam-and-hat mask support the hat portion and prevent a release of the hat portion during the isotropic etching process. An anisotropic etch process can be used prior to the isotropic etching process to change a character of the tip. The underlayer can be patterned and etched to form a cantilever that includes the sharp protrusion extending outward of a surface of the cantilever.

Abstract: A method of patterning a layer of magnetic material to form isolated magnetic regions. The method forms a mask on a film stack comprising a layer of magnetic material such that the protected and unprotected regions are defined. The unprotected regions are etched in a high temperature environment to form isolated magnetic regions.

Abstract: In the step of forming a gate electrode in the region having the line width in which the miniaturization has been progressed, the present invention provides a method of fabricating a thin film transistor (TFT) whose patterning margin can be enlarged without requiring carrying out the photolithography multiple times. According to a fabricating method of the present invention, the mask pattern of the first layer and the mask pattern of the second layer can be formed in a self-aligned process and as a mask pattern which is analog and whose size are different from each other by performing the photolithography once. The hut shape gate can be formed in a self-aligned process by setting the line width located on the active layer so as to be Li in the mask pattern of the first layer, and so as to be L? in the mask pattern of the second layer, and by in turn carrying out the anisotropic etching using the mask pattern of the second layer and the anisotropic etching using the mask pattern of the first layer.

Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.

Abstract: A method is provided for forming iridium oxide (IrOx) nanotubes. The method comprises: providing a substrate; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; introducing oxygen as a precursor reaction gas; establishing a final pressure in the range of 1 to 50 Torr; establishing a substrate, or chamber temperature in the range of 200 to 500 degrees C.; and using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx hollow nanotubes from the substrate surface. Typically, the (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor is initially heated in an ampule to a first temperature in the range of 60 to 90 degrees C., and the first temperature is maintained in the transport line introducing the precursor. The precursor may be mixed with an inert carrier gas such as Ar, or the oxygen precursor reaction gas may be used as the carrier.

Abstract: A method of manufacturing an ink-jet printhead, including forming an insulation film on a substrate, depositing a metal layer onto said insulation film and patterning said metal layer to form a heater, forming an electrical wire on said substrate, etching said substrate at a predetermined depth from a top surface of said substrate in a direction perpendicular to a major surface of said heater to form a narrow passage, depositing an ink chamber barrier layer on said top surface of said substrate and patterning said ink chamber barrier layer to form an ink chamber, stacking a nozzle plate having a nozzle on said ink chamber barrier layer and disposed on an upper portion of said ink chamber barrier layer, and applying predetermined pressure and temperature onto said nozzle plate to bond said nozzle plate and said substrate, and etching said substrate from a bottom surface thereof to form a wide passage communicating with said narrow passage.

Abstract: We have developed an uncomplicated method of plasma etching deeply recessed features such as deep trenches, of at least 5 ?m in depth, in a silicon-containing substrate, in a manner which generates smooth sidewalls, having a roughness of less than about 1 ?m, typically less than about 500 nm, and even more typically between about 100 nm and 20 nm. Features having a sidewall taper angle, relative to an underlying substrate, typically ranges from about 85° to about 92° and exhibiting the smooth sidewalls are produced by the method. In one embodiment, a stabilizing etchant species is used constantly during the plasma etch process, while at least one other etchant species and at least one polymer depositing species are applied intermittently, typically periodically, relative to each other. In another embodiment, the stabilizing etchant species is used constantly and a mixture of the other etchant species and polymer depositing species is used intermittently.

Abstract: According to embodiments of the invention, a bit line interlayer insulating layer is placed over a semiconductor substrate. Two adjacent bit line patterns are placed in parallel on the bit line interlayer insulating layer and each of the two adjacent bit line patterns includes a bit line and a bit line capping layer pattern stacked thereon. A buried contact interlayer insulating layer covers a surface of the semiconductor substrate having the two adjacent bit line patterns. A contact hole is placed in a portion between the bit line patterns to penetrate the buried contact interlayer insulating layer and the bit line interlayer insulating layer and to expose at least one side wall of the bit line patterns. A contact hole spacer covers side wall of the contact hole. A contact hole plug is placed on the contact hole spacer to fill the contact hole.

Abstract: A method of anisotropiocally etching a semiconductive substrate uses a hydrofluorocarbon etch gas with an etch selectivity fluorocarbon gas. The fluorocarbon gas is used under conditions that enhance selectivity of the etch to an etch stop layer with respect to a bulk dielectric material such as doped or undoped silicon dioxide. In one method, a silicon dioxide dielectric layer is provided upon an etch stop layer, wherein the etch stop layer comprises silicon dioxide that is doped differently from the silicon dioxide dielectric layer. A gaseous etchant including a hydrofluorocarbon etch gas and a fluorocarbon selectivity compound is provided, and the silicon dioxide dielectric layer is exposed to the gaseous-etchant.

Abstract: A method of forming integrated circuitry includes chemical vapor depositing a silicon carbide comprising layer over a substrate at a temperature of no greater than 500° C. Plasma etching is conducted through at least a portion of the silicon carbide comprising layer using a gas chemistry comprising oxygen and hydrogen. Semiconductor processing methods include the above in fabrication of contact openings and in fabrication of MRAM circuitry. Semiconductor processing methods also include fabrication of contact openings using resist and removing silicon carbide comprising material and resist in a common plasma etching step.

Abstract: A method and intermediate structure for improving the thinning and planarity of a wafer back side utilizing planarization material applied to the back side prior to at least one portion of the thinning operation and which is subsequently removed concurrently with the wafer material by one or more suitable thinning or planarization techniques. The planarization material may be applied as a thin layer or film of a hardenable material to the rough, bare back side of a wafer to produce a planar surface when hardened. The planarization material is selected to exhibit a material removal rate approximating the removal rate of the wafer material for a given removal technique such as etching, mechanical abrasion or chemical-mechanical planarization (CMP). This approach to wafer thinning and planarization results in improved process control in the form of uniform material removal rates, reduction in wafer warpage, final surface smoothness and planarity, and even distribution of residual stresses.

Abstract: A process is presented for realizing buried microchannels (10) in an integrated structure (1) comprising a monocrystalline silicon substrate (2). The process forms in the substrate (2) at least one trench (4). A microchannel (10) is obtained starting from a small surface port of the trench (4) by anisotropic etching of the trench. The microchannel (10) is then completely buried in the substrate (2) by growing a microcrystalline structure to enclose the small surface port.

Abstract: A cleaning process for cleaning the surface of a substrate is disclosed, wherein the surface comprises portions of a dielectric material and portions of a conductive material. According to the method disclosed, the temperature at the surface of the substrate is kept below a predefined value during the actual cleaning step in a reactive and/or inert plasma ambient, such as an argon gas ambient, wherein the predefined value corresponds to the surface temperature at which agglomeration of the conductive material occurs.

Abstract: The subject invention pertains to a method and apparatus for etching copper (Cu). The subject invention can involve passing a halide gas over an area of Cu such that CuX, or CuX and CuX2, are formed, where X is the halide. Examples of halides which can be utilized with the subject matter include, but are not necessarily limited to, Cl, Br, F, and I. Once the CuX, or CuX and CuX2, are formed the subject invention can then involve passing a reducing gas over the area of Cu for a sufficient time to etch away at least a portion of the CuX, or CuX2, respectively. With respect to a specific embodiment in which CuX and CuX2 are produced when the halide gas is passed over the area of Cu, the reducing gas can be passed until essentially all of the CuX2 is etched and at least a portion of the CuX is etched. Examples of reducing gases which can be utilized with the subject invention include, but are not necessarily limited to, hydrogen gas and hydrogen gas plasma.

Abstract: A method for forming a patterned silicon-containing layer is disclosed. The method includes providing a substrate, providing a polysilicon layer on the substrate, providing a hard mask layer on the polysilicon layer, patterning and etching the hard mask layer and etching the polysilicon layer according to the pattern of the hard mask layer using a fluorine-containing etchant gas. The resulting sidewall profile of the etched polysilicon layer is substantially straight, uniform and devoid of a necking or notched configuration.

Abstract: A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Abstract: A method for etching a feature in an etch layer through a photoresist mask over a substrate is provided. A substrate with an etch layer disposed below a photoresist mask is placed in a process chamber. The photoresist mask is conditioned, wherein the conditioning comprises providing a conditioning gas comprising a hydrogen containing gas with a flow rate and at least one of a fluorocarbon and a hydrofluorocarbon with a flow rate to the process chamber; and energizing the conditioning gas to form the conditioning plasma. The conditioning plasma is stepped. An etch plasma is provided to the process chamber, wherein the etch plasma is different than the conditioning plasma. A feature is etched in the etch layer with the etch plasma.

Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

Abstract: This invention relates to a method for self-aligned fabricating an isolation structure of a trench capacitor. The method takes two steps to etch the substrate for forming the shallow trench of the isolation structure, wherein the conductive layer and the collar oxide layer of the trench capacitor remain intact during the etching processes.

Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.

Abstract: A multi-layered film on a semiconductor substrate is etched with a multi-step etching process by sequentially providing a plurality of process gases having different compositions in a chamber. A plasma discharge to excite the process gases is continued without an interruption during a switch to a different process gas. A relationship between different process gases desirable for the continuous plasma excitation is also disclosed. An apparatus suitable to practice this continuous plasma excitation process includes a process gas supply system having a gas reservoir. A mixture of at least two component gases is prepared and reserved in the reservoir, and is supplied to the etching chamber when it is needed.

Abstract: A method is provided for patterning iridium oxide (IrOx) nanostructures. The method comprises: forming a substrate first region adjacent a second region; growing IrOx nanostructures from a continuous IrOx film overlying the first region; simultaneously growing IrOx nanostructures from a non-continuous IrOx film overlying the second region; selectively etching areas of the second region exposed by the non-continuous IrOx film; and, lifting off the IrOx nanostructures overlying the second region. Typically, the first region is formed from a first material and the second region from a second material, different than the first material. For example, the first material can be a refractory metal, or refractory metal oxide. The second material can be SiOx. The step of selectively etching areas of the second region exposed by the non-continuous IrOx film includes exposing the substrate to an etchant that is more reactive with the second material than the IrOx.

Abstract: A method of masking and etching a semiconductor substrate includes forming a layer to be etched over a semiconductor substrate. An imaging layer is formed over the layer to be etched. Selected regions of the imaging layer are removed to leave a pattern of openings extending only partially into the imaging layer. After the removing, the layer to be etched is etched using the imaging layer as an etch mask. In one implementation, an ion implant lithography method of processing a semiconductor includes forming a layer to be etched over a semiconductor substrate. An imaging layer of a selected thickness is formed over the layer to be etched. Selected regions of the imaging layer are ion implanted to change solvent solubility of implanted regions versus non-implanted regions of the imaging layer, with the selected regions not extending entirely through the imaging layer thickness.

Abstract: An Iridium barrier layer is between a contact plug and a bottom electrode of a capacitor. Etching is performed to pattern the bottom electrode and barrier layer using a fluorine-based recipe resulting in the formation of a first fence clinging to the sidewalls. Next the remaining barrier layer is etched using a CO-based recipe. A second fence is formed clinging to and structurally supported by the first fence. At the same time, the CO-based recipe etches away a substantial portion of the first fence to remove the structural support provided to the second fence. The second fence is therefore lifted-off from the sidewalls leaving the sidewalls substantially free of clinging fences. The etched barrier layer has a sidewall transition. The sidewalls have a relatively low taper angle above the sidewall transition and a relatively steep taper angle below the sidewall transition.

Abstract: A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric layer by lithography. An organic layer is then formed. A trench is formed on the dielectric layer by the organic layer, thereby forming a dual damascene structure comprised of the trench and the via. The present invention is directed to a simplified dual damascene process, which can obtain a better trench profile without increasing the dielectric constant of the inter-metal dielectric (IMD).

Abstract: A light-emitting microelectronic package includes a light-emitting diode (110) having a first region (114) of a first conductivity type, a second region (116) of a second conductivity type, and a light-emitting p-n junction (118) between the first and second regions. The light-emitting diode defines a lower contact surface (120) and a mesa (122) projecting upwardly from the lower contact surface. The first region (114) of a first conductivity type is disposed in the mesa (122) and defines a top surface of the mesa, and the second region (116) of a second conductivity type defines the lower contact surface that substantially surrounds the mesa (122). The mesa includes at least one sidewall (130) extending between the top surface (124) of the mesa and the lower contact surface (120), the at least one sidewall (130) having a roughened surface for optimizing light extraction from the package.

Abstract: A method for fabrication of silicon-on-nothing (SON) MOSFET using selective etching of Si1?xGex layer, includes preparing a silicon substrate; growing an epitaxial Si1?xGex layer on the silicon substrate; growing an epitaxial thin top silicon layer on the epitaxial Si1?xGex layer; trench etching of the top silicon and Si1?xGex, into the silicon substrate to form a first trench; selectively etching the Si1?xGex layer to remove substantially all of the Si1?xGex to form an air gap; depositing a layer of SiO2 by CVD to fill the first trench; trench etching to from a second trench; selectively etching the remaining Si1?xGex layer; depositing a second layer of SiO2 by CVD to fill the second trench, thereby decoupling a source, a drain and a channel from the substrate; and completing the structure by state-of-the-art CMOS fabrication techniques.

Abstract: A method of forming a micro groove structure according to the invention has the steps of: (a) forming a mask pattern on a substrate capable of being subjected to dry etching; (b) dry etching the substrate having the mask pattern formed thereon; (c) vapor-phase forming a thin film of a masking material for the dry etching, on a non-etched surface portion of the substrate after the dry etching; and (d) dry etching the substrate having the thin film formed thereon. The steps (a) to (d) are carried out successively.

Abstract: Shallow trench isolation structures are simultaneously fabricated such that ones in a cell region have first-type features and others in a periphery region have second-type features. The first-type features can be rounded edges or can be first depths and widths, and the second-type features can be unrounded edges or can be second depths and widths which are different from the first depths and widths. The method includes forming patterned photoresist over a hard mask over portions of a cell and a periphery region, and removing the exposed hard mask layer in the periphery region while removing a portion of the exposed hard mask layer in the cell region. A trench is then partially formed in the periphery region and more of the hard mask layer is removed in the cell region, followed by the trench in the periphery region being deepened while a trench in the cell region is formed.

Abstract: A method for fabricating a through hole is disclosed. First, a conductive structure having a conductive layer and a cap layer are formed on a substrate. A patterned first photoresist layer is formed on the substrate and the conductive structure to define a pattern of the through hole. Then, a first etching process to remove the cap layer not covered by the first photoresist layer is performed until the conductive layer is exposed. The first photoresist layer is removed. A dielectric layer and a patterned second photoresist layer are formed on the substrate. Finally, a second etching process is performed to remove the dielectric layer not covered by the second photoresist layer until the conductive layer is exposed. The pattern of the second photoresist layer is the same as the pattern of the first photoresist layer.

Abstract: Disclosed is apparatus for treating samples, and a method of using the apparatus. The apparatus includes processing apparatus (a) for treating the samples (e.g., plasma etching apparatus), (b) for removing residual corrosive compounds formed by the sample treatment, (c) for wet-processing of the samples and (d) for dry-processing the samples. A plurality of wet-processing treatments of a sample can be performed. The wet-processing apparatus can include a plurality of wet-processing stations. The samples can either be passed in series through the plurality of wet-processing stations, or can be passed in parallel through the wet-processing stations.

Abstract: A method of forming a shallow trench isolation is disclosed. An example method of forming a shallow trench isolation performs a planarization process for a substrate on which a hard mask and an insulation layer are formed, selectively etching the insulation layer on the edge of the substrate by using wet etch equipment, and performs a main etching process in the center region of the substrate.

Abstract: A method of fabricating a flash memory cell is provided. The method includes providing a substrate and forming a patterned mask layer over the substrate. Using the patterned mask layer as an etching mask, the substrate is etched to form a trench. Thereafter, a first dielectric layer is formed over the substrate and then a first gate and a second gate is formed beside each sidewall of the trench. A first source/drain region is formed in the substrate at the bottom of the trench. A second dielectric layer is formed over the substrate and then a passivation layer is formed over the second dielectric layer. Afterwards, a portion of the passivation layer, the second dielectric layer and the first dielectric layer are removed. A third gate is formed in the trench and then the mask layer is removed. A third dielectric layer is formed on the substrate. Thereafter, a fourth and a fifth gate are formed beside the respective sidewall of the first gate and the second gate.

Abstract: A method of fabricating substrates, e.g., bulk wafers, silicon on insulator wafers, silicon on saphire, optoelectronic substrates. The method includes providing a substrate (e.g., silicon, gallium arsenide, gallium nitride, quartz). The substrate has a film characterized by a non-uniform surface, which includes a plurality of defects. At least some of the defects are of a size ranging from about 100 Angstroms and greater. The method also includes applying a combination of a deposition species for deposition of a deposition material and an etching species for etching etchable material. The combination of the deposition species and the etching species contact the non-uniform surface in a thermal setting to reduce a level of non-uniformity of the non-uniform surface by filling a portion of the defects to smooth the film of material. The smoothed film of material is substantially free from the defects and is characterized by a surface roughness of a predetermined value.