Selectively Etching Substrate Possessing Multiple Layers Of Differing Etch Characteristics Patents (Class 438/738)
  • Patent number: 12148692
    Abstract: A semiconductor package and a manufacturing method thereof are provided. A package substrate of a device includes a functional circuit structure in a central region of the package substrate and a seal ring structure in a peripheral region of the package substrate and electrically isolated from the functional circuit structure. The seal ring structure includes a via pattern including outer discrete features arranged in an outer loop and inner discrete features arranged in an inner loop between the outer loop and the functional circuit structure. In a top view, ends of adjacent two of the inner discrete features are spaced apart from each other by a non-zero distance, and one of the outer discrete features overlaps the non-zero distance.
    Type: Grant
    Filed: April 27, 2023
    Date of Patent: November 19, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Fang-Yu Liang, Kai-Chiang Wu
  • Patent number: 12142518
    Abstract: The present application discloses a method for fabricating a semiconductor device including: providing a photomask including an opaque layer on a mask substrate and surrounding a translucent layer on the mask substrate; forming a pre-process mask layer on a device stack; patterning the pre-process mask layer using the photomask to form a patterned mask layer including a mask region corresponding to the opaque layer, a trench region corresponding to the translucent layer, and a via hole corresponding to the mask opening of via feature; performing a damascene etching process to form a via opening and a trench opening in the device stack. The device stack includes a first dielectric layer on a substrate, a first etch stop layer on the first dielectric layer, and a second dielectric layer on the first etch stop layer. The damascene etching process forms the trench opening having a bottom on the first etch stop layer.
    Type: Grant
    Filed: March 23, 2022
    Date of Patent: November 12, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventor: Wei-Chen Pan
  • Patent number: 11973006
    Abstract: A method includes etching a through-substrate via (TSV) in a substrate from a backside of the substrate. The substrate has a device layer on a frontside. The method further includes depositing a conformal spacer layer on the backside of the substrate, and sidewalls and a bottom of the TSV, and etching the spacer layer to form a self-aligned mask for etching a contact opening at the bottom of TSV to a metal pad in the device layer, and etching the contact opening at the bottom of TSV to the metal pad in the device layer. The method further includes disposing a conductive material layer in the TSV and the contact opening to make a vertical interconnection from the backside of the substrate to the metal pad in the device layer.
    Type: Grant
    Filed: October 5, 2020
    Date of Patent: April 30, 2024
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jeffrey Peter Gambino, Swarnal Borthakur
  • Patent number: 11944021
    Abstract: Some embodiments relate to an integrated circuit including one or more memory cells arranged over a semiconductor substrate between an upper metal interconnect layer and a lower metal interconnect layer. A memory cell includes a bottom electrode disposed over the lower metal interconnect layer, a data storage or dielectric layer disposed over the bottom electrode, and a top electrode disposed over the data storage or dielectric layer. An upper surface of the top electrode is in direct contact with the upper metal interconnect layer without a via or contact coupling the upper surface of the top electrode to the upper metal interconnect layer. Sidewall spacers are arranged along sidewalls of the top electrode, and have bottom surfaces that rest on an upper surface of the data storage or dielectric layer.
    Type: Grant
    Filed: March 15, 2022
    Date of Patent: March 26, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Yang Chang, Wen-Ting Chu
  • Patent number: 11935780
    Abstract: A manufacturing method of a semiconductor structure includes: etching a substrate such that the substrate has a first top surface and a second top surface higher than the first top surface; implanting the first top surface of the substrate by boron to increase a p-type concentration of the first top surface of the substrate; forming a first dielectric layer on the substrate; and forming a second dielectric layer on the first dielectric layer.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: March 19, 2024
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chuan-Lin Hsiao, Wei-Ming Liao
  • Patent number: 11903329
    Abstract: A method of reducing junction resistance variation for junctions in quantum information processing devices fabricated using two-step deposition processes. In one aspect, a method includes providing a dielectric substrate, forming a first resist layer on the dielectric substrate, forming a second resist layer on the first resist layer, and forming a third resist layer on the second resist layer. The first resist layer includes a first opening extending through a thickness of the first resist layer, the second resist layer includes a second opening aligned over the first opening and extending through a thickness of the second resist layer, and the third resist layer includes a third opening aligned over the second opening and extending through a thickness of the third resist layer.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: February 13, 2024
    Assignee: Google LLC
    Inventor: Brian James Burkett
  • Patent number: 11817392
    Abstract: An integrated circuit is disclosed. The integrated circuit includes conductive rails, signal rails, at least one first via, and at least one first conductive segment. The at least one first via is disposed between the first conductive layer and the second conductive layer, and couples a first signal rail of the signal rails to at least one of the conductive rails. The first signal rail is configured to transmit a supply signal through the at least one first via and the at least one of the conductive rails to at least one element of the integrated circuit. The at least one first conductive segment is disposed between the first conductive layer and the second conductive layer. The at least one first conductive segment is coupled to the at least one of the conductive rails and is separate from the first signal rail.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: November 14, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shih-Wei Peng, Chia-Tien Wu, Jiann-Tyng Tzeng
  • Patent number: 11810964
    Abstract: A semiconductor device includes a first active region defined on a substrate, a first gate electrode across the first active region, a first drain region in the first active region at a position adjacent to the first gate electrode, an undercut region between the first active region and the first gate electrode, and a first gate spacer on a side surface of the first gate electrode and extending into the undercut region.
    Type: Grant
    Filed: October 1, 2020
    Date of Patent: November 7, 2023
    Inventors: Bongseok Suh, Daewon Kim, Beomjin Park, Sukhyung Park, Sungil Park, Jaehoon Shin, Bongseob Yang, Junggun You, Jaeyun Lee
  • Patent number: 11778919
    Abstract: A method of manufacturing a magnetoresistive stack/structure comprising (a) etching through a second magnetic region to (i) provide sidewalls of the second magnetic region and (ii) expose a surface of a dielectric layer, (b) depositing a first encapsulation layer on the sidewalls of the second magnetic region and over a surface of the dielectric layer, (c) thereafter: (i) etching the first encapsulation layer which is disposed over the dielectric layer using a first etch process, and (ii) etching re-deposited material using a second etch process, wherein, after such etching, a portion of the first encapsulation layer remains on the sidewalls of the second magnetic region, (d) etching (i) through the dielectric layer to form a tunnel barrier and provide sidewalls thereof and (ii) etching the first magnetic region to provide sidewalls thereof, and (e) depositing a second encapsulation layer on the sidewalls of the tunnel barrier and first magnetic region.
    Type: Grant
    Filed: October 26, 2021
    Date of Patent: October 3, 2023
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Sarin A. Deshpande, Kerry Joseph Nagel, Chaitanya Mudivarthi, Sanjeev Aggarwal
  • Patent number: 11777472
    Abstract: A bulk acoustic wave resonator is provided. The bulk acoustic wave resonator incudes a carrier substrate, having a main surface extending along a first direction; a piezoelectric layer, located on a side of the carrier substrate in a second direction perpendicular to the main surface of the carrier substrate; a first electrode and a second electrode; a cavity boundary structure, having a body part extending along the first direction and a protruding part protruding from the body part toward the piezoelectric layer; a resonant cavity, defined by the cavity boundary structure and the piezoelectric layer; and a periphery dielectric layer, located on a side of the protruding part of the cavity boundary structure away from the resonant cavity, a material of the periphery dielectric layer is different from a material of at least a portion of the protruding part adjacent to the periphery dielectric layer.
    Type: Grant
    Filed: November 22, 2022
    Date of Patent: October 3, 2023
    Assignee: Shenzhen Newsonic Technologies Co., Ltd.
    Inventors: Guojun Weng, Jian Wang
  • Patent number: 11715755
    Abstract: Methods of forming a super high density metal-insulator-metal (SHDMIM) capacitor and semiconductor device are disclosed herein. A method includes depositing a first insulating layer over a semiconductor substrate and a series of conductive layers separated by a series of dielectric layers over the first insulating layer, the series of conductive layers including device electrodes and dummy metal plates. A first set of contact plugs through the series of conductive layers contacts one or more conductive layers of a first portion of the series of conductive layers. A second set of contact plugs through the series of dielectric layers avoids contact of a second portion of the series of conductive layers, the second portion of the series of conductive layers electrically floating.
    Type: Grant
    Filed: June 15, 2020
    Date of Patent: August 1, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Hsien-Wei Chen, Ying-Ju Chen, Jie Chen, Ming-Fa Chen
  • Patent number: 11557631
    Abstract: Disclosed is a semiconductor device including first conductive lines, second conductive lines crossing the first conductive lines, and memory cells at intersections between the first conductive lines and the second conductive lines. Each of the memory cells includes a magnetic tunnel junction pattern, a bi-directional switching pattern connected in series to the magnetic tunnel junction pattern, and a conductive pattern between the magnetic tunnel junction pattern and the bi-directional switching pattern.
    Type: Grant
    Filed: November 3, 2020
    Date of Patent: January 17, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kilho Lee, Gwanhyeob Koh, Ilmok Park, Junhee Lim
  • Patent number: 11557507
    Abstract: A semiconductor structure includes a multilayer structure having a first layer and a second layer disposed on the first layer. The semiconductor structure further includes at least a first via extending from a top of the second layer to a top of a first metal contact disposed in the first layer. A polymer film is disposed on at least a portion of sidewalls of the first via.
    Type: Grant
    Filed: October 29, 2019
    Date of Patent: January 17, 2023
    Assignee: International Business Machines Corporation
    Inventors: Yann A. M. Mignot, Chih-Chao Yang
  • Patent number: 11545958
    Abstract: A film bulk acoustic resonator (FBAR) structure includes a bottom cap wafer, a piezoelectric layer disposed on the bottom cap wafer, the piezoelectric layer including a single crystalline piezoelectric material, a bottom electrode disposed below the piezoelectric layer; a top electrode disposed above the piezoelectric layer; and a cavity disposed below the bottom electrode.
    Type: Grant
    Filed: January 31, 2022
    Date of Patent: January 3, 2023
    Assignee: Shenzhen Newsonic Technologies Co., Ltd.
    Inventor: Jian Wang
  • Patent number: 10892671
    Abstract: Methods of manufacturing electrically conductive copper components for electric devices and method of joining electrically conductive copper components are provided. Each of the electrically conductive copper components are manufactured to include a preexisting coating of joining material located on or adjacent to a joining surface thereof.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: January 12, 2021
    Assignee: GM Global Technology Operations LLC
    Inventors: Hongliang Wang, Chen Zhou, Xingcheng Xiao
  • Patent number: 10811273
    Abstract: Provided is a method of modifying a surface of a substrate for improved etch selectivity of nitride etching. In an embodiment, the method includes providing a substrate with a nitride-containing structure, the nitride-containing structure having an oxygen-nitrogen layer. The method may also include performing a surface modification process on the nitride-containing structure with the oxygen-nitrogen layer using one or more gases, the surface modification process generating a cleaned nitride-containing structure. Additionally, the method may include performing a nitride etch process using the cleaned nitride-containing structure, wherein the etched nitride-containing structure are included in 5 nm or lower technology nodes, and the nitride etch process meets target etch rate and target etch selectivity, and the cleaned nitride-containing structure meet target residue cleaning objectives.
    Type: Grant
    Filed: September 11, 2018
    Date of Patent: October 20, 2020
    Assignee: Tokyo Electron Limited
    Inventors: Christopher Talone, Erdinc Karakas, Andrew Nolan, Sergey A. Voronin, Alok Ranjan
  • Patent number: 10276775
    Abstract: A vibration device that includes a vibration portion, a support portion connected to the vibration portion, a bending-vibrating portion connected to the support portion, and a frame-shaped base portion connected to the bending-vibration portion and disposed so as to surround the vibration portion. The base portion defines a slit that extends in a first direction crossing a second direction in which the support portion extends from the vibration portion, the slit defining first and second fixed ends of the bending-vibrating portion and which are continuous with the base portion. A length between a portion of the bending-vibrating portion connected to the support portion to one of the first and second fixed ends of the bending-vibrating portion is in a range of ?/8 to 3?/8, where ? denotes a wavelength of a bending vibration corresponding to a frequency of a characteristic vibration of the vibration portion.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: April 30, 2019
    Assignee: MURATA MANUFACTURING CO., LTD.
    Inventors: Takashi Hase, Toshio Nishimura, Hiroaki Kaida
  • Patent number: 10002873
    Abstract: A method of manufacturing a semiconductor device includes stacking a molding layer and a preliminary support layer on a substrate, forming a support layer having a plurality of openings by removing at least a portion of the preliminary support layer, forming a sacrificial layer by filling the plurality of openings with a different material from a material of the molding layer and from a material of the preliminary support layer, forming a plurality of vertical holes through the support layer and through the molding layer, forming a lower electrode within the plurality of vertical holes, and removing the sacrificial layer and the molding layer.
    Type: Grant
    Filed: June 7, 2017
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun Sil Hong, Seong Mo Koo
  • Patent number: 9853032
    Abstract: A semiconductor device includes a substrate and a plurality of storage nodes on the substrate and extending in a vertical direction relative to the substrate. A lower support pattern is in contact with the storage nodes between a bottom and a top of the storage nodes, the lower support pattern spaced apart from the substrate in the vertical direction, and the lower support pattern having a first maximum thickness in the vertical direction. An upper support pattern is in contact with the storage nodes above the lower support pattern relative to the substrate, the upper support pattern spaced apart from the lower support pattern in the vertical direction, and the lower support pattern having a second maximum thickness in the vertical direction that is greater than the first maximum thickness of the lower support pattern.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: December 26, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: JungWoo Seo
  • Patent number: 9748366
    Abstract: An article having alternating oxide layers and nitride layers is etched by an etch process. The etch process includes providing a first gas comprising C4F6H2 in a chamber of an etch reactor, ionizing the C4F6H2 containing gas to produce a plasma comprising a plurality of ions, and etching the article using the plurality of ions.
    Type: Grant
    Filed: September 19, 2014
    Date of Patent: August 29, 2017
    Assignee: Applied Materials, Inc.
    Inventors: Jong Mun Kim, Kenny L. Doan, Li Ling, Jairaj Payyapilly, Srinivas D. Nemani, Daisuke Shimizu, Yuju Huang
  • Patent number: 9574134
    Abstract: A voltage driven light emitting device includes an electroluminescent material and semiconductor nanocrystals, luminescent organic small molecules, mixtures of emissive species molecules, or conductive polymers. The semiconductor nanocrystals, luminescent organic small molecules, mixtures of emissive species molecules, or conductive polymers emit light. The semiconductor nanocrystals, luminescent organic small molecules, mixtures of emissive species molecules, or conductive polymers can be doped to provide desired emission characteristics. Devices that share a substrate and emit more than one color may be conveniently made.
    Type: Grant
    Filed: May 7, 2010
    Date of Patent: February 21, 2017
    Assignee: MASSACHUSETTS INSTITUTE OF TECHNOLOGY
    Inventors: Vanessa Wood, Matthew J. Panzer, Jonathan E. Halpert, Moungi G. Bawendi, Vladimir Bulovic
  • Patent number: 9379061
    Abstract: Some embodiments of the present disclosure relate to an integrated circuit device. The integrated circuit device includes a semiconductor substrate, and an inter-level dielectric layer arranged over the semiconductor substrate. An etch-stop layer is arranged over the inter-level dielectric layer. The etch-stop layer comprises silicon oxide, silicon nitride, or silicon oxynitride, and has a density greater than or equal to 2.15 g/cm3.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: June 28, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Joung-Wei Liou, Han-Ti Hsiaw, Keng-Chu Lin
  • Patent number: 9334571
    Abstract: Methods for the formation of individual, precisely shaped nano- or micro-scale metallic structures, particularly pyramids. With this technique, mass fabrication of high-quality, uniform, and ultra-sharp pyramids, cones and wedges is achieved. The high yield, reproducibility, durability and massively parallel fabrication methods of this disclosure provide structures suitable for reliable optical sensing and detection and for cementing near-field optical imaging and spectroscopy as a routine characterization.
    Type: Grant
    Filed: March 13, 2013
    Date of Patent: May 10, 2016
    Assignee: Regents of the University of Minnesota
    Inventors: Sang-hyun Oh, Timothy W. Johnson
  • Patent number: 9167700
    Abstract: A method of making a connection-pad structure includes providing a substrate and coating a curable layer over the substrate. A group of intersecting micro-channels is embossed in the curable layer. Each micro-channel extends from a surface of the curable layer into the curable layer toward the substrate. The curable layer is cured to form a cured layer having embossed intersecting micro-channels in the cured layer; the group of intersecting micro-channels forms a connection pad. A curable electrical conductor is located in the intersecting micro-channels. The curable electrical conductor is cured to form an electrically continuous cured electrical conductor formed in the group of intersecting micro-channels and an electrical connector is electrically connected to the cured electrical conductor.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: October 20, 2015
    Assignee: EASTMAN KODAK COMPANY
    Inventors: Ronald Steven Cok, David Paul Trauernicht
  • Patent number: 9111999
    Abstract: When performing plasma assisted etch processes for patterning complex metallization systems of microstructure devices, the probability of creating plasma-induced damage, such as arcing, may be reduced or substantially eliminated by using a superior ramp-up system for the high frequency power and the low frequency power. To this end, the high frequency power may be increased at a higher rate compared to the low frequency power component, wherein, additionally, a time delay may be applied so that, at any rate, the high frequency component reaches its target power level prior to the low frequency component.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: August 18, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Mohammed Radwan, Matthias Zinke
  • Patent number: 9059200
    Abstract: A field effect transistor (FET) includes a III-Nitride channel layer, a III-Nitride barrier layer on the channel layer, wherein the barrier layer has an energy bandgap greater than the channel layer, a source electrode electrically coupled to one of the III-Nitride layers, a drain electrode electrically coupled to one of the III-Nitride layers, a gate insulator layer stack for electrically insulating a gate electrode from the barrier layer and the channel layer, the gate insulator layer stack including an insulator layer, such as SiN, and an AlN layer, the gate electrode in a region between the source electrode and the drain electrode and in contact with the insulator layer, and wherein the AlN layer is in contact with one of the III-Nitride layers.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: June 16, 2015
    Assignee: HRL Laboratories, LLC
    Inventors: Rongming Chu, David F. Brown, Xu Chen, Adam J. Williams, Karim S. Boutros
  • Patent number: 9041062
    Abstract: A semiconductor device includes an insulator formed within a void to electrically isolate a fin from an underlying substrate. The void is created by removing a doped sacrificial layer formed between the substrate and a fin layer. The sacrificial layer is doped to allow for a thicker layer relative to an un-doped layer of substantially similar composition. The doped sacrificial layer thickness may be between 10 nm and 250 nm and may be carbon doped silicon-germanium. The thicker sacrificial layer allows for a thicker insulator so as to provide adequate electrical isolation between the fin and the substrate. During formation of the void, the fin may be supported by a dummy gate. The semiconductor structure may also include a bulk region that has at least a maintained portion of the doped sacrificial layer.
    Type: Grant
    Filed: September 19, 2013
    Date of Patent: May 26, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kangguo Cheng, Ali Khakifirooz, Alexander Reznicek, Dominic J. Schepis
  • Patent number: 9023733
    Abstract: The present disclosure relates to a method (10) for block-copolymer lithography. This method comprises the step of obtaining (12) a self-organizing block-copolymer layer comprising at least two polymer components having mutually different etching resistances, and the steps of applying at least once each of first plasma etching (14) of said self-organizing block-copolymer layer using a plasma formed from a substantially ashing gas, and second plasma etching (16) of said self-organizing block-copolymer layer using plasma formed from a pure inert gas or mixture of inert gases in order to selectively remove a first polymer phase. A corresponding intermediate product also is described.
    Type: Grant
    Filed: September 26, 2013
    Date of Patent: May 5, 2015
    Assignees: IMEC, Tokyo Electron Limited
    Inventors: Boon Teik Chan, Shigeru Tahara
  • Patent number: 8999856
    Abstract: A method of selectively etching silicon nitride from a substrate comprising a silicon nitride layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the silicon nitride layer at a higher etch rate than the reactive gas etches the silicon oxide layer.
    Type: Grant
    Filed: March 9, 2012
    Date of Patent: April 7, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Jingchun Zhang, Anchuan Wang, Nitin Ingle
  • Patent number: 8999855
    Abstract: According one embodiment, a method for manufacturing a semiconductor device is provided, which includes forming a pair of element isolation insulation films on a semiconductor substrate, forming a gate electrode structure on sides of the gate electrode structure, selectively removing oxide films that are formed on a top surface of the diffusion layer and a top surface of the gate electrode by placing the substrate in a gas atmosphere selected from the group consisting of F, Cl, Br, I, H, O, Ar, or N; and irradiating the semiconductor substrate with microwave radiation. The method also includes depositing a metal film on a top surface of the diffusion layer and a top surface of the gate electrode, and a silicide film is formed by heating the substrate.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: April 7, 2015
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Makoto Honda, Tomonori Aoyama
  • Patent number: 8993452
    Abstract: Provided are methods of patterning metal gate structures including a high-k gate dielectric. In an embodiment, a soluble hard mask layer may be used to provide a masking element to pattern a metal gate. The soluble hard mask layer may be removed from the substrate by water or a photoresist developer. In an embodiment, a hard mask including a high-k dielectric is formed. In a further embodiment, a protection layer is formed underlying a photoresist pattern. The protection layer may protect one or more layers formed on the substrate from a photoresist stripping process.
    Type: Grant
    Filed: January 18, 2013
    Date of Patent: March 31, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Matt Yeh, Shun Wu Lin, Chi-Chun Chen, Ryan Chia-Jen Chen, Yi-Hsing Chen, Chien-Hao Chen, Donald Y. Chao, Kuo-Bin Huang
  • Patent number: 8987144
    Abstract: In sophisticated semiconductor devices, high-k metal gate electrode structures may be formed in an early manufacturing stage with superior integrity of sensitive gate materials by providing an additional liner material after the selective deposition of a strain-inducing semiconductor material in selected active regions. Moreover, the dielectric cap materials of the gate electrode structures may be removed on the basis of a process flow that significantly reduces the degree of material erosion in isolation regions and active regions by avoiding the patterning and removal of any sacrificial oxide spacers.
    Type: Grant
    Filed: August 4, 2011
    Date of Patent: March 24, 2015
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Stephan Kronholz, Markus Lenski, Hans-Juergen Thees
  • Patent number: 8951859
    Abstract: A method for fabricating passive devices such as resistors and capacitors for a 3D non-volatile memory device. In a peripheral area of a substrate, alternating layers of a dielectric such as oxide and a conductive material such as heavily doped polysilicon or metal silicide are provided in a stack. The substrate includes one or more lower metal layers connected to circuitry. One or more upper metal layers are formed above the stack. Contact structures are formed which extend from the layers of conductive material to portions of the one or more upper metal layers so that the layers of conductive material are connected to one another in parallel or serially by the contact structures and the at least one upper metal layer. Additional contact structures can connect the circuitry to the one or more upper metal layers. The passive device can be fabricated concurrently with a 3D memory array using common processing steps.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: February 10, 2015
    Assignee: SanDisk Technologies Inc.
    Inventors: Masaaki Higashitani, Peter Rabkin
  • Patent number: 8937021
    Abstract: In some embodiments, methods for forming a three dimensional NAND structure include providing to a process chamber a substrate having alternating nitride layers and oxide layers or alternating polycrystalline silicon consisting layers and oxide layers formed atop the substrate and a photoresist layer formed atop the alternating layers; etching the photoresist layer to expose at least a portion of the alternating layers; providing a process gas comprising sulfur hexafluoride and oxygen to the process chamber; providing RF power of about 4 kW to about 6 kW to a first inductive RF coil and a second inductive RF coil disposed proximate the process chamber to ignite the process gas to form a plasma, wherein a current flowing through the first inductive RF coil is out of phase with RF current flowing through the second inductive RF coil; and etching through a desired number of the alternating layers to form a feature.
    Type: Grant
    Filed: June 17, 2014
    Date of Patent: January 20, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Han Soo Cho, Sang Wook Kim, Joo Won Han, Kee Young Cho, Anisul H. Khan
  • Patent number: 8932960
    Abstract: Different portions of a continuous loop of semiconductor material are electrically isolated from one another. In some embodiments, the end of the loop is electrically isolated from mid-portions of the loop. In some embodiments, loops of semiconductor material, having two legs connected together at their ends, are formed by a pitch multiplication process in which loops of spacers are formed on sidewalls of mandrels. The mandrels are removed and a block of masking material is overlaid on at least one end of the spacer loops. In some embodiments, the blocks of masking material overlay each end of the spacer loops. The pattern defined by the spacers and the blocks are transferred to a layer of semiconductor material. The blocks electrically connect together all the loops. A select gate is formed along each leg of the loops. The blocks serve as sources/drains.
    Type: Grant
    Filed: February 26, 2013
    Date of Patent: January 13, 2015
    Assignee: Micron Technology, Inc.
    Inventor: Luan C. Tran
  • Patent number: 8921136
    Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.
    Type: Grant
    Filed: January 17, 2013
    Date of Patent: December 30, 2014
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Neng-Kuo Chen, Shao-Ming Yu, Gin-Chen Huang, Chia-Jung Hsu, Sey-Ping Sun, Clement Hsingjen Wann
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Patent number: 8871120
    Abstract: Some embodiments include methods of removing silicon dioxide in which the silicon dioxide is exposed to a mixture that includes activated hydrogen and at least one primary, secondary, tertiary or quaternary ammonium halide. The mixture may also include one or more of thallium, BX3 and PQ3, where X and Q are halides. Some embodiments include methods of selectively etching undoped silicon dioxide relative to doped silicon dioxide, in which thallium is incorporated into the doped silicon dioxide prior to the etching. Some embodiments include compositions of matter containing silicon dioxide doped with thallium to a concentration of from about 1 weight % to about 10 weight %.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: October 28, 2014
    Assignee: Micron Technology, Inc.
    Inventor: Nishant Sinha
  • Patent number: 8865595
    Abstract: A semiconductor device and methods for small trench patterning are disclosed. The device includes a plurality of gate structures and sidewall spacers, an etch stop layer disposed over the sidewall spacers, an interlayer dielectric (ILD) layer disposed on a bottom portion of the etch stop layer, an etch buffer layer disposed on an upper portion of the etch stop layer, and a plurality of metal plugs between the gate structures. An upper portion of the metal plugs is adjacent to the etch buffer layer and a lower portion of the metal plugs is adjacent to the ILD layer.
    Type: Grant
    Filed: January 5, 2012
    Date of Patent: October 21, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Ya Hui Chang
  • Patent number: 8859355
    Abstract: A method of fabricating a semiconductor device including proving a substrate having a germanium containing layer that is present on a dielectric layer, and etching the germanium containing layer of the substrate to provide a first region including a germanium containing fin structure and a second region including a mandrel structure. A first gate structure may be formed on the germanium containing fin structures. A III-V fin structure may then be formed on the sidewalls of the mandrel structure. The mandrel structure may be removed. A second gate structure may be formed on the III-V fin structure.
    Type: Grant
    Filed: May 6, 2013
    Date of Patent: October 14, 2014
    Assignee: International Business Machines Corporation
    Inventor: Effendi Leobandung
  • Patent number: 8852962
    Abstract: Embodiments of the present invention provide methods and apparatus for forming a patterned magnetic layer for use in magnetic media. According to embodiments of the present application, a silicon oxide layer formed by low temperature chemical vapor deposition is used to form a pattern in a hard mask layer, and the patterned hard mask is used to form a patterned magnetic layer by plasma ion implantation.
    Type: Grant
    Filed: October 24, 2012
    Date of Patent: October 7, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Steven Verhaverbeke, Roman Gouk, Li-Qun Xia, Mei-yee Shek, Yu Jin
  • Patent number: 8846542
    Abstract: The invention includes methods for selectively etching insulative material supports relative to conductive material. The invention can include methods for selectively etching silicon nitride relative to metal nitride. The metal nitride can be in the form of containers over a semiconductor substrate, with such containers having upwardly-extending openings with lateral widths of less than or equal to about 4000 angstroms; and the silicon nitride can be in the form of a layer extending between the containers. The selective etching can comprise exposure of at least some of the silicon nitride and the containers to Cl2 to remove the exposed silicon nitride, while not removing at least the majority of the metal nitride from the containers. In subsequent processing, the containers can be incorporated into capacitors.
    Type: Grant
    Filed: February 13, 2014
    Date of Patent: September 30, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Kevin R. Shea, Thomas M. Graettinger
  • Patent number: 8828841
    Abstract: A system and method for forming an isolation trench is provided. An embodiment comprises forming a trench and then lining the trench with a dielectric liner. Prior to etching the dielectric liner, an outgassing process is utilized to remove any residual precursor material that may be left over from the deposition of the dielectric liner. After the outgassing process, the dielectric liner may be etched, and the trench may be filled with a dielectric material.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: September 9, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Tang Peng, Bing-Hung Chen, Tze-Liang Lee, Hao-Ming Lien
  • Patent number: 8828884
    Abstract: A method of making multi-level contacts. The method includes providing an in-process multilevel device including at least one device region and at least one contact region. The contact region includes a plurality of electrically conductive layers configured in a step pattern. The method also includes forming a conformal etch stop layer over the plurality of electrically conductive layers, forming a first electrically insulating layer over the etch stop layer, forming a conformal sacrificial layer over the first electrically insulating layer and forming a second electrically insulating layer over the sacrificial layer. The method also includes etching a plurality of contact openings through the etch stop layer, the first electrically insulating layer, the sacrificial layer and the second electrically insulating layer in the contact region to the plurality of electrically conductive layers.
    Type: Grant
    Filed: May 23, 2012
    Date of Patent: September 9, 2014
    Assignee: Sandisk Technologies Inc.
    Inventors: Yao-Sheng Lee, Zhen Chen, Syo Fukata
  • Patent number: 8822299
    Abstract: A method of fabricating a semiconductor device includes forming a gate dielectric layer comprising an oxide, and at least one conductive layer on a substrate, forming a mask on the conductive layer and patterning the at least one conductive layer by etching the at least one conductive layer using the mask as an etch mask to thereby form a gate electrode, wherein the oxide of the gate dielectric layer and the material of the at least one conductive layer are selected such that a byproduct of the etching of the at least one conductive layer, formed on the mask during the etching of the at least one conductive layer, comprises an oxide having a higher etch rate with respect to an etchant than the oxide of the gate dielectric layer.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: September 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Kwangwook Lee, Inseak Hwang
  • Patent number: 8815658
    Abstract: The present invention provides a method of forming a transistor. The method includes forming a first layer of a first semiconductor material above an insulation layer. The first semiconductor material is selected to provide high mobility to a first carrier type. The method also includes forming a second layer of a second semiconductor material above the first layer of semiconductor material. The second semiconductor material is selected to provide high mobility to a second carrier type opposite the first carrier type. The method further includes forming a first masking layer adjacent the second layer and etching the second layer through the first masking layer to form at least one feature in the second layer. Each feature in the second layer forms an inverted-T shape with a portion of the second layer.
    Type: Grant
    Filed: August 13, 2012
    Date of Patent: August 26, 2014
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Hemant Adhikari, Rusty Harris
  • Patent number: 8809112
    Abstract: The present invention refers to a method for selectively structuring of a polymer matrix comprising CNT (carbon nano tubes) on a flexible plastic substructure. The method also includes a suitable etching composition, which allows to proceed the method in a mass production.
    Type: Grant
    Filed: April 26, 2011
    Date of Patent: August 19, 2014
    Assignee: Merck Patent GmbH
    Inventors: Werner Stockum, Arjan Meijer, Ingo Koehler
  • Patent number: 8796156
    Abstract: A method of forming an integrated circuit structure includes providing a semiconductor substrate; providing a first lithography mask, a second lithography mask, and a third lithography mask; forming a first mask layer over the semiconductor substrate, wherein a pattern of the first mask layer is defined using the first lithography mask; performing a first etch to the semiconductor substrate to define an active region using the first mask layer; forming a second mask layer having a plurality of mask strips over the semiconductor substrate and over the active region; forming a third mask layer over the second mask layer, wherein a middle portion of the plurality of mask strips is exposed through an opening in the third mask layer, and end portions of the plurality of mask strips are covered by the third mask layer; and performing a second etch to the semiconductor substrate through the opening.
    Type: Grant
    Filed: January 4, 2012
    Date of Patent: August 5, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ming-Feng Shieh, Tsung-Lin Lee, Chang-Yun Chang
  • Patent number: 8790974
    Abstract: A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.
    Type: Grant
    Filed: September 20, 2013
    Date of Patent: July 29, 2014
    Assignee: Fujitsu Semiconductor Limited
    Inventors: Satoshi Nakai, Masato Suga, Jusuke Ogura