Abstract: A method of manufacturing a die seal ring including the following steps is provided. A dielectric layer is formed on a substrate. Conductive layers stacked on the substrate are formed in the dielectric layer. Each of the conductive layers includes a first conductive portion and a second conductive portion. The second conductive portion is disposed on the first conductive portion. A width of the first conductive portion is smaller than a width of the second conductive portion. A first air gap is formed between a sidewall of the first conductive portion and the dielectric layer. A second air gap is formed between a sidewall of the second conductive portion and the dielectric layer.

Abstract: In an embodiment, a method includes: forming a first dielectric layer over a die, the first dielectric layer including a photo-sensitive material; curing the first dielectric layer to reduce photo-sensitivity of the first dielectric layer; patterning the first dielectric layer by etching to form a first opening; forming a first metallization pattern in the first opening of the first dielectric layer; forming a second dielectric layer over the first metallization pattern and the first dielectric layer, the second dielectric layer including the photo-sensitive material; patterning the second dielectric layer by exposure and development to form a second opening; and forming a second metallization pattern in the second opening of the second dielectric layer, the second metallization pattern electrically connected to the first metallization pattern.

Abstract: A semiconductor storage device according to an embodiment includes a plurality of memory cells, a first film, and a second film. The memory cells are placed at intervals in a first direction on a semiconductor substrate. The first film is placed continuously in the first direction above the memory cells so as to cover all of the memory cells and including mainly metal oxide. The second film is placed on the first film and including mainly silicon nitride or silicon dioxide.

Abstract: A device includes a substrate, a gate dielectric over the substrate, and a gate electrode over the gate dielectric. A drain region and a source region are disposed on opposite sides of the gate electrode. Insulation regions are disposed in the substrate, wherein edges of the insulation regions are in contact with edges of the drain region and the source region. A dielectric mask includes a portion overlapping a first interface between the drain region and an adjoining portion of the insulation regions. A drain silicide region is disposed over the drain region, wherein an edge of the silicide region is substantially aligned to an edge of the first portion of the dielectric mask.

Abstract: Methods, apparatus, and systems for fabricating a semiconductor device comprising a semiconductor substrate; an oxide layer above the semiconductor substrate; a first metal component comprising tungsten disposed within the oxide layer; an interlayer dielectric (ILD) above the oxide layer, wherein the ILD comprises a trench and a bottom of the trench comprises at least a portion of the top of the first metal component; a barrier material disposed on sidewalls and the bottom of the trench; and a second metal component disposed in the trench.

Abstract: Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract: A method of forming a semiconductor integrated circuit (IC) includes forming a first semiconductor layer over a substrate, the first semiconductor layer having an uneven upper surface, forming a stop layer over the first semiconductor layer, the first semiconductor layer disposed between the substrate and the stop layer, and treating the stop layer to change its etch selectivity relative to the first semiconductor layer.

Abstract: In this method for producing a photoelectric conversion device: an i-type non-crystalline layer and an n-type non-crystalline layer comprising a non-crystalline semiconductor film are formed on the light-receiving surface of a semiconductor substrate; an i-type non-crystalline layer and an n-type non-crystalline layer comprising a non-crystalline semiconductor film are formed on the back surface of the semiconductor substrate; a protective layer is formed on the n-type non-crystalline layer; an insulating layer is formed on the n-type non-crystalline layer; and in the state where the top of the n-type non-crystalline layer is covered by the protective layer, patterning is performed by eliminating a portion of the i-type non-crystalline layer, the n-type non-crystalline layer, and the insulating layer.

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract: A method for fabricating a semiconductor device includes sequentially forming an etch stop film and an insulating film on a substrate including a lower pattern forming a conductive mask pattern including a first opening on the insulating film, forming a via-hole in the insulating film using the conductive mask pattern as an etch mask, the via-hole exposing the etch stop film, removing the conductive mask pattern, and forming a passivation film along a side wall of the via-hole after removing the conductive mask pattern.

Abstract: To prevent contact plugs formed to sandwich an abutting portion between gate electrodes, from being short-circuited via a void formed inside an insulating film of the abutting portion. Over sidewalls SW facing each other in the abutting portion between gate electrodes G2 and G5, a liner insulating film 6 and an interlayer insulating film 7 are formed. Between the sidewalls SW, the liner insulating film 6 formed on each of the side walls of the sidewalls SW are brought in contact with each other to close a space between the sidewalls SW to prevent a void from being generated inside the interlayer insulating film 7 and the liner insulating film 6.

Abstract: A method for fabricating a metal silicide interconnect in a stacked 3D non-volatile memory array. A stack of alternating layers of undoped/lightly doped polysilicon and heavily doped polysilicon is formed on a substrate. Memory holes are etched in cell areas of the stack while an interconnect area is protected. Slits are etched in the cell areas and the interconnect areas. A wet etch is performed via the slits or the memory holes in the cell area to remove portions of the undoped/lightly doped polysilicon layers in the cell area, and dielectric is deposited. Silicidation transforms portions of the heavily doped polysilicon layers in the cell area to metal silicide, and transforms portions of the heavily doped and undoped/lightly doped polysilicon layers in the interconnect area to metal silicide. The metal silicide interconnect can be used for routing power and control signals from below the stack to above the stack.

Abstract: A method of forming and controlling air gaps between adjacent raised features on a substrate includes forming a silicon-containing film in a bottom region between the adjacent raised features using a flowable deposition process. The method also includes forming carbon-containing material on top of the silicon-containing film and forming a second film over the carbon-containing material using a flowable deposition process. The second film fills an upper region between the adjacent raised features. The method also includes curing the materials at an elevated temperature for a period of time to form the air gaps between the adjacent raised features. The thickness and number layers of films can be used to control the thickness, vertical position and number of air gaps.

Abstract: The present disclosure relates to methods of forming a self-aligned contact and related apparatus. In some embodiments, the method forms a plurality of gate lines interspersed between a plurality of dielectric lines, wherein the gate lines and the dielectric lines extend in a first direction over an active area. One or more of the plurality of gate lines are into a plurality of gate line sections aligned in the first direction. One or more of the plurality of dielectric lines are cut into a plurality of dielectric lines sections aligned in the first direction. A dummy isolation material is deposited between adjacent dielectric sections in the first direction and between adjacent gate line sections in the first direction. One or more self-aligned metal contacts are then formed by replacing a part of one or more of the plurality of dielectric lines over the active area with a contact metal.

Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

Abstract: A method of manufacturing a plurality of spacers in a film stack includes forming at least one electrically-conductive element having sidewalls on a substrate, depositing a plurality of passivation layers proximate to the substrate, and performing etching on one of the plurality of passivation layers to form a plurality of spacers substantially across from the sidewalls of the at least one electrically-conductive element.

Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.

Abstract: The invention provides a process for producing a substrate with a piercing aperture, the piercing aperture being formed by conducting dry etching from the side of a second surface opposite to a first surface of a substrate to the first surface, the process comprising, in the following order, the steps of (a) forming a groove around a region where the piercing aperture is formed in the first surface of the substrate, (b) forming an etch-stop layer in the region where the piercing aperture is formed in the first surface of the substrate and in the interior of the groove, and (c) forming the piercing aperture by conducting the dry etching from the side of the second surface.

Abstract: The present invention relates to an etching method of capable of etching a silicon carbide substrate with a higher accuracy. A first etching step in which a silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C, SF6 gas is supplied into a processing chamber and plasma is generated from the SF6 gas, and a bias potential is applied to a platen, thereby isotropically etching the silicon carbide substrate K, and a second etching step in which the silicon carbide substrate K is heated to a temperature equal to or higher than 200 ° C., SF6 gas and O2 gas are supplied into the processing chamber and plasma is generated from the SF6 gas and the O2 gas, and a bias potential is applied to the platen on which the silicon carbide substrate K is placed, thereby etching the silicon carbide substrate K while forming a silicon oxide film as passivation film on the silicon carbide substrate K are alternately repeated.

Abstract: First, a semiconductor substrate having a first active region and a second active region is provided. The first active region includes a first transistor and the second active region includes a second transistor. A first etching stop layer, a stress layer, and a second etching stop layer are disposed on the first transistor, the second transistor and the isolation structure. A first etching process is performed by using a patterned photoresist disposed on the first active region as a mask to remove the second etching stop layer and a portion of the stress layer from the second active region. The patterned photoresist is removed, and a second etching process is performed by using the second etching stop layer of the first active region as a mask to remove the remaining stress layer and a portion of the first etching stop layer from the second active region.

Abstract: A method of manufacturing a semiconductor integrated circuit device which includes a semiconductor substrate; and multiple semiconductor elements disposed on the semiconductor substrate. The semiconductor elements include an n-channel MOS transistor and a p-channel MOS transistor. The n-channel MOS transistor is covered by a tensile stress film, and the p-channel MOS transistor is covered by a compressive stress film. A dummy region, the entire surface of which is covered by a combination of the tensile stress film and the compressive stress film, is disposed on the surface of the semiconductor substrate.

Abstract: A method is described for manufacturing a component having a through-connection. The method includes providing a substrate; forming a trench structure in the substrate, a substrate area which is completely surrounded by the trench structure being produced; forming a closing layer for closing off the trench structure, a cavity girded by the closing layer being formed in the area of the trench structure; removing substrate material from the substrate area surrounded by the closed-off trench structure; and at least partially filling the substrate area surrounded by the closed-off trench structure with a metallic material. A component having a through-connection is also described.

Abstract: A method of manufacturing a semiconductor device includes providing a substrate having a gate structure, a source region, and a drain region formed thereon, and the gate structure includes a gate insulating layer and a gate electrode. The method also includes forming a first stress layer on the substrate, removing the first stress layer, and forming a second stress layer on the substrate.

Abstract: Each gate structure formed on the substrate includes a gate dielectric, a gate conductor, a first etch stop layer, and a gate cap dielectric. A second etch stop layer is formed over the gate structures, gate spacers, and source and drain regions. A first contact-level dielectric layer and a second contact-level dielectric layer are formed over the second etch stop layer. Gate contact via holes extending at least to the top surface of the gate cap dielectrics are formed. Source/drain contact via holes extending to the interface between the first and second contact-level dielectric layers are subsequently formed. The various contact via holes are vertically extended by simultaneously etching exposed gate cap dielectrics and exposed portions of the first contact-level dielectric layer, then by simultaneously etching the first and second etch stop layers. Source/drain contact vias self-aligned to the outer surfaces gate spacers are thereby formed.

Abstract: A method for manufacturing a semiconductor device including at least one of the following steps: (1) Forming a lower electrode pattern on/over a substrate. (2) Forming a first interlayer insulating layer on the lower electrode pattern. (3) Forming an upper electrode pattern on the first interlayer insulating layer. (4) Forming a passivation layer on a side of the upper electrode pattern. (5) Forming a second interlayer insulating layer on the upper electrode pattern. (6) Etching the second interlayer insulating layer to form a cavity which exposes the passivation layer. (7) Forming a contact ball in the cavity.

Abstract: Embodiments of the invention provide a method of creating vias and trenches with different length. The method includes depositing a plurality of dielectric layers on top of a semiconductor structure with the plurality of dielectric layers being separated by at least one etch-stop layer; creating multiple openings from a top surface of the plurality of dielectric layers down into the plurality of dielectric layers by a non-selective etching process, wherein at least one of the multiple openings has a depth below the etch-step layer; and continuing etching the multiple openings by a selective etching process until one or more openings of the multiple openings that are above the etch-stop layer reach and expose the etch-stop layer. Semiconductor structures made thereby are also provided.

Abstract: Disclosed is a monitoring TEG for an etching process in a semiconductor device. The TEG includes an etch stopping layer on a substrate and a target layer to be etched provided on the etch stopping layer. The target layer to be etched includes a first opening portion formed by etching a portion of the target layer to be etched and a second opening portion formed by etching another portion of the target layer to be etched. The second opening portion has a smaller depth than the first opening portion. A depth of a partial contact hole formed by a first partial etching process may be measured.

Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.

Abstract: A method of manufacturing a semiconductor device including at least one of the following steps: (1) Forming a plurality of lower electrodes over a substrate. (2) Forming a first stop film over the lower electrodes. (3) Forming a filling layer over the first stop film. (4) Forming a second stop film over the filling layer. (5) Forming a first interlayer insulating layer over the second stop film. (6) Forming a plurality of upper electrodes over the first interlayer insulating layer. (7) Forming a second interlayer insulating layer over the upper electrodes. (8) Etching the second interlayer insulating layer and the first interlayer insulating layer to form a cavity. (9) Forming a contact ball in the cavity.

Abstract: A method for performing a spacer etch process is described. The method includes conformally applying a spacer material over a gate structure on a substrate, and performing a spacer etch process sequence to partially remove the spacer material from a capping region of the gate structure and a substrate region on the substrate adjacent a base of the gate structure, while retaining a spacer sidewall positioned along a sidewall of the gate structure.

Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.

Abstract: Methods and apparatus for removing oxide from a surface, the surface comprising at least one of silicon and germanium, are provided. The method and apparatus are particularly suitable for removing native oxide from a metal silicide layer of a contact structure. The method and apparatus advantageously integrate both the etch stop layer etching process and the native oxide removal process in a single chamber, thereby eliminating native oxide growth or other contaminates redeposit during the substrate transfer processes. Furthermore, the method and the apparatus also provides the improved three-step chemical reaction process to efficiently remove native oxide from the metal silicide layer without adversely altering the geometry of the contact structure and the critical dimension of the trenches or vias formed in the contact structure.

Abstract: According to example embodiments, a methods includes forming a peripheral structure including peripheral circuits on a peripheral circuits region of a substrate, recessing a cell array region of the substrate to form a concave region having a bottom surface lower than a top surface of the peripheral structure, forming a stacked layer structure conformally covering the concave region, the stacked layer structure including a plurality of layers sequentially stacked and having a lowest top surface in the cell array region and a highest top surface in the peripheral circuits region, forming a planarization stop layer that conformally covers the stacked layer structure, and planarizing the stacked layer structure using the planarization stop layer in the cell array region as a planarization end point to expose top surfaces of the thin layers between the cell array region and the peripheral circuits region simultaneously with a top surface of the peripheral structure.

Abstract: A method is provided for fabricating a transistor. A replacement gate stack is formed on a semiconductor layer, a gate spacer is formed, and a dielectric layer is formed. The dummy gate stack is removed to form a cavity. A gate dielectric and a work function metal layer are formed in the cavity. The cavity is filled with a gate conductor. One and only one of the gate conductor and the work function metal layer are selectively recessed. An oxide film is formed in the recess such that its upper surface is co-planar with the upper surface of the dielectric layer. The oxide film is used to selectively grow an oxide cap. An interlayer dielectric is formed and etched to form a cavity for a source/drain contact. A source/drain contact is formed in the contact cavity, with a portion of the source/drain contact being located directly on the oxide cap.

Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.

Abstract: A method for manufacturing a semiconductor device including, forming a first insulating film above a silicon substrate, forming an impurity layer in the first insulating film by ion-implanting impurities into a predetermined depth of the first insulating film, and modifying the impurity layer to a barrier insulating film by annealing the first insulating film after the impurity layer is formed, is provided.

Abstract: A method of fabricating openings is disclosed. First, a semiconductor substrate having a salicide region thereon is provided. An etch stop layer and at least a dielectric layer are disposed on the semiconductor substrate from bottom to top. Second, the dielectric layer and the etching stop layer are patterned to form a plurality of openings in the dielectric layer and in the etching stop layer so that the openings expose the salicide region. Then, a dielectric thin film covering the dielectric layer, sidewalls of the openings and the salicide region is formed. Later, the dielectric thin film disposed on the dielectric layer and on the salicide region is removed.

Abstract: A method for designing, fabricating, and predicting a desired structure in and/or on a host material through defining etch masks and etching the host material is provided. The desired structure can be micro- or nanoscale structures, such as suspended nanowires and corresponding supporting pillars, and can be defined one layer at a time. Arbitrary desired structures can also be defined and obtained through etching. Further, given the desired structure, a starting structure can be predicted where etching of the starting structure yields the desired structure.

Abstract: A method to determine minimum etch mask dosage or thickness as a function of etch depth or maximum etch depth as a function of etch mask implantation dosage or thickness, for fabricating structures in or on a substrate through etch masking via addition or removal of a masking material and subsequent etching.

Abstract: A semiconductor device with stress trench isolation and a method for forming the same are provided. The method includes: providing a silicon substrate; forming first trenches and second trenches on the silicon substrate, wherein an extension direction of the first trenches is perpendicular to that of the second trenches; forming a first dielectric layer in the first trenches and forming a second dielectric layer in the second trenches; and forming a gate stack on a portion of the silicon substrate surrounded by the first trenches and the second trenches, wherein a channel length direction under the gate stack is parallel to the extension direction of the first trenches, indices of crystal plane of the silicon substrate are {100}, and the extension direction of the first trenches is along the crystal orientation <110>. The embodiments of the present invention can improve response speed and performance of the devices.

Abstract: A method of etching a sacrificial layer for a micro-machined structure, the sacrificial layer positioned between a layer of a first material and a layer of a second material, the etching being carried out by an etching agent. The method includes: providing at least one species having an affinity for the etching agent greater than that of the layers of first material and second material and less than or equal to that of the sacrificial layer; and then etching the sacrificial layer by the etching agent, the etching being carried out to eliminate at least partially the sacrificial layer and then to eliminate at least partially the species.

Abstract: A method for forming a memory device includes: forming a tunnel insulation layer, a conductive layer for a floating gate electrode, a charge blocking layer and a conductive layer for a control gate electrode over a substrate; and selectively etching the conductive layer for the control gate electrode, the charge blocking layer and the conductive layer for the floating gate electrode, thereby forming a plurality of gate lines, a plurality of select lines and at least two dummy lines disposed in a gap region between adjacent select lines, wherein the gate lines, the select lines and the dummy lines together construct strings.

Abstract: A method of forming a nanopore array includes patterning a front layer of a substrate to form front trenches, the substrate including a buried layer disposed between the front layer and a back layer; depositing a membrane layer over the patterned front layer and in the front trenches; patterning the back layer and the buried layer to form back trenches, the back trenches being aligned with the front trenches; forming a plurality of nanopores through the membrane layer; depositing a sacrificial material in the front trenches and the back trenches; depositing front and back insulating layers over the sacrificial material; and heating the sacrificial material to a decomposition temperature of the sacrificial material to remove the sacrificial material and form pairs of front and back channels, wherein the front channel of each channel pair is connected to the back channel of its respective channel pair by an individual nanopore.

Abstract: The present application discloses a method of manufacturing a semiconductor structure. According to at least one embodiment, a first etch stop layer is formed over a conductive feature and a substrate, and the conductive feature is positioned over the substrate. A second etch stop layer is formed over the first etch stop layer. A first etch is performed to form an opening in the second etch stop layer, and the opening exposes a portion of the first etch stop layer. A second etch is performed to extend the opening downwardly by removing a portion of the exposed first etch stop layer, and the extended opening exposes a portion of the conductive feature.

Abstract: A method for processing an amorphous carbon film which has been formed on a substrate and wet-cleaned after being dry-etched includes preparing the substrate having the wet-cleaned amorphous carbon film and modifying a surface of the amorphous carbon film, before forming an upper layer on the wet-cleaned amorphous carbon film.

Abstract: A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon; forming a first cap layer on a surface of the substrate and sidewall of the gate structure; forming a second cap layer on the first cap layer; forming a third cap layer on the second cap layer; performing an etching process to partially remove the third cap layer, the second cap layer, and the first cap layer to form a first spacer and a second spacer on the sidewall of the gate structure; and forming a contact etch stop layer (CESL) on the substrate to cover the second spacer, wherein the third cap layer and the CESL comprise same deposition condition.

Abstract: An exemplary structure for a field effect transistor according to at least one embodiment comprises a substrate comprising a surface; a gate structure comprising sidewalls and a top surface over the substrate; a spacer adjacent to the sidewalls of the gate structure; a first contact etch stop layer over the spacer and extending along the surface of the substrate; an interlayer dielectric layer adjacent to the first contact etch stop layer, wherein a top surface of the interlayer dielectric layer is coplanar with the top surface of the gate structure; and a second contact etch stop layer over the top surface of the gate structure.

Abstract: A dual damascene process for forming conductive interconnects on an integrated circuit die. The process includes providing a layer (16) of porous, ultra low-k (ULK) dielectric material in which a via opening (30) is subsequently formed. A thermally degradable polymeric (“porogen”) material (42) is applied to the side wall sidewalls of the opening (30) such that the porogen material penetrates deeply into the porous ULK dielectric material (thereby sealing the pores and increasing the density thereof). Once a conductive material (36) has been provided with the opening (30) and polished back by means of chemical mechanical polishing (CMP), the complete structure is subjected to a curing step to cause the porogen material (44) with the ULK dielectric layer (16) to decompose and evaporate, thereby restoring the porosity (and low-k value) of the dielectric layer (16). Attached are a marked-up copy of the originally filed specification and a clean substitute specification in accordance with 37 C.F.R. §§1.

Abstract: A high-K/metal gate semiconductor device is provided with larger self-aligned contacts having reduced resistance. Embodiments include forming a first high-k metal gate stack on a substrate between source/drain regions, a second high-k metal gate stack on an STI region, and a first ILD between the metal gate stacks, forming an etch stop layer and a second ILD sequentially over the substrate, with openings in the second ILD over the metal gate stacks, forming spacers on the edges of the openings, forming a third ILD over the second ILD and the spacers, removing the first ILD over the source/drain regions, removing the etch stop layer, the second ILD, and the third ILD over the source/drain regions, adjacent the spacers, and over a portion of the spacers, forming first trenches, removing the third ILD over the second high-k metal gate stack and over a portion of the spacers, forming second trenches, and forming contacts in the first and second trenches.