Lateral Etching Of Intermediate Layer (i.e., Undercutting) Patents (Class 438/739)
  • Patent number: 10312568
    Abstract: A process for making a self-aligned waveguide includes: disposing a central conductor layer on a substrate; disposing a mask layer on the central conductor layer; forming a mask from the mask layer; removing a portion of the central conductor layer; forming an undercut interposed between substrate and the mask; forming a central conductor; disposing a ground conductor layer on the mask and the substrate; removing a portion of the ground conductor layer disposed on the mask; forming a ground plane conductor from the ground conductor layer in response to removing the portion of the ground conductor layer; and removing the mask to make the self-aligned waveguide in which the undercut provides self-alignment of each of the inner walls of the ground plane conductor to each of the sidewalls of the central conductor, and the ground plane conductor is electrically isolated from the central conductor.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: June 4, 2019
    Assignee: THE UNITED STATES OF AMERICA, AS REPRESENTED BY THE SECRETARY OF COMMERCE
    Inventor: David P. Pappas
  • Patent number: 9646844
    Abstract: A method for forming a stair-step structure in a substrate is provided. An organic mask is formed over the substrate. A hardmask with a top layer and sidewall layer is formed over the organic mask. The sidewall layer of the hard mask is removed while leaving the top layer of the hardmask. The organic mask is trimmed. The substrate is etched. The forming the hardmask, removing the sidewall layer, trimming the organic mask, and etching the substrate are repeated a plurality of times.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: May 9, 2017
    Assignee: Lam Research Corporation
    Inventors: Qian Fu, Hyun-Yong Yu
  • Patent number: 9508591
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: November 29, 2016
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 9224843
    Abstract: Disclosed is a trench formation technique wherein a first etch process forms an opening through a semiconductor layer into a semiconductor substrate and then a second etch process expands the portion of the opening within the substrate to form a trench. However, prior to the second etch, a doped region is formed in the substrate at the bottom surface of the opening. Then, the second etch is performed such that an undoped region of the substrate at the sidewalls of the opening is etched at a faster etch rate than the doped region, thereby ensuring that the trench has a relatively high aspect ratio. Also disclosed is a bipolar semiconductor device formation method. This method incorporates the trench formation technique so that a trench isolation region formed around a collector pedestal has a high aspect ratio and, thereby so that collector-to-base capacitance Ccb and collector resistance Rc are both minimized.
    Type: Grant
    Filed: March 31, 2015
    Date of Patent: December 29, 2015
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Benoit, James R. Elliott, Qizhi Liu
  • Patent number: 9202889
    Abstract: An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: December 1, 2015
    Assignee: Intel Corporation
    Inventors: Anand Murthy, Boyan Boyanov, Glenn A Glass, Thomas Hoffman
  • Patent number: 9184295
    Abstract: A method for manufacturing a suspended membrane in a single-crystal semiconductor substrate, including the steps of: forming in the substrate an insulating ring delimiting an active area, removing material from the active area, successively forming in the active area a first and a second layers, the second layer being a single-crystal semiconductor layer, etching a portion of the internal periphery of said ring down to a depth greater than the thickness of the second layer, removing the first layer so that the second layer formed a suspended membrane anchored in the insulating ring.
    Type: Grant
    Filed: November 12, 2013
    Date of Patent: November 10, 2015
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Stéphane Monfray, Thomas Skotnicki
  • Publication number: 20150140829
    Abstract: A method includes followings operations. A semiconductor substrate is provided. A photoresist is formed on the semiconductor substrate. Dopants are inserted into the photoresist to carbonize a portion of the photoresist. An etch steam is sprayed on the semiconductor substrate and the photoresist. A hole is formed at a surface of the photoresist by the etch steam. The etch steam is flowed into the hole so as to remove a portion of the photoresist at an interface between the semiconductor substrate and the photoresist. The photoresist is decorticated from the semiconductor substrate.
    Type: Application
    Filed: November 15, 2013
    Publication date: May 21, 2015
    Applicant: Taiwan Semiconductor Manufacturing Company Ltd.
    Inventors: PEI-WEN CHI, HSUEH-CHIN LU, SHIN HSIEN LIAO, HUNG-HSIN LIANG
  • Patent number: 9029178
    Abstract: A method for producing a device including plural cavities defined between a substrate in at least one given semiconductor material and a membrane resting on a top of insulating posts projecting from the substrate, the method allowing a height of the cavity or cavities to be adapted independently of a height of the insulating posts and allowing cavities of different heights to be formed.
    Type: Grant
    Filed: November 8, 2012
    Date of Patent: May 12, 2015
    Assignee: Commissariat à l'énergie atomique et aux énergies alternatives
    Inventors: Vincent Larrey, Jean-Philippe Polizzi
  • Patent number: 9018084
    Abstract: A tapered fin field effect transistor can be employed to provide enhanced electrostatic control of the channel. A stack of a semiconductor fin and a dielectric fin cap having substantially vertical sidewall surfaces is formed on an insulator layer. The sidewall surfaces of the semiconductor fin are passivated by an etch residue material from the dielectric fin cap with a tapered thickness profile such that the thickness of the etch residue material decreased with distance from the dielectric fin cap. An etch including an isotropic etch component is employed to remove the etch residue material and to physically expose lower portions of sidewalls of the semiconductor fin. The etch laterally etches the semiconductor fin and forms a tapered region at a bottom portion. The reduced lateral width of the bottom portion of the semiconductor fin allows greater control of the channel for a fin field effect transistor.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: April 28, 2015
    Assignee: International Business Machines Corporation
    Inventors: Josephine B. Chang, Michael A. Guillorn, Chung-Hsun Lin, Ryan M. Martin, Jeffrey W. Sleight
  • Publication number: 20150102465
    Abstract: Suspended structures are provided using selective etch technology. Such structures can be protected on all sides when the selective undercut etch is performed, thereby providing excellent control of feature geometry combined with superior material quality.
    Type: Application
    Filed: October 10, 2014
    Publication date: April 16, 2015
    Inventors: Robert Chen, James S. Harris, JR., Suyog Gupta
  • Patent number: 9006010
    Abstract: Radiation detectors and methods of fabricating radiation detectors are provided. One method includes mechanically polishing at least a first surface of a semiconductor wafer using a polishing sequence including a plurality of polishing steps, wherein a last polishing step of the polishing sequence includes polishing with a slurry having a grain size smaller than about 0.1 ?m to create a polished first surface. The method also includes applying (i) an encapsulation layer on a top of the polished first surface to seal the polished first surface and (ii) a photoresist layer on top of the encapsulation layer on the polished first surface. The method further includes creating undercuts of the encapsulation layer under the photoresist layer. The method additionally includes partially etching the polished first surface of the semiconductor via the openings in the photoresist layer and in the encapsulation layer to partially etch the semiconductor creating etched regions.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: April 14, 2015
    Assignee: General Electric Company
    Inventors: Arie Shahar, Eliezer Traub, Diego Sclar, Peter Rusian
  • Patent number: 8999839
    Abstract: A method of manufacturing a semiconductor structure, the method includes removing a portion of a dielectric filler from a first metal-containing layer formed over a semiconductor substrate to define an air-gap region according to a predetermined air-gap pattern. The method further includes filling the air-gap region with a decomposable filler and forming a dielectric capping layer over the first metal-containing layer. The method further includes decomposing the decomposable filler.
    Type: Grant
    Filed: May 15, 2013
    Date of Patent: April 7, 2015
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Hui Su, Cheng-Lin Huang, Jiing-Feng Yang, Zhen-Cheng Wu, Ren-Guei Wu, Dian-Hau Chen, Yuh-Jier Mii
  • Patent number: 8999744
    Abstract: Provided are an avalanche photodiode and a method of fabricating the same. The method of fabricating the avalanche photodiode includes sequentially forming a compound semiconductor absorption layer, a compound semiconductor grading layer, a charge sheet layer, a compound semiconductor amplification layer, a selective wet etch layer, and a p-type conductive layer on an n-type substrate through a metal organic chemical vapor deposition process.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: April 7, 2015
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Mi-Ran Park, O-Kyun Kwon
  • Patent number: 8999844
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each of which including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: April 7, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 9000566
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: February 5, 2014
    Date of Patent: April 7, 2015
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8946007
    Abstract: After formation of a gate electrode, a source trench and a drain trench are formed down to an upper portion of a bottom semiconductor layer having a first semiconductor material of a semiconductor-on-insulator (SOI) substrate. The source trench and the drain trench are filled with at least a second semiconductor material that is different from the first semiconductor material to form source and drain regions. A planarized dielectric layer is formed and a handle substrate is attached over the source and drain regions. The bottom semiconductor layer is removed selective to the second semiconductor material, the buried insulator layer, and a shallow trench isolation structure. The removal of the bottom semiconductor layer exposes a horizontal surface of the buried insulator layer present between source and drain regions on which a conductive material layer is formed as a back gate electrode.
    Type: Grant
    Filed: February 7, 2013
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Bruce B. Doris, Kangguo Cheng, Ali Khakifirooz, Douglas C. La Tulipe, Jr.
  • Patent number: 8940648
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2), chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: August 12, 2013
    Date of Patent: January 27, 2015
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8901009
    Abstract: A memory device includes a lower interconnection in a semiconductor substrate, the lower interconnection being made of a material different from the semiconductor substrate, a selection element on the lower interconnection, and a memory element on the selection element.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 2, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jaekyu Lee, Kiseok Suh, Tae Eung Yoon
  • Patent number: 8889564
    Abstract: A mandrel having vertical planar surfaces is formed on a single crystalline semiconductor layer. An epitaxial semiconductor layer is formed on the single crystalline semiconductor layer by selective epitaxy. A first spacer is formed around an upper portion of the mandrel. The epitaxial semiconductor layer is vertically recessed employing the first spacers as an etch mask. A second spacer is formed on sidewalls of the first spacer and vertical portions of the epitaxial semiconductor layer. Horizontal bottom portions of the epitaxial semiconductor layer are etched from underneath the vertical portions of the epitaxial semiconductor layer to form a suspended ring-shaped semiconductor fin that is attached to the mandrel. A center portion of the mandrel is etched employing a patterned mask layer that covers two end portions of the mandrel. A suspended semiconductor fin is provided, which is suspended by a pair of support structures.
    Type: Grant
    Filed: August 31, 2012
    Date of Patent: November 18, 2014
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, James J. Demarest, Balasubramanian S. Haran
  • Patent number: 8883651
    Abstract: A method of manufacturing a transistor of a semiconductor device, the method including forming a gate pattern on a semiconductor substrate, forming a spacer on a sidewall of the gate pattern, wet etching the semiconductor substrate to form a first recess in the semiconductor substrate, wherein the first recess is adjacent to the spacer, and wet etching the first recess to form a second recess in the semiconductor substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: November 11, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seokhoon Kim, Sangsu Kim, Chung Geun Koh, Byeongchan Lee, Sunghil Lee, Jinyeong Joe
  • Patent number: 8883575
    Abstract: A process may include forming a mask directly on and above a region selected as an initial semiconductor fin on a substrate and reducing the initial semiconductor fin forming a semiconductor fin that is laterally thinned from the initial semiconductor fin. The process may be carried out causing the mask to recede to a greater degree in the lateral direction than the vertical direction. In various embodiments, the process may include removing material from the fin semiconductor to achieve a thinned semiconductor fin, which has receded beneath the shadow of the laterally receded mask. Electronic devices may include the thinned semiconductor fin as part of a semiconductor device.
    Type: Grant
    Filed: April 5, 2012
    Date of Patent: November 11, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Mark Fischer, T. Earl Allen, H. Montgomery Manning
  • Patent number: 8877652
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 2, 2014
    Date of Patent: November 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8853044
    Abstract: A phase-change random access memory (PCRAM) device includes a semiconductor substrate; switching elements formed on the semiconductor substrate; a plurality of phase-change structures formed on the switching elements; and heat absorption layers buried between the plurality of phase-change structures, wherein the plurality of phase-change structures are insulated from the heat absorption layers.
    Type: Grant
    Filed: November 11, 2013
    Date of Patent: October 7, 2014
    Assignee: SK Hynix Inc.
    Inventor: Nam Kyun Park
  • Patent number: 8791017
    Abstract: Disclosed herein are various methods of forming conductive structures, such as conductive lines and via, on an integrated circuit device using a spacer erosion technique. In one example, the method includes forming a patterned hard mask layer above a layer of insulating material, the patterned hard mask having a hard mask opening, forming an erodible spacer in the hard mask opening to thereby define a spacer opening and performing at least one etching process through the spacer opening on the layer of insulating material to define a trench therein for a conductive structure, wherein the erodible spacer is substantially eroded away during the at least one etching process.
    Type: Grant
    Filed: October 26, 2011
    Date of Patent: July 29, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventor: Gunter Grasshoff
  • Patent number: 8790523
    Abstract: A method for manufacturing a magnetic head, includes forming, on a non-magnetic film, a main magnetic pole film with a body portion and a write magnetic pole portion continuous with the body portion, and etching the non-magnetic film such that an undercut is formed around the body portion and beneath the write magnetic pole portion. The undercut penetrates beneath the write magnetic pole portion in a track width direction. The method includes wet etching the non-magnetic film beneath the main magnetic pole film at the undercut, the undercut being at least partially filled with an organic filler. The method also includes, after removal of the organic filler, covering at least both sides of the write magnetic pole portion with a magnetic gap film, and forming a write shield film adjacent to the magnetic gap film. The undercut forms a hollow in the non-magnetic film underlying the write magnetic pole portion.
    Type: Grant
    Filed: January 7, 2009
    Date of Patent: July 29, 2014
    Assignee: TDK Corporation
    Inventors: Hisayoshi Watanabe, Yusuke Ide
  • Patent number: 8753974
    Abstract: Structures and methods for the dissipation of charge build-up during the formation of cavities in semiconductor substrates.
    Type: Grant
    Filed: June 20, 2007
    Date of Patent: June 17, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Brian Griffin, Russ Benson
  • Patent number: 8722537
    Abstract: MEMS devices and methods for utilizing sacrificial layers are provided. An embodiment comprises forming a first sacrificial layer and a second sacrificial layer over a substrate, wherein the second sacrificial layer acts as an adhesion layer. Once formed, the first sacrificial layer and the second sacrificial layer are patterned such that the second sacrificial layer is undercut to form a step between the first sacrificial layer and the second sacrificial layer. A top capacitor electrode is formed over the second sacrificial layer, and the first sacrificial layer and the second sacrificial layer are removed in order to free the top capacitor electrode.
    Type: Grant
    Filed: January 13, 2010
    Date of Patent: May 13, 2014
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yao-Te Huang, Chia-Hua Chu, Yu-Nu Hsu, Chun-Wen Cheng, Li-Chung Peng
  • Patent number: 8697528
    Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: April 15, 2014
    Assignee: International Business Machines Corporation
    Inventor: Thomas W. Dyer
  • Patent number: 8686542
    Abstract: A compliant monopolar micro device transfer head array and method of forming a compliant monopolar micro device transfer array from an SOI substrate are described. In an embodiment, the micro device transfer head array including a base substrate and a patterned silicon layer over the base substrate. The patterned silicon layer may include a silicon interconnect and an array of silicon electrodes electrically connected with the silicon interconnect. Each silicon electrode includes a mesa structure protruding above the silicon interconnect, and each silicon electrode is deflectable into a cavity between the base substrate and the silicon electrode. A dielectric layer covers a top surface of each mesa structure.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: April 1, 2014
    Assignee: LuxVue Technology Corporation
    Inventors: Dariusz Golda, Andreas Bibl
  • Patent number: 8679986
    Abstract: Provided is a method for manufacturing a semiconductor device so as not expose a semiconductor layer to moisture and the number of masks is reduced. For example, a first conductive film, a first insulating film, a semiconductor film, a second conductive film, and a mask film are formed. The first mask film is processed to form a first mask layer. Dry etching is performed on the first insulating film, the semiconductor film, and the second conductive film with the use of the first mask layer to form a thin film stack body, so that a surface of the first conductive film is at least exposed. Sidewall insulating layers covering side surfaces of the thin film stack body are formed. The first conductive film is side-etched to form a first electrode. A second electrode layer is formed with the second mask layer.
    Type: Grant
    Filed: September 24, 2011
    Date of Patent: March 25, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Takafumi Mizoguchi, Kojiro Shiraishi
  • Patent number: 8652971
    Abstract: A MEMS device having a device cavity in a substrate has a cavity etch monitor proximate to the device cavity. An overlying layer including dielectric material is formed over the substrate. A monitor scale is formed in or on the overlying layer. Access holes are etched through the overlying layer and a cavity etch process forms the device cavity and a monitor cavity. The monitor scale is located over a lateral edge of the monitor cavity. The cavity etch monitor includes the monitor scale and monitor cavity, which allows visual measurement of a lateral width of the monitor cavity; the lateral dimensions of the monitor cavity being related to lateral dimensions of the device cavity.
    Type: Grant
    Filed: March 5, 2012
    Date of Patent: February 18, 2014
    Assignee: Texas Instruments Incorporated
    Inventors: Ricky Alan Jackson, Walter Baker Meinel, Karen Hildegard Ralston Kirmse
  • Patent number: 8643059
    Abstract: A substrate structure and method of manufacturing the same are disclosed. The substrate structure may includes a substrate on which a plurality of protrusions are formed on one surface thereof and a plurality of buffer layers formed according to a predetermined pattern and formed spaced apart from each other on the plurality of protrusions.
    Type: Grant
    Filed: January 3, 2011
    Date of Patent: February 4, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jun-youn Kim, Su-hee Chae, Hyun-gi Hong, Young-jo Tak
  • Patent number: 8609492
    Abstract: Methods of forming, devices, and apparatus associated with a vertical memory cell are provided. One example method of forming a vertical memory cell can include forming a semiconductor structure over a conductor line. The semiconductor structure can have a first region that includes a first junction between first and second doped materials. An etch-protective material is formed on a first pair of sidewalls of the semiconductor structure above the first region. A volume of the first region is reduced relative to a body region of the semiconductor structure in a first dimension.
    Type: Grant
    Filed: July 27, 2011
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Kurt D. Beigel, Sanh D. Tang
  • Patent number: 8609536
    Abstract: Apparatuses and methods for stair step formation using at least two masks, such as in a memory device, are provided. One example method can include forming a first mask over a conductive material to define a first exposed area, and forming a second mask over a portion of the first exposed area to define a second exposed area, the second exposed area is less than the first exposed area. Conductive material is removed from the second exposed area. An initial first dimension of the second mask is less than a first dimension of the first exposed area and an initial second dimension of the second mask is at least a second dimension of the first exposed area plus a distance equal to a difference between the initial first dimension of the second mask and a final first dimension of the second mask after a stair step structure is formed.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: December 17, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Chang Wan Ha, Graham R. Wolstenholme, Deepak Thimmegowda
  • Patent number: 8599616
    Abstract: A three-dimensional (3D) non-volatile memory (NVM) array including spaced-apart horizontally-disposed bitline structures arranged in vertical stacks, each bitline structures including a mono-crystalline silicon beam and a charge storage layer entirely surrounding the beam. Vertically-oriented wordline structures are disposed next to the stacks such that each wordline structure contacts corresponding portions of the charge storage layers. NVM memory cells are formed at each bitline/wordline intersection, with corresponding portions of each bitline structure forming each cell's channel region. The bitline structures are separated by air gaps, and each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: December 3, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Avi Strum
  • Patent number: 8586395
    Abstract: Here, an apparatus is provided. The apparatus generally comprises a substrate and a thermopile. The thermopile includes a cavity that is etched into the substrate, a functional area that is formed over the substrate (where the cavity is generally coextensive with the functional area), and a metal ring formed over the substrate along the periphery of the functional area (where the metal ring is thermally coupled to the substrate).
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: November 19, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: Walter Meinel, Kalin V. Lazarov
  • Patent number: 8569182
    Abstract: A method of fabricating a three-dimensional semiconductor device includes forming a stacked structure, and the stacked structure includes a first layer, a second layer, a third layer, and a fourth layer sequentially stacked on a substrate. The method also includes forming a sacrificial spacer on a sidewall of the stacked structure such that the sacrificial spacer exposes a sidewall of the third layer, and recessing the exposed sidewall of the third layer thereby forming a recess region between the second and fourth layers.
    Type: Grant
    Filed: January 3, 2012
    Date of Patent: October 29, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Yong Park, Eunsun Youm
  • Patent number: 8530361
    Abstract: A method for depositing a silicon containing film on a substrate using an organoaminosilane is described herein. The organoaminosilanes are represented by the formulas: wherein R is selected from a C1-C10 linear, branched, or cyclic, saturated or unsaturated alkyl group with or without substituents; a C5-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, or a silyl group in formula C with or without substituents, R1 is selected from a C3-C10 linear, branched, cyclic, saturated or unsaturated alkyl group with or without substituents; a C6-C10 aromatic group with or without substituents, a C3-C10 heterocyclic group with or without substituents, a hydrogen atom, a silyl group with substituents and wherein R and R1 in formula A can be combined into a cyclic group and R2 representing a single bond, (CH2)n chain, a ring, C3-C10 branched alkyl, SiR2, or SiH2.
    Type: Grant
    Filed: December 22, 2010
    Date of Patent: September 10, 2013
    Assignee: Air Products and Chemicals, Inc.
    Inventors: Manchao Xiao, Xinjian Lei, Heather Regina Bowen, Mark Leonard O'Neill
  • Patent number: 8530350
    Abstract: Methods for forming semiconductor structures are disclosed, including a method that involves forming sets of conductive material and insulating material, forming a first mask over the sets, forming a first number of contact regions, forming a second mask over a first region of the sets, and removing material from of the sets in a second, exposed region laterally adjacent the first region to form a second number of contact regions. Another method includes forming first and second contact regions on portions of sets of conductive materials and insulating materials, each of the second contact regions more proximal to an underlying substrate than each of the first contact regions. Apparatuses such as memory devices including laterally adjacent first and second regions each including contact regions of a different portion of a plurality of conductive materials and related methods of forming such devices are also disclosed.
    Type: Grant
    Filed: June 2, 2011
    Date of Patent: September 10, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Eric H. Freeman, Michael A. Smith
  • Patent number: 8507386
    Abstract: A method of etching recesses into silicon prior to formation of embedded silicon alloy source/drain regions. The recess etch includes a plasma etch component, using an etch chemistry of a primary fluorine-based or chlorine-based etchant, in combination with a similar concentration of hydrogen bromide. The concentration of both the primary etchant and the hydrogen bromide is relatively low; a diluent of an inert gas or oxygen is added to the reactive species. Loading effects on the undercut of the recess etch are greatly reduced, resulting in reduced transistor performance variation.
    Type: Grant
    Filed: September 13, 2010
    Date of Patent: August 13, 2013
    Assignee: Texas Instruments Incorporated
    Inventors: David Gerald Farber, Tom Lii
  • Patent number: 8501609
    Abstract: A method for generating three-dimensional (3D) non-volatile memory (NVM) arrays includes forming multiple parallel horizontally-disposed mono-crystalline silicon beams that are spaced apart and arranged in a vertical stack (e.g., such that an elongated horizontal air gap is defined between each adjacent beam in the stack), forming separate charge storage layers on each of the mono-crystalline silicon beams such that each charge storage layer includes a high-quality thermal oxide layer that entirely covers (i.e., is formed on the upper, lower and opposing side surfaces of) each of the mono-crystalline silicon beams, and then forming multiple vertically-disposed poly-crystalline silicon wordline structures next to the stack such that each wordline structure is connected to each of the bitline structures in the stack by way of corresponding portions of the separate charge storage layers. The memory cells are accessed during read/write operations by way of the corresponding wordline and bitline structures.
    Type: Grant
    Filed: February 2, 2012
    Date of Patent: August 6, 2013
    Assignee: Tower Semiconductor Ltd.
    Inventors: Yakov Roizin, Avi Strum
  • Patent number: 8492218
    Abstract: A first liner and a second liner are formed such that a peripheral portion of the second liner overlies a peripheral portion of the first liner. A photoresist layer is applied and patterned such that a sidewall of a patterned photoresist layer overlies an overlapping peripheral portion of the second liner An isotropic dry etch is performed to laterally etch the overlapping peripheral portion of the second liner from below the patterned photoresist layer. The patterned photoresist is subsequently removed, and a structure without an overlap of the first and second liners is provided.
    Type: Grant
    Filed: April 3, 2012
    Date of Patent: July 23, 2013
    Assignees: International Business Machines Corporation, Global Foundries, Inc.
    Inventors: Ming Cai, Aimin Xing, Chandra Reddy
  • Patent number: 8470629
    Abstract: A structure which prevents thinning and disconnection of a wiring is provided, in a micromachine (MEMS structure body) formed with a surface micromachining technology. A wiring (upper auxiliary wiring) over a sacrificial layer is electrically connected to a different wiring (upper connection wiring) over the sacrificial layer, so that thinning, disconnection, and the like of the wiring formed over the sacrificial layer at a step portion generated due to the thickness of the sacrificial layer can be prevented. The wiring over the sacrificial layer is formed of the same conductive film as an upper driving electrode which is a movable electrode and is thus thin. However, the different wiring is formed over a structural layer, which is formed by a CVD method and has a rounded step, and has a thickness of 200 nm to 1 ?m, whereby thinning, disconnection, and the like of the wiring can be further prevented.
    Type: Grant
    Filed: July 25, 2011
    Date of Patent: June 25, 2013
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Mayumi Mikami, Konami Izumi
  • Patent number: 8461054
    Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.
    Type: Grant
    Filed: October 7, 2008
    Date of Patent: June 11, 2013
    Assignee: LG Display Co., Ltd.
    Inventors: Kye-Chan Song, Jeong Oh Kim, Young Kwon Kang
  • Patent number: 8461028
    Abstract: A method and semiconductor device for synthesizing graphene using ion implantation of carbon. Carbon is implanted in a metal using ion implantation. After the carbon is distributed in the metal, the metal is annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the surface of the metal. The metal/graphene surface is then transferred to a dielectric layer in such a manner that the graphene layer is placed on top of the dielectric layer. The metal layer is then removed. Alternatively, recessed regions are patterned and etched in a dielectric layer located on a substrate. Metal is later formed in these recessed regions. Carbon is then implanted into the metal using ion implantation. The metal may then be annealed and cooled in order to precipitate the carbon from the metal to form a layer of graphene on the metal's surface.
    Type: Grant
    Filed: October 8, 2012
    Date of Patent: June 11, 2013
    Assignee: Board of Regents, The University of Texas System
    Inventors: Luigi Colombo, Robert M. Wallace, Rodney S. Ruoff
  • Patent number: 8445978
    Abstract: A micro or nano electromechanical transducer device formed on a semiconductor substrate comprises a movable structure which is arranged to be movable in response to actuation of an actuating structure. The movable structure comprises a mechanical structure comprising at least one mechanical layer having a first thermal response characteristic and a first mechanical stress response characteristic, at least one layer of the actuating structure, the at least one layer having a second thermal response characteristic different to the first thermal response characteristic and a second mechanical stress response characteristic different to the first mechanical stress response characteristic, a first compensation layer having a third thermal response characteristic and a third mechanical stress characteristic, and a second compensation layer having a fourth thermal response characteristic and a fourth mechanical stress response characteristic.
    Type: Grant
    Filed: November 25, 2009
    Date of Patent: May 21, 2013
    Assignees: Freescale Semiconductor, Inc., Commissariat à l'Energie Atomique et aux Energies Alternatives (CEA)
    Inventors: Francois Perruchot, Emmanuel Defay, Patrice Rey, Lianjun Liu, Sergio Pacheco
  • Patent number: 8435846
    Abstract: Transistor devices and methods of their fabrication are disclosed. In one method, a dummy gate structure is formed on a substrate. Bottom portions of the dummy gate structure are undercut. In addition, stair-shaped, raised source and drain regions are formed on the substrate and within at least one undercut formed by the undercutting. The dummy gate structure is removed and a replacement gate is formed on the substrate.
    Type: Grant
    Filed: October 3, 2011
    Date of Patent: May 7, 2013
    Assignee: International Business Machines Corporation
    Inventors: Kangguo Cheng, Bruce B. Doris, Balasubramanian S. Haran, Ali Khakifirooz, Pranita Kulkarni
  • Patent number: 8415179
    Abstract: A light emitting diode and a light emitting diode (LED) manufacturing method are disclosed. The LED comprises a substrate; a first n-type GaN layer; a second n-type GaN layer; an active layer; and a p-type GaN layer formed on the substrate in sequence; the second n-type GaN layers has a bottom surface interfacing with the first n-type GaN layer, a rim of the bottom surface has a roughened exposed portion, and Ga—N bonds on the bottom surface has an N-face polarity.
    Type: Grant
    Filed: December 2, 2011
    Date of Patent: April 9, 2013
    Assignee: Advanced Optoelectronic Technology, Inc.
    Inventors: Tzu-Chien Hung, Shun-Kuei Yang, Chia-Hui Shen
  • Patent number: 8399876
    Abstract: A semiconductor die includes at least one first region and at least one second region. The at least one first region is configured to emit light having at least a first wavelength. The at least one second region is configured to emit light having at least a second wavelength, which is different from the first wavelength.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: March 19, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Taek Kim
  • Patent number: 8377785
    Abstract: Disclosed is a transistor that incorporates epitaxially deposited source/drain semiconductor films and a method for forming the transistor. A crystallographic etch is used to form recesses between a channel region and trench isolation regions in a silicon substrate. Each recess has a first side, having a first profile, adjacent to the channel region and a second side, having a second profile, adjacent to a trench isolation region. The crystallographic etch ensures that the second profile is angled so that all of the exposed recess surfaces comprise silicon. Thus, the recesses can be filled by epitaxial deposition without divot formation. Additional process steps can be used to ensure that the first side of the recess is formed with a different profile that enhances the desired stress in the channel region.
    Type: Grant
    Filed: April 6, 2011
    Date of Patent: February 19, 2013
    Assignee: International Business Machines Corporation
    Inventor: Thomas W. Dyer