Charge Transfer Device (e.g., Ccd, Etc.) Patents (Class 438/75)
  • Patent number: 7863076
    Abstract: Disclosed herein is a solid-state image pickup device which includes: a light-receiving unit for photoelectric conversion of incident light; and a charge transfer unit of an n-channel insulating gate type configured to transfer a signal charge photoelectrically converted in the light-receiving unit; wherein the charge transfer unit has an insulating film formed on a transfer electrode and having a negative fixed charge.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: January 4, 2011
    Assignee: Sony Corporation
    Inventor: Susumu Hiyama
  • Patent number: 7863077
    Abstract: An image sensor and method of manufacturing the same are disclosed. A semiconductor substrate can be prepared comprising a photodiode region, a transistor region, and a floating diffusion region. A gate dielectric can be disposed under a surface of the semiconductor substrate in the transistor region. A first dielectric pattern can be provided having a portion above and a portion below the surface of the semiconductor substrate in the photodiode and the floating diffusion regions. A second dielectric can be disposed under the gate dielectric. The second dielectric can extend the depth of the gate dielectric into the semiconductor substrate to space the movement path of photoelectrons from the photodiode region to the floating diffusion region.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: January 4, 2011
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Dong Bin Park
  • Patent number: 7842985
    Abstract: Disclosed is a CMOS image sensor including a gate electrode of a finger type transfer transistor for controlling the saturation state of a floating diffusion region according to the luminance level (i.e. low luminance or high luminance). The CMOS image sensor includes first and second photodiode regions for generating electrons in response to incident light, and a transfer transistor positioned between the first and second photodiodes for receiving the generated electrons transferred from the first and/or second photodiode.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: November 30, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Keun Hyuk Lim
  • Patent number: 7838319
    Abstract: There are provided a MOS transistor and a manufacturing method thereof. The MOS transistor includes a substrate on which an insulating layer is formed, a gate embedded in the insulating layer, wherein the top surface of the gate is exposed, a gate oxide layer formed on the insulating layer and the gate, a silicon layer formed on the gate oxide layer, and a source region and a drain region formed in the silicon layer to be in contact with the gate oxide layer.
    Type: Grant
    Filed: November 3, 2008
    Date of Patent: November 23, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: Yun Hyung Sun
  • Patent number: 7829361
    Abstract: The invention relates to an imaging device having a pixel cell with a transparent conductive material interconnect line for focusing incident light onto a photosensor and providing an electrical connection to pixel circuitry, and the method of making the same.
    Type: Grant
    Filed: February 5, 2008
    Date of Patent: November 9, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: David Wells
  • Publication number: 20100264502
    Abstract: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning of the detector using standard semiconductor processing.
    Type: Application
    Filed: October 19, 2009
    Publication date: October 21, 2010
    Applicant: US Gov't Represented by the Secretary of the Navy Office of Naval Research (ONR/NRL) code OOCCIP
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Patent number: 7816169
    Abstract: Disclosed is an ordered microelectronic fabrication sequence in which color filters are formed by conformal deposition directly onto a photodetector array of a CCD, CID, or CMOS imaging device to create a concave-up pixel surface, and, overlayed with a high transmittance planarizing film of specified index of refraction and physical properties which optimize light collection to the photodiode without additional conventional microlenses. The optically flat top surface serves to encapsulate and protect the imager from chemical and thermal cleaning treatment damage, minimizes topographical underlayer variations which would aberrate or cause reflection losses of images formed on non-planar surfaces, and, obviates residual particle inclusions induced during dicing and packaging. A CCD imager is formed by photolithographically patterning a planar-array of photodiodes on a semiconductor substrate. The photodiode array is provided with metal photoshields, passivated, and, color filters are formed thereon.
    Type: Grant
    Filed: December 31, 2008
    Date of Patent: October 19, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yang-Tung Fan, Chiou-Shian Peng, Cheng-Yu Chu, Shih-Jane Lin, Yen-Ming Chen, Fu-Jier Fan, Kuo-Wei Li
  • Patent number: 7816170
    Abstract: A dual-pixel full color CMOS imager comprises a two-photodiode stack including an n doped substrate, a bottom photodiode, and a top photodiode. The bottom photodiode has a bottom p doped layer at a first depth overlying the substrate and a bottom n doped layer cathode overlying the bottom p doped layer. The top photodiode has a top p doped layer overlying the bottom n doped layer and a top n doped layer cathode overlying the top p doped layer. A single photodiode including a bottom p doped layer overlies the substrate at a third depth. The third depth is less than, or equal to the first depth. A bottom n doped layer overlies the bottom p doped layer, a top p doped layer directly overlies the bottom n doped layer without an intervening layer, and a top n doped layer overlies the top p doped layer.
    Type: Grant
    Filed: October 14, 2008
    Date of Patent: October 19, 2010
    Assignee: Sharp Laboratories of America, Inc.
    Inventors: Jong-Jan Lee, Jon M. Speigle, Douglas J. Tweet
  • Patent number: 7811850
    Abstract: Isolation methods and devices for isolating pixels of an image sensor pixel. The isolation structure and methods include forming a biased gate over a field isolation region and adjacent a pixel of an image sensor. The isolation methods also include forming an isolation gate over substantial portions of a field isolation region to isolate pixels in an array of pixels.
    Type: Grant
    Filed: September 29, 2006
    Date of Patent: October 12, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Chandra Mouli, Howard Rhodes
  • Patent number: 7790496
    Abstract: An imaging apparatus includes (a) a full-frame, charge-coupled device having (i) a conductive layer of a first dopant type; (ii) a plurality of pixels arranged as a charge-coupled device in the conductive layer that collects charge in response to incident light and transfers the collected charge; (iii) an overflow drain of a dopant type opposite the first type disposed in the conductive layer and laterally adjacent to each pixel; and the apparatus having (b) a voltage supply connected to the lateral overflow drain that is at a first voltage during readout and at a second voltage that is lower than the first voltage during integration.
    Type: Grant
    Filed: September 23, 2008
    Date of Patent: September 7, 2010
    Assignee: Eastman Kodak Company
    Inventor: Eric J. Meisenzahl
  • Patent number: 7785918
    Abstract: An image device which includes reflowed color filters. Reflowed color filters may be formed by heat treating preliminary color filters. When preliminary color filters are reflowed, color filters of different colors may be formed continuous with each other. Contiguous color filters in an image device may reduce manufacturing costs, maximize optical efficiency, minimize noise, and/or minimize crosstalk.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: August 31, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Young-Je Yun
  • Patent number: 7777229
    Abstract: A method for fabricating a back-illuminated semiconductor imaging device and resulting imaging device is disclosed, which includes the steps providing a substrate having a front surface and a back surface; growing an epitaxial layer substantially overlying the front surface of the substrate; forming at least one barrier layer substantially within the epitaxial layer; fabricating at least one imaging structure overlying and extending into the epitaxial layer, the imaging structure at least one charge transfer region, the at least one barrier layer substantially underlying the at least one charge transfer region, wherein light incident on the back surface of the substrate generates charge carriers which are diverted away from the at least one charge transfer region by the at least one barrier layer. At least a portion of the epitaxial layer is grown using an epitaxial lateral overgrowth technique.
    Type: Grant
    Filed: August 24, 2007
    Date of Patent: August 17, 2010
    Assignee: Sarnoff Corporation
    Inventors: Pradyumna Kumar Swain, Mahalingam Bhaskaran, Peter Levine, Norman Goldsmith
  • Publication number: 20100201859
    Abstract: A pinned photodiode with improved short wavelength light response. In exemplary embodiments of the invention, a gate oxide is formed over a doped, buried region in a semiconductor substrate. A gate conductor is formed on top of the gate oxide. The gate conductor is transparent, and in one embodiment is a layer of indium-tin oxide. The transparent conductor can be biased to reduce the need for a surface dopant in creating a pinned photodiode region. The biasing of the transparent conductor produces a hole-rich accumulation region near the surface of the substrate. The gate conductor material permits a greater amount of charges from short wavelength light to be captured in the photo-sensing region in the substrate, and thereby increases the quantum efficiency of the photosensor.
    Type: Application
    Filed: February 12, 2010
    Publication date: August 12, 2010
    Inventors: Chandra Mouli, Howard E. Rhodes
  • Publication number: 20100181602
    Abstract: Disclosed is a solid-state image sensor including a photoelectric converter, a charge detector, and a transfer transistor. The photoelectric converter stores a signal charge that is subjected to photoelectric conversion. The charge detector detects the signal charge. The transfer transistor transfers the signal charge from the photoelectric converter to the charge detector. In the solid-state image sensor, the transfer transistor includes a gate insulating film, a gate electrode formed on the gate insulating film, a first spacer formed on a sidewall of the gate electrode on a side of the photoelectric converter, and a second spacer formed on another sidewall of the gate electrode on a side of the charge detector. The first spacer is longer than the second spacer.
    Type: Application
    Filed: January 13, 2010
    Publication date: July 22, 2010
    Applicant: Sony Corporation
    Inventor: Tetsuya Oishi
  • Patent number: 7759157
    Abstract: In a solid-state image pick-up device in which a photoelectric converting section formed on a semiconductor substrate and a gate oxide film of a transfer path of a charge coupled device (CCD) which is close to the photoelectric converting section are constituted by a laminated film comprising a silicon oxide film (SiO) and a silicon nitride film (SiN), the gas oxide film has a single layer structure in which at least an end on the photoelectric converting section side of the gate oxide film does not contain the silicon nitride film.
    Type: Grant
    Filed: February 19, 2008
    Date of Patent: July 20, 2010
    Assignee: FujiFilm Corporation
    Inventors: Eiichi Okamoto, Shunsuke Tanaka, Shinji Uya
  • Publication number: 20100178725
    Abstract: P type semiconductor well regions 8 and 9 for device separation are provided in an upper and lower two layer structure in conformity with the position of a high sensitivity type photodiode PD, and the first P type semiconductor well region 8 at the upper layer is provided in the state of being closer to the pixel side than an end portion of a LOCOS layer 1A, for limiting a dark current generated at the end portion of the LOCOS layer 1A. In addition, the second P type semiconductor well region 9 at the lower layer is formed in a narrow region receding from the photodiode PD, so that the depletion layer of the photodiode PD is prevented from being obstructed, and the depletion is secured in a sufficiently broad region, whereby enhancement of the sensitivity of the photodiode PD can be achieved.
    Type: Application
    Filed: March 29, 2010
    Publication date: July 15, 2010
    Applicant: SONY CORPORATION
    Inventors: Hiroaki FUJITA, Ryoji SUZUKI, Nobuo NAKAMURA, Yasushi MARUYAMA
  • Publication number: 20100176272
    Abstract: A photoelectric conversion device includes a photoelectric conversion unit which is arranged in a semiconductor substrate, a charge holding portion which is arranged in the semiconductor substrate and temporarily holds a charge generated by the photoelectric conversion unit, a first transfer electrode which is arranged at a position above the semiconductor substrate to transfer a charge generated by the photoelectric conversion unit to the charge holding portion, a charge-voltage converter which is arranged in the semiconductor substrate and converts a charge into a voltage, and a second transfer electrode which is arranged at a position above the semiconductor substrate to transfer a charge held by the charge holding portion to the charge-voltage converter, and the first transfer electrode is arranged to cover the charge holding portion, and not to overlap the second transfer electrode when viewed from a direction perpendicular to the upper surface of the semiconductor substrate.
    Type: Application
    Filed: December 22, 2009
    Publication date: July 15, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventor: Masatsugu Itahashi
  • Patent number: 7754557
    Abstract: A method for manufacturing a vertical CMOS image sensor related to a semiconductor device is disclosed. A high-temperature double annealing process and/or an additional passivation nitride film are selectively applied in order to improve dark leakage characteristics and also to prevent or reduce an incidence of circular defects, thereby enhancing the quality and reliability of the vertical CMOS image sensor.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: July 13, 2010
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Jeong Su Park
  • Publication number: 20100171857
    Abstract: A method of manufacturing a solid-state imaging device. Light-receiving sensor portions each constituting a pixel in the form of a matrix is arranged. The matrix has columns aligned in a vertical direction and rows aligned in a horizontal direction. Charge-transfer portions are formed on either side of the columns of said pixels. Transfer electrodes in said charge-transfer portions are formed to include a first transfer electrode formed of a first electrode layer and a second transfer electrode formed by electrically connecting the first electrode layer and a second electrode layer through a contact. The second transfer electrode being disposed in the vertical direction above the charge-transfer portion in a vicinity of the contact to decrease the width of the charge-transfer portions in the horizontal direction and increase the light receiving sensor portions in the vertical direction.
    Type: Application
    Filed: March 15, 2010
    Publication date: July 8, 2010
    Applicant: Sony Corporation
    Inventor: Hideo Kanbe
  • Patent number: 7750382
    Abstract: A deep implanted region of a first conductivity type located below a transistor array of a pixel sensor cell and adjacent a doped region of a second conductivity type of a photodiode of the pixel sensor cell is disclosed. The deep implanted region reduces surface leakage and dark current and increases the capacitance of the photodiode by acting as a reflective barrier to photo-generated charge in the doped region of the second conductivity type of the photodiode. The deep implanted region also provides improved charge transfer from the charge collection region of the photodiode to a floating diffusion region adjacent the gate of the transfer transistor.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: July 6, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Howard Rhodes
  • Patent number: 7749798
    Abstract: An image sensing circuit and method is disclosed, wherein a photodiode is formed in a substrate through a series of angled implants. The photodiode is formed by a first, second and third implant, wherein at least one of the implants are angled so as to allow the resulting photodiode to extend out beneath an adjoining gate. Under an alternate embodiment, a fourth implant is added, under an increased implant angle, in the region of the second implant. The resulting photodiode structure substantially reduces or eliminates transfer gate subthreshold leakage.
    Type: Grant
    Filed: March 31, 2005
    Date of Patent: July 6, 2010
    Assignee: Aptina Imaging Corporation
    Inventors: Howard E. Rhodes, Richard A. Mauritzson, Inna Patrick
  • Patent number: 7749799
    Abstract: Methods for bringing or exposing metal pads or traces to the backside of a backside-illuminated imager allow the pads or traces to reside on the illumination side for electrical connection. These methods provide a solution to a key packaging problem for backside thinned imagers. The methods also provide alignment marks for integrating color filters and microlenses to the imager pixels residing on the frontside of the wafer, enabling high performance multispectral and high sensitivity imagers, including those with extremely small pixel pitch. In addition, the methods incorporate a passivation layer for protection of devices against external contamination, and allow interface trap density reduction via thermal annealing. Backside-illuminated imagers with illumination side electrical connections are also disclosed.
    Type: Grant
    Filed: November 15, 2006
    Date of Patent: July 6, 2010
    Assignee: California Institute of Technology
    Inventor: Bedabrata Pain
  • Patent number: 7745250
    Abstract: An image sensor and manufacturing process thereof are provided. An image sensor according to an embodiment comprises a first wafer formed with a photodiode cell without a microlens and a second wafer formed with a circuit part including transistor and a capacitor. The first wafer is stacked on the second wafer such that a connecting electrode can be used to electrically connect the photodiode cell of the first wafer to the circuit part of the second wafer.
    Type: Grant
    Filed: December 26, 2007
    Date of Patent: June 29, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Jae Won Han
  • Patent number: 7736939
    Abstract: A method for forming microlenses of different curvatures is described, wherein a substrate having at least a first and a second areas different in height is provided. A transparent photosensitive layer having a planar surface is formed on the substrate and then patterned into at least two islands of different thicknesses respectively over the first area and the second area. The at least two islands are heated and softened to form at least two microlenses of different curvatures respectively over the first area and the second area, wherein the higher an area is, the smaller the curvature of the corresponding microlens is.
    Type: Grant
    Filed: July 7, 2005
    Date of Patent: June 15, 2010
    Assignee: United Microelectronics Corp.
    Inventors: Hsin-Ping Wu, Chia-Huei Lin
  • Publication number: 20100140668
    Abstract: An image sensor includes an imaging area that includes a plurality of pixels, with each pixel including a photosensitive charge storage region formed in a substrate. A passivation implantation region contiguously surrounds the side wall and bottom surfaces of each trench in the one or more trench isolation regions. A portion of each passivation implantation region is laterally adjacent to a respective charge storage region and resides only in an isolation gap disposed between the respective charge storage region and a respective trench isolation region and does not substantially reside under the charge storage region. Each passivation implantation region is formed by implanting one or more dopants at a low energy into the side wall and bottom surfaces of each trench after annealing the image sensor and prior to filling the trenches with an insulating material.
    Type: Application
    Filed: November 11, 2009
    Publication date: June 10, 2010
    Inventor: Eric G. Stevens
  • Patent number: 7727794
    Abstract: A theme is to prevent the generation of noise due to damage in a photodetecting portion in a mounting process in a photodiode array, a method of manufacturing the same, and a radiation detector. In a photodiode array, wherein a plurality of photodiodes (4) are formed in array form on a surface at a side of an n-type silicon substrate (3) onto which light to be detected is made incident and penetrating wirings (8), which pass through from the incidence surface side to the back surface side, are formed for the photodiodes (4), the photodiode array (1) is arranged with a transparent resin film (6), which covers the formed regions of the photodiodes (4) and transmits the light to be detected, provided at the incidence surface side.
    Type: Grant
    Filed: March 10, 2004
    Date of Patent: June 1, 2010
    Assignee: Hamamatsu Photonics K.K.
    Inventor: Katsumi Shibayama
  • Patent number: 7723145
    Abstract: A solid-state imaging device includes a semiconductor substrate including: a plurality of light-receptive portions that are arranged one-dimensionally or two-dimensionally; a vertical transfer portion that transfers signal electric charge read out from the light-receptive portions in a vertical direction; a horizontal transfer portion that transfers the signal electric charge transferred by the vertical transfer portion in a horizontal direction; a barrier region adjacent to the horizontal transfer portion, the barrier region letting only surplus electric charge of the horizontal transfer portion pass therethough; a drain region adjacent to the barrier region, into which the surplus electric charge passing through the barrier region is discharged; and an insulation film adjacent to the drain region. A portion of the drain region is located beneath the insulation film.
    Type: Grant
    Filed: November 20, 2008
    Date of Patent: May 25, 2010
    Assignee: Panasonic Corporation
    Inventor: Toshihiro Kuriyama
  • Patent number: 7709872
    Abstract: Image sensor devices and methods for fabricating the same are provided. An exemplary embodiment of an image sensor device comprises a support substrate. A passivation structure is formed over the support substrate. An interconnect structure is formed over the passivation structure. A first semiconductor layer is formed over the interconnect structure, having a first and second surfaces, wherein the first and second surfaces are opposing surfaces. At least one light-sensing device is formed over/in the first semiconductor layer from a first surface thereof. A color filter layer is formed over the first semiconductor layer from a second surface thereof. At least one micro lens is formed over the color filter layer.
    Type: Grant
    Filed: September 13, 2006
    Date of Patent: May 4, 2010
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Gwo-Yuh Shiau, Ming-Chyi Liu, Yuan-Chih Hsieh, Shih-Chi Fu, Chia-Shiung Tsai
  • Patent number: 7709913
    Abstract: An image sensor package includes a substrate, a sensor chip, a frame, a lens element and at least a pair of guide pins. The sensor chip is mounted on the substrate, and has two opposite sides and a sensing region, which has a sensing region central axis. The frame is mounted on the substrate, and has an aperture and an inner space with the sensor chip disposed therein. The lens element is disposed inside the aperture and has a lens central axis. The guide pins locate oppositely inside the inner space of the frame with an interval between the tips of the guide pins substantially identical to the distance between the opposite sides of the sensor chip, wherein the central line of the interval between the tips of the guide pins defines a positioning line, which substantially coincides with the lens central axis; wherein the tip of each guide pin is aligned with one of the opposite sides of the sensor chip such that the positioning line is substantially coincided with the sensing region central axis.
    Type: Grant
    Filed: February 28, 2008
    Date of Patent: May 4, 2010
    Assignee: Advanced Semiconductor Engineering Inc.
    Inventor: Jian Cheng Chen
  • Patent number: 7704781
    Abstract: The present invention, in the various exemplary embodiments, provides a RGB color filter array. The red, green and blue pixel cells are arranged in a honeycomb pattern. The honeycomb layout provides the space to vary the size of pixel cells of an individual color so that, for example, the photosensor of blue pixels can be made larger than that of the red or green pixels. In another aspect of the invention, depicted in the exemplary embodiments, the honeycomb structure can also be implemented with each pixel rowing having a same color of pixel cells which can simplify can conversion in the readout circuits. In another aspect of the invention, the RGB honeycomb pixel array may be implemented using a shared pixel cell architecture.
    Type: Grant
    Filed: March 5, 2007
    Date of Patent: April 27, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: Jeffrey A. McKee
  • Patent number: 7704775
    Abstract: The invention provides CCD type solid-state imaging apparatus comprises: photoelectric conversion elements; a plurality of first transfer paths extending in a first direction; and second transfer paths extending in a first direction; the first transfer paths and the second transfer paths respectively including a plurality of discretely formed first layer transfer electrode films and second layer transfer electrode films formed between the first layer transfer electrode films and whose ends are laminated on the ends of the adjacent first layer transfer electrode films via insulating films. The thickness of the insulating film between the first layer transfer electrode film and the second layer transfer electrode film constituting the second transfer path shown is smaller than the thickness of the insulating film between the first layer transfer electrode film and the second layer transfer electrode film constituting the first transfer path shown.
    Type: Grant
    Filed: June 19, 2006
    Date of Patent: April 27, 2010
    Assignee: Fujifilm Corporation
    Inventor: Shinji Uya
  • Patent number: 7704826
    Abstract: A method of reading surface levels of a field defined on a substrate using a sensing apparatus having at least one cell array composed of a plurality of cells, in which some of the cells constituting the at least one cell array are selected and designated as available cells. Light is radiated onto a surface of the field. Light reflected to the available cells from the surface is sensed to extract available level signals. The available level signals may be calculated to read the surface level of the field. The surface level of the field are used in a method of controlling the level of an exposure apparatus controlling the substrate mounted on a leveling stage in up, down, right, left, front, back, and rotational directions using the surface level.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: April 27, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Jong-Ho Lim
  • Publication number: 20100097512
    Abstract: A solid-state imaging apparatus includes a plurality of photoelectric conversion units configured to generate signal charge from light received at light-receiving surfaces thereof, the plurality of photoelectric conversion units being provided in the image-sensing area of a substrate; a charge reading unit configured to read signal charge generated by the photoelectric conversion units, a charge readout channel area thereof being provided in the image-sensing area of the substrate; a transfer register unit configured to transfer signal charge read from the plurality of photoelectric conversion units by the charge reading unit, a charge transfer channel area thereof being provided in the image-sensing area of the substrate; and a light-shielding unit that is provided in the image-sensing area of the substrate and that has an opening through which light is transmitted formed in an area corresponding to a light-receiving surface of a respective photoelectric conversion unit.
    Type: Application
    Filed: September 18, 2009
    Publication date: April 22, 2010
    Applicant: Sony Corporation
    Inventors: Shinji Miyazawa, Takeshi Takeda
  • Patent number: 7701026
    Abstract: A backside imaging device includes a bump that is disposed overlapping with a sensor array region or a photodiode in a planar view. By this configuration, the bump becomes a support, and the semiconductor substrate is prevented from being damaged because of a bending applied to the semiconductor substrate.
    Type: Grant
    Filed: March 2, 2007
    Date of Patent: April 20, 2010
    Assignee: NEC Electronics Corporation
    Inventor: Hitoshi Abiko
  • Patent number: 7701030
    Abstract: In a photodiode formed by a region of a first type inside a region of a second type, of a semiconductor substrate, the region of the first type includes a first zone including a dopant of the first type having a first concentration and a first depth. The region of the first type also has a second zone adjacent to the first zone in the dopant of the first type has a second concentration higher than the first concentration and a second depth smaller than the first depth. A method for making such a diode is also disclosed.
    Type: Grant
    Filed: December 24, 2007
    Date of Patent: April 20, 2010
    Assignee: STMicroelectronics SA
    Inventor: Francois Roy
  • Patent number: 7696546
    Abstract: A silicide layer (first silicide layer, second silicide layer) is laminated on top laminate surfaces of gates of a transmission transistor and a reset transistor, respectively. Each of the first silicide layer and the second silicide layer respectively formed on each of the gates extends in a direction along the main surface of the semiconductor substrate among at least a portion of a plurality of image pixels, connecting gates with one another among the respective image pixels. On the other hand, a signal outputter is not in contact with any silicide layers, has the top laminate surface that is covered with an insulating layer, and is connected with other transistors via a metal wiring layer.
    Type: Grant
    Filed: January 17, 2008
    Date of Patent: April 13, 2010
    Assignee: Panasonic Corporation
    Inventors: Tatsuya Hirata, Shouzi Tanaka, Ryohei Miyagawa
  • Patent number: 7687306
    Abstract: A CMOS image sensor and manufacturing method thereof are disclosed. The present CMOS image sensor comprises: a semiconductor substrate including an active region having a photo diode region and a transistor region; a gate on the active region, comprising a gate insulating layer and a gate electrode thereon; a first source/drain diffusion region in the transistor region at one side of the gate electrode, including a first conductivity type dopant; a second photo diode diffusion region in the region at the other side of the gate electrode, the second diffusion region including a first conductivity type dopant; insulating sidewalls on sides of the gate electrode; and a third diffusion region over or in the second diffusion region, extending below one of the insulating sidewalls (e.g., closest to the photo diode region), and including a second conductivity type dopant.
    Type: Grant
    Filed: June 5, 2006
    Date of Patent: March 30, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Gyun Jeon
  • Publication number: 20100055825
    Abstract: A method for manufacturing a semiconductor device that includes a semiconductor substrate, the method comprises: a first irradiation step of irradiating a first irradiated region with a focused ion beam so as to selectively remove a first portion corresponding to the first irradiated region of the wiring pattern, the first irradiated region being positioned on an inner side of a short defect portion of the wiring pattern in a direction along a plane parallel to the principal surface; and a second irradiation step of, after the first irradiation step, irradiating a second irradiated region with a focused ion beam so as to remove a second portion corresponding to the second irradiated region of the wiring pattern, the second irradiated region including a region that is positioned on an outer side of the short defect portion in the direction along the plane parallel to the principal surface.
    Type: Application
    Filed: August 7, 2009
    Publication date: March 4, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Kouhei Hashimoto, Masatsugu Itahashi
  • Patent number: 7670867
    Abstract: The method for manufacturing a CMOS image sensor is employed to prevent bridge phenomenon between adjacent microlenses by employing openings between the microlenses. The method includes the steps of: preparing a semiconductor substrate including isolation regions and photodiodes therein obtained by a predetermined process; forming an interlayer dielectric (ILD), metal interconnections and a passivation layer formed on the semiconductor substrate in sequence; forming a color filter array having a plurality of color filters on the passivation layer; forming an over-coating layer (OCL) on the color filter array by using a positive photoresist or a negative photoresist; forming openings in the OCL by patterning the OCL by using a predetermined mask; and forming dome-typed microlenses on a patterned OCL.
    Type: Grant
    Filed: October 3, 2005
    Date of Patent: March 2, 2010
    Inventors: Chang-Young Jeong, Dae-Ung Shin, Hong-Ik Kim
  • Patent number: 7659186
    Abstract: A method for manufacturing the CMOS image sensor comprising forming an epitaxial layer provided with a plurality of photo diodes on a semiconductor substrate, coating a first photo resist on the epitaxial layer and performing a patterning process on the first photo resist using a predetermined reference value in order to form a first photo resist pattern, coating a second photo resist on the epitaxial layer and first photo resist pattern and performing a patterning process for the second photo resist in order to form the second photo resist pattern on the first photo resist pattern; and forming a well area of a pixel area by performing a dopant implantation process using a mask pattern including the first photo resist pattern and the second photo resist pattern.
    Type: Grant
    Filed: November 30, 2007
    Date of Patent: February 9, 2010
    Assignee: Dongbu Hitek Co., Ltd.
    Inventor: Sun Kyung Bang
  • Patent number: 7659136
    Abstract: It is an object to provide solid-state imaging device, which can easily be manufactured and has a high reliability, and a method of manufacturing the solid-state imaging device. In the present invention, a manufacturing method comprises the steps of forming a plurality of IT-CCDs on a surface of a semiconductor substrate, bonding a translucent member to the surface of the semiconductor substrate in order to have a gap opposite to each light receiving region of the IT-CCD, and isolating a bonded member obtained at the bonding step for each of the IT-CCDs.
    Type: Grant
    Filed: April 17, 2006
    Date of Patent: February 9, 2010
    Assignee: Fujifilm Corporation
    Inventors: Hiroshi Maeda, Kazuhiro Nishida, Yoshihisa Negishi, Shunichi Hosaka
  • Publication number: 20100025799
    Abstract: A wafer for backside illumination type solid imaging device has a plurality of pixels inclusive of a photoelectric conversion device and a charge transfer transistor at its front surface side and a light receiving surface at its back surface side, wherein said wafer is a SOI wafer obtained by forming a given active layer on a support substrate made of C-containing n-type semiconductor material through a chemical oxide film having a thickness of not more than 1 nm.
    Type: Application
    Filed: July 30, 2009
    Publication date: February 4, 2010
    Applicant: SUMCO CORPORATION
    Inventor: Kazunari Kurita
  • Publication number: 20100026869
    Abstract: An image sensor and a method for manufacturing the same are provided. The image sensor comprises a readout circuitry, an interlayer dielectric, an interconnection, and a CuInGaSe2 (CIGS) image sensing device. The readout circuitry is disposed on a first substrate. The interlayer dielectric is disposed over the first substrate. The interconnection is in the interlayer dielectric and electrically connected to the readout circuitry. The CIGS image sensing device is disposed over the interconnection and electrically connected to the readout circuitry through the interconnection.
    Type: Application
    Filed: July 23, 2009
    Publication date: February 4, 2010
    Inventor: Chang Hun Han
  • Patent number: 7655495
    Abstract: A CMOS image sensor array and method of fabrication wherein the sensor includes Copper (Cu) metallization levels allowing for incorporation of a thinner interlevel dielectric stack with improved thickness uniformity to result in a pixel array exhibiting increased light sensitivity. In the sensor array, each Cu metallization level includes a Cu metal wire structure formed at locations between each array pixel and, a barrier material layer is formed on top each Cu metal wire structure that traverses the pixel optical path. By implementing a single mask or self-aligned mask methodology, a single etch is conducted to completely remove the interlevel dielectric and barrier layers that traverse the optical path. The etched opening is then refilled with dielectric material.
    Type: Grant
    Filed: January 17, 2007
    Date of Patent: February 2, 2010
    Assignee: International Business Machiens Corporation
    Inventors: James W. Adkisson, Jeffrey P. Gambino, Mark D. Jaffe, Robert K. Leidy, Anthony K. Stamper
  • Patent number: 7651881
    Abstract: A transfer film, on which an adhesive is applied, is glued to plural spacers formed on a glass substrate. The glass substrate is laid on a working table, and one end of the transfer film is fixed to a winding roller. A peeling guide is set at a position over the transfer film. The winding roller is driven to wind the transfer film while the working table moves horizontally. While winding the transfer film, the angle between the glass substrate and the transfer film is kept constant. After the transfer film is peeled off, the adhesive is uniformly transferred to each of the spacers.
    Type: Grant
    Filed: March 24, 2004
    Date of Patent: January 26, 2010
    Assignee: FUJIFILM Corporation
    Inventors: Kosuke Takasaki, Kazuhiro Nishida, Kiyofumi Yamamoto
  • Publication number: 20100013967
    Abstract: A solid state imaging device includes: a light receiving portion; a transfer gate; a clock wiring group; and a substance. The light receiving portion includes a plurality of light receiving elements formed on a substrate. The charge transfer portion transfers electric charges supplied from the light receiving portion. The transfer gate is provided between the light receiving portion and the charge transfer portion and supplies the electric charges accumulated in the light receiving portion to the charge transfer portion. The clock wiring group includes a plurality of wirings and supplies a plurality of clocks for transferring the electric charges. The substance shields light with a wavelength lower than a predetermined wavelength. The plurality of wirings is arranged away from one another with a gap corresponding to the predetermined wavelength. The substance is arranged to cover the gap and shields light with a wavelength possibly passing through the gap.
    Type: Application
    Filed: July 1, 2009
    Publication date: January 21, 2010
    Applicant: NEC Electronics Corporation
    Inventor: Makoto Tanaka
  • Patent number: 7645646
    Abstract: In the manufacture of an electronic device such as an active matrix display, a vertical amorphous PIN photodiode or similar thin-film diode (D) is advantageously integrated with a polysilicon TFT (TFT1, TFT2) in a manner that permits a good degree of optimization of the respective TFT and diode properties while being compatible with the complex pixel context of the display. High temperature processes for making the active semiconductor film (10) of the TFT more crystalline than an active semiconductor film (40) of the diode and for forming the source and drain doped regions (s1,s2, d1,d2) of the TFT are carried out before depositing the active semiconductor film (40) of the diode. Thereafter, the lateral extent of the diode is defined by etching while protecting with an etch-stop film (30) an interconnection film (20) that can provide a doped bottom electrode region (41) of the diode as well as one of the doped regions (s2, g1) of the TFT.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: January 12, 2010
    Assignee: Koninklijke Philips Electronics N.V.
    Inventor: Nigel D. Young
  • Patent number: 7642107
    Abstract: A pixel with a photosensor and a transfer transistor having a split transfer gate. A first section of the transfer gate is connectable to a first voltage source while a second section of the transfer gate is connectable to a second voltage source. Thus, during a charge integration period of a photosensor, the two sections of the transfer gate may be oppositely biased to decrease dark current while controlling blooming of electrons within and out of the pixel cell. During charge transfer the two gate sections may be commonly connected to a positive voltage sufficient to transfer charge from the photosensor to a floating diffusion region.
    Type: Grant
    Filed: December 21, 2006
    Date of Patent: January 5, 2010
    Assignee: Aptina Imaging Corporation
    Inventor: John Ladd
  • Publication number: 20090322923
    Abstract: A photoelectric apparatus includes a substrate and an array of a plurality of pixels each having at least one photoelectric device including a lower electrode over the substrate, a photoelectric layer over the lower electrode, and an upper electrode over the photoelectric layer, the photoelectric apparatus further includes an electrically conductive partition between adjacent two of the pixels, the conductive partition being electrically connected with the upper electrode and a transparent insulating layer on the upper electrode, and the pixels is individually sealed in by the partition and the transparent insulating layer.
    Type: Application
    Filed: June 24, 2009
    Publication date: December 31, 2009
    Applicant: FUJIFILM CORPORATION
    Inventor: Yoshiki Maehara
  • Patent number: 7638354
    Abstract: An image sensor can include a gate insulation layer, a gate electrode, a photodiode, and a floating diffusion region. The gate insulation layer can be formed on and/or over a semiconductor substrate for a transfer transistor. The gate insulation layer includes a first gate insulation layer having a central opening and a second gate insulation layer formed on and/or over an uppermost surface of the first gate insulation layer including the opening. The gate electrode can be formed on and/or over the gate insulation layer. The photodiode can be formed in the semiconductor substrate at one side of the gate electrode so as to generate an optical charge. The floating diffusion region can be formed in the semiconductor at the other side of the gate electrode opposite to the photodiode. The floating diffusion region can be electrically connected to the photodiode through a channel so as to store the optical charge generated from the photodiode.
    Type: Grant
    Filed: December 14, 2007
    Date of Patent: December 29, 2009
    Assignee: Dongbu HiTek Co., Ltd.
    Inventor: Ji-Hoon Hong