Abstract: A method of manufacturing a liquid crystal display device which includes pixel electrodes and common electrodes which are alternatively arranged in each pixel defined on a substrate, including the steps of: forming a conductive film on the substrate; forming a mask layer, of which etching selection ratio is different from the conductive layer, on the conductive layer; forming a photo-resist pattern of a fixed pattern on the mask layer; forming a mask pattern, which has an undercut shape to the photo-resist pattern, by etching the mask layer by use of the photo-resist pattern as an etching mask; removing the photo-resist pattern; and etching the conductive film by use of the mask pattern as an etching mask, to provide at least any one of the common electrode and the pixel electrode.

Abstract: Single source precursors are subjected to carbon dioxide to form particles of material. The carbon dioxide may be in a supercritical state. Single source precursors also may be subjected to supercritical fluids other than supercritical carbon dioxide to form particles of material. The methods may be used to form nanoparticles. In some embodiments, the methods are used to form chalcopyrite materials. Devices such as, for example, semiconductor devices may be fabricated that include such particles. Methods of forming semiconductor devices include subjecting single source precursors to carbon dioxide to form particles of semiconductor material, and establishing electrical contact between the particles and an electrode.

Abstract: To provide a reliable, efficient method for reducing oxidized metals used upon manufacturing of the multilayer interconnection structure, semiconductor device, etc. With this method vapor containing at least a carboxylic acid ester is hydrolyzed by water vapor to reduce oxidized metal. The multilayer interconnection manufacturing method of the present invention includes at least film formation step, interconnection formation step, and reduction step using the metal reduction method of the present invention. The multilayer interconnection structure of the present invention is manufactured by the multilayer interconnection structure manufacturing method of the present invention. The semiconductor device manufacturing method of the present invention includes at least film formation step, patterning step, interconnection formation step, and reduction step using the metal reduction method.

Abstract: The method of manufacturing a semiconductor device comprises forming a metal film over silicon regions and insulating films; performing a first heat treatment under an oxygen atmosphere containing oxygen as a main ingredient, to form a first silicide film in the silicon region by reacting the metal film and the silicon region, and to simultaneously form a metal oxide by oxidizing the entire surface of the metal film from the surface side thereof; and selectively removing the metal oxide and the unreacted metal film using a chemical.

Abstract: In one embodiment, a method for treating a surface of a semiconductor substrate is disclosed. The semiconductor substrate has a first pattern covered by a resist and a second pattern not covered by the resist. The method includes supplying a resist-insoluble first chemical solution onto a semiconductor substrate to subject the second pattern to a chemical solution process. The method includes supplying a mixed liquid of a water repellency agent and a resist-soluble second chemical solution onto the semiconductor substrate after the supply of the first chemical solution, to form a water-repellent protective film on a surface of at least the second pattern and to release the resist. In addition, the method can rinse the semiconductor substrate using water after the formation of the water-repellent protective film, and dry the rinsed semiconductor substrate.

Abstract: A capacitive electromechanical transducer includes a substrate, a cavity formed by a vibrating membrane held above the substrate with a certain distance between the vibrating membrane and the substrate by supporting portions arranged on the substrate, a first electrode whose surface is exposed to the cavity, and a second electrode whose surface facing the cavity is covered with an insulating film, wherein the first electrode is provided on a surface of the substrate or a lower surface of the vibrating membrane and the second electrode is provided on a surface of the vibrating membrane or a surface of the substrate so as to face the first electrode. In this transducer, fine particles composed of an oxide film of a substance constituting the first electrode are arranged on the surface of the first electrode, and the diameter of the fine particles is 2 to 200 nm.

Abstract: An etching solution for a metal hard mask. The etching solution comprises a mixture of a dilute HF (hydrofluoric acid) and a silicon containing precursor. The etching solution also comprises a surfactant agent, a carboxylic acid, and a copper corrosion inhibitor. The etching solution is selectively toward etching the metal hard mask material (e.g., Titanium) while suppressing Tungsten, Copper, oxide dielectric material, and carbon doped oxide.

Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems provide the thin layer of pre-rinsing liquid before applying etchant at the edge bevel region of the wafer. The etchant is less diluted and diffuses faster through a thinned layer of rinsing liquid. An edge bevel removal embodiment involving that is particularly effective at reducing process time, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Abstract: A solar cell manufacturing method according to the present invention is a solar cell manufacturing method that forms a transparent conductive film of ZnO as an electric power extracting electrode on a light incident side, the method comprises at least in a following order: a process A forming the transparent conductive film on a substrate by applying a sputtering voltage to sputter a target made of a film formation material for the transparent conductive film; a process B forming a texture on a surface of the transparent conductive film; a process C cleaning the surface of the transparent conductive film on which the texture has been formed using an UV/ozone; and a process D forming an electric power generation layer on the transparent conductive film.

Abstract: The various embodiments described in the specification provide improved mechanisms of removal of unwanted deposits on the bevel edge to improve process yield. The embodiments provide apparatus and methods of treating the bevel edge of a copper plated substrate to convert the copper at the bevel edge to a copper compound that can be wet etched with a fluid at a high etch selectivity in comparison to copper. In one embodiment, the wet etch of the copper compound at high selectivity to copper allows the removal of the non-volatile copper at substrate bevel edge in a wet etch processing chamber. The plasma treatment at bevel edge allows the copper at bevel edge to be removed at precise spatial control to about 2 mm or below, such as about 1 mm, about 0.5 mm or about 0.25 mm, to the very edge of substrate.

Abstract: A method of producing a transistor includes providing a substrate including in order a first electrically conductive material layer, a second electrically conductive material layer, and a third electrically conductive material layer. A resist material layer is deposited over the third electrically conductive material layer. The resist material layer is patterned to expose a portion of the third electrically conductive material layer. Some of the third electrically conductive material layer is removed to expose a portion of the second electrically conductive material layer. The third electrically conductive material layer is caused to overhang the second electrically conductive material layer by removing some of the second electrically conductive material layer. Some of the first electrically conductive material layer is removed.

Abstract: An etchant composition for etching a transparent electrode is provided, the etchant composition includes an inorganic acid, an ammonium (NH4+)-containing compound, a cyclic amine compound, and the remaining amount of water.

Abstract: The present disclosure relates to a solution for selectively removing metal, such as Ta or TaN, from a substrate, such as an aluminum containing substrate. The solution comprises an acid, such as HF or buffered HF, an ingredient comprising a fluorine ion, such as ammonium fluoride (NH4F), ethylene glycol, and water. A method of selectively removing metal from a substrate using this solution is also disclosed.

Abstract: A semiconductor device of the present invention has a first interconnect layer formed over the semiconductor substrate, and a semiconductor element; the first interconnect layer has an insulating layer, and a first interconnect filled in a surficial portion of the insulating layer; the semiconductor element has a semiconductor layer, a gate insulating film, and a gate electrode; the semiconductor layer is positioned over the first interconnect layer; the gate insulating film is positioned over or below semiconductor layer; and the gate electrode is positioned on the opposite side of the semiconductor layer while placing the gate insulating film in between.

Abstract: An electrically conductive first chemical solution is supplied to the back surface of a semiconductor substrate, on the front surface of which elements are formed. After starting supplying the first chemical solution, wet processing is performed by supplying an electrically conductive second chemical solution to the front surface of the semiconductor substrate.

Abstract: A method for manufacturing printed circuit board includes steps below. A first electrically conductive layer including a first surface and a second surface at an opposite side thereof to the first surface is provided. A number of first traces directly formed on the second surface. A first insulating layer is formed on the second surface of the first electrically conductive layer and the surface of the first traces. The electrically conductive layer is etched to form a number of second traces, the second traces superpose the first traces, the first traces and the second traces constitute a circuit pattern.

Abstract: Exposed copper regions on a semiconductor substrate can be etched by a wet etching solution comprising (i) one or more complexing agents selected from the group consisting of bidentate, tridentate, and quadridentate complexing agents; and (ii) an oxidizer, at a pH of between about 5 and 12. In many embodiments, the etching is substantially isotropic and occurs without visible formation of insoluble species on the surface of copper. The etching is useful in a number of processes in semiconductor fabrication, including for partial or complete removal of copper overburden, for planarization of copper surfaces, and for forming recesses in copper-filled damascene features. Examples of suitable etching solutions include solutions comprising a diamine (e.g., ethylenediamine) and/or a triamine (e.g., diethylenetriamine) as bidentate and tridentate complexing agents respectively and hydrogen peroxide as an oxidizer.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: A method of removing non-noble metal oxides from material (e.g., semiconductor material) used to make a microelectronic device includes providing the material comprising traces of the conducting non-noble metal oxides; applying a chemical mixture (or chemical solution) to the material; removing the traces of the non-noble metal oxides from the material; and removing the chemical mixture from the material. The non-noble metal oxides comprise MoOx, wherein x is a positive number between 0 and 3. The chemical solution comprises any one of HNO3-based chemicals, H2SO4-based chemicals, HCl-based chemicals, or NH4OH-based chemicals.

Abstract: A method for the production of a structured metal layer (7) made from an alloy composed of titanium and nickel includes the following process steps: a sacrificial layer composite (3) is provided, which comprises a second sacrificial layer (2) applied onto a first sacrificial layer (1), the first sacrificial layer (1) is subjected for the purpose of structuring to a wet-chemical etching process in such a manner that undercutting of the sacrificial layer (1) occurs, a metal layer (7) of the alloy is applied indirectly or directly to the structured sacrificial layer composite (3). The first sacrificial layer (1) is at a greater distance from the metal layer (7). The second sacrificial layer (2) facing the metal layer (7) to be deposited is subjected to a dry etching process prior to wet-chemical etching of the first sacrificial layer (1) so that the second sacrificial layer (2) is provided with a structure that corresponds to the desired structure of the metal layer (7).

Abstract: A manufacturing method for manufacturing a light-sensing structure is provided. The manufacturing method includes the steps as follows. (a) A circuit layer is formed on an upper surface of a first substrate, wherein the first substrate includes at least one light-sensing device and the circuit layer includes at least one device structure and at least one release feature that is made of metal and is formed on part of the light-sensing device and the device structure. (b) A first light-filtering layer is formed on part of the circuit layer. (c) The release feature is removed by a wet-etching process.

Abstract: The present invention discloses an etchant for etching at least two different metal layers, the etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—). The present invention also discloses a method of fabricating a metal wiring on a substrate, the method comprising forming a first metal layer on a substrate, forming a second metal layer on the first metal layer, and simultaneously etching the first metal layer and the second metal layer with an etchant comprising hydrogen peroxide (H2O2) and one of carboxylic acid, carboxylate salt, and acetyl group (CH3CO—).

Abstract: Disclosed are an etchant which is used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode and which is capable of selectively etching copper without etching nickel, and a method for manufacturing a semiconductor device using the same. Specifically disclosed are an etchant to be used for the manufacture of a semiconductor device using a semiconductor substrate having an electrode, including hydrogen peroxide, an organic acid, and an organic phosphonic acid, wherein the organic acid is at least one member selected from citric acid and malic acid; a content of hydrogen peroxide is from 0.75 to 12% by mass; a content of the organic acid is from 0.75 to 25% by mass; and a content of the organic phosphonic acid is from 0.0005 to 1% by mass, and a method for manufacturing a semiconductor device using the etchant.

Abstract: A method for forming a thin-film transistor (TFT) includes providing a substrate, forming a first patterned conducting layer on the substrate, forming an organic dielectric layer on the first patterned conducting layer and the substrate, forming a seeding layer on the organic dielectric layer, using the seeding layer as a crystal growing base to form an inorganic semiconductor layer on the seeding layer, and forming a second patterned conducting layer on the inorganic semiconductor layer.

Abstract: A method of removing a metal nitride material is disclosed. The method comprises forming a semiconductor device structure comprising an exposed metal material and an exposed metal nitride material. The semiconductor device structure is subjected to a solution comprising water, ozone, and at least one additive to remove the exposed metal nitride material at a substantially greater rate than the exposed metal material.

Abstract: Methods and etchant compositions for wet etching to selectively remove a hafnium aluminum oxide (HfAlOx) material relative to silicon oxide (SiOx) are provided.

Abstract: A memory, comprising a metal portion, a first metal layer and second metal oxide layer is provided. The first metal oxide layer is on the metal portion, and the first metal oxide layer includes N resistance levels. The second metal oxide layer is on the first metal oxide layer, and the second metal oxide layer includes M resistance levels. The memory has X resistance levels and X is less than the summation of M and N, for minimizing a programming disturbance.

Abstract: This disclosure relates to an etching composition containing at least one sulfonic acid, at least one compound containing a halide anion, the halide being chloride or bromide, at least one compound containing a nitrate or nitrosyl ion, and water. The at least one sulfonic acid can be from about 25% by weight to about 95% by weight of the composition. The halide anion can be chloride or bromide, and can be from about 0.01% by weight to about 0.5% by weight of the composition. The nitrate or nitrosyl ion can be from about 0.1% by weight to about 20% by weight of the composition. The water can be at least about 3% by weight of the composition.

Abstract: An etchant includes about 0.1 percent by weight to about 30 percent by weight of ammonium persulfate (NH4)2S2O8, about 0.1 percent by weight to about 10 percent by weight of an inorganic acid, about 0.1 percent by weight to about 10 percent by weight of an acetate salt, about 0.01 percent by weight to about 5 percent by weight of a fluorine-containing compound, about 0.01 percent by weight to about 5 percent by weight of a sulfonic acid compound, about 0.01 percent by weight to about 2 percent by weight of an azole compound, and a remainder of water. Accordingly, the etchant may have high stability to maintain etching ability. Thus, manufacturing margins may be improved so that manufacturing costs may be reduced.

Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.

Abstract: An etchant includes hydrogen peroxide (H2O2), and a mixed solution including at least one of an organic acid, an inorganic acid, and a neutral salt.

Abstract: Methods of fabricating components for microelectronic devices, microelectronic devices including memory cells or other components, and computers including memory devices include forming memory cells. For example, one embodiment is directed toward a method of fabricating a memory cell on a workpiece having a substrate, a plurality of active areas in the substrate, and a dielectric layer over the active areas. One embodiment of the method includes constructing bit line contact openings in the dielectric layer over first portions of the active areas and cell plug openings over second portions of the active areas. The method also includes depositing a first conductive material into the bit line contact openings to form bit line contacts and into the cell plug openings to form cell plugs. A conductive line is formed in a trench in the substrate.

Abstract: The present invention relates to a method for forming electrode patterns of a ceramic substrate including the steps of: forming a plurality of conductive adhesion patterns on the ceramic substrate to be separated apart from one another; forming a plating seed layer, covering the conductive adhesion patterns, on the ceramic substrate; forming photoresist patterns, exposing parts corresponding to the conductive adhesion patterns, on the plating seed layer; forming a plating layer on the plating seed layer exposed by the photoresist patterns; removing the photoresist patterns; and etching parts of the plating seed layer exposed by removal of the photoresist patterns.

Abstract: A method of making a monolithic photovoltaic module having a flexible substrate is described. The method includes the following steps. First, a flexible substrate is provided, and a first adhesive layer, a metal layer, and a second adhesive layer are formed thereon. The second adhesive layer, the metal layer and the first adhesive layer are etched with at least one etching paste. In addition, a patterned semiconductor body layer patterned by an etching paste or a laser scribing is formed thereon. Furthermore, transparent top electrodes patterned by an etching paste or a cold laser scribing are formed on the patterned semiconductor body layer.

Abstract: The present invention relates to a method for treating copper or copper alloy surfaces for tight bonding to polymeric substrates, for example solder masks found in multilayer printed circuit boards. The substrate generally is a semiconductor-device, a lead frame or a printed circuit board.

Abstract: The present disclosure provides a method for making a semiconductor device. The method includes forming a material layer on a substrate; forming a sacrificial layer on the material layer, where the material layer and sacrificial layer each as a thickness less than 100 angstrom; forming a patterned photoresist layer on the sacrificial layer; applying a first wet etching process to etch the sacrificial layer to form a patterned sacrificial layer using the patterned photoresist layer as a mask; applying a second wet etching process to etch the first material layer; and applying a third wet etching process to remove the patterned sacrificial layer.

Abstract: There is provided an etching method of an amorphous oxide layer containing In and at least one of Ga and Zn, which includes etching the amorphous oxide layer using an etchant containing any one of acetic acid, citric acid, hydrochloric acid, and perchloric acid.

Abstract: A piezoelectric tactile sensor comprises a piezoelectric membrane with a top surface, a transducer of elastic column with a bottom end surface to overlay over the top surface of the piezoelectric membrane and plural microelectrodes being sandwiched between the top surface of the piezoelectric membrane and the bottom end surface of the transducer in spread manner. When the transducer is subjected to an external stress, the piezoelectric membrane will generate uneven stress distribution to initiate dispersed microelectrodes output a corresponding induced voltage signal for being analyzed to figure out the direction and magnitude of the external stress.

Abstract: Plating accelerator is applied selectively to a substantially-unfilled wide (e.g., low-aspect-ratio feature cavity. Then, plating of metal is conducted to fill the wide feature cavity and to form an embossed structure in which the height of a wide-feature metal protrusion over the metal-filled wide-feature cavity is higher than the height of metal over field regions. Most of the overburden metal is removed using non-contact techniques, such as chemical wet etching. Metal above the wide feature cavity protects the metal-filled wide-feature interconnect against dishing, and improved planarization techniques avoid erosion of the metal interconnect and dielectric insulating layer. In some embodiments, plating of metal onto a substrate is conducted to fill narrow (e.g., high-aspect-ratio feature cavities) in the dielectric layer before selective application of plating accelerator and filling of the wide feature cavity.

Abstract: Methods for preventing feature collapse subsequent to etching a layer encasing the features include adding a non-aqueous liquid to a microelectronic topography having remnants of an aqueous liquid arranged upon its surface and subsequently exposing the topography to a pressurized chamber including a fluid at or greater than its saturated vapor pressure or critical pressure. The methods include flushing from the pressurized chamber liquid arranged upon the topography and, thereafter, venting the chamber in a manner sufficient to prevent liquid formation therein. The topography features may be submerged in a liquid while pressurizing the chamber. A process chamber used to prevent feature collapse includes a substrate holder for supporting a microelectronic topography, a vessel configured to contain the substrate holder, and a sealable region surrounding the substrate holder and the vessel. The chamber is configured to sequester wet chemistry supplied to the vessel from metallic surfaces of the sealable region.

Abstract: A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask.

Abstract: One or more embodiments relate to a method for making a semiconductor structure, comprising: providing a workpiece; forming a barrier layer over the workpiece; forming a separation layer over the barrier layer; forming a conductive layer over the separation layer; and wet etching the conductive layer.

Abstract: Methods are disclosed for monitoring the amount of metal contamination imparted during wafer processing operations such as polishing and cleaning. The methods include subjecting a silicon-on-insulator structure to the semiconductor process, precipitating metal contamination in the structure and delineating the metal contaminants.

Abstract: Disclosed herein is a solder self-assembly structure, an IC chip including a solder self-assembly structure, and a method of making the same. The structure includes a release layer disposed on a portion of an upper surface of the substrate, laterally spaced from a via in the substrate. A barrier layer metallization (BLM) is disposed in a first part over a portion of the substrate including a via, and in a second part over the release layer, leaving a surface of the substrate exposed between the first portion and the second portion of the BLM. A solder structure is disposed over the first and second portions of the BLM and the exposed surface of the substrate disposed there between. When the solder structure is reflowed and annealed, surface tension in the solder causes self-assembly of a three-dimensional, compliant solder structure.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer.

Abstract: A lead frame includes a base material having a front surface for mounting of a semiconductor chip and a back surface for connection with an external board, and an Ni layer having a thick section and thin section. The thick section is formed on the back surface of the base material, whereas the thin section is formed on all or a part of the front surface of the base material. It is preferable that the thick section has a thickness ranging from 2.5 to 5 ?m, and the thin section is 0.5-2 ?m thinner than the thick section. The lead frame can be manufactured with improved productivity by forming an Ni layer on both front and back surfaces of the base material, and then etching only the Ni layer formed on the front surface of the base material.

Abstract: Processes for selectively patterning a magnetic film structure generally include selectively etching an exposed portion of a freelayer disposed on a tunnel barrier layer by a wet process, which includes exposing the freelayer to an etchant solution comprising at least one acid and an organophosphorus acid inhibitor or salt thereof, stopping on the tunnel barrier layer.

Abstract: The present invention provides etchant solutions including deionized water and an organic acid having a carboxyl radical and a hydroxyl radical. Methods of forming magnetic memory devices are also disclosed.

Abstract: An etching process is employed to selectively pattern an exposed magnetic layer of a magnetic thin film structure. The etching process generally includes selectively patterning a magnetic film structure comprises providing a magnetic structure comprising at least one bottom magnetic layer, at least one top magnetic layer, wherein the at least one bottom magnetic layer is separated from the at least one top magnetic layer by a tunnel barrier layer; and selectively etching the top magnetic layer with an etching solution comprising at least one weakly absorbing acid, a surfactant inhibitor soluble in the at least one weakly absorbing acid, and at least one cation additive, wherein etching of the tunnel barrier layer is substantially prevented. In some embodiments, etching solution comprises at least one perfluoroalkane sulfonic acid, an alkylsulfonate salt soluble in the at least one perfluoroalkane sulfonic acid, and at least one cation additive.

Abstract: A method of forming a fine pattern begins with providing a c-plane hexagonal semiconductor crystal. A mask having a predetermined pattern is formed on the semiconductor crystal. The semiconductor crystal is dry-etched by using the mask to form a first fine pattern on the semiconductor crystal. The semiconductor crystal including the first fine pattern is wet-etched to expand the first fine pattern in a horizontal direction to form a second fine pattern. The second fine pattern obtained in the wet-etching the semiconductor crystal has a bottom surface and a sidewall that have unique crystal planes, respectively. The present fine-pattern forming process can be advantageously applied to a semiconductor light emitting device, particularly, to a phonic crystal structure required to have fine patterns or a structure using a surface plasmon resonance principle.