Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/754)
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Patent number: 7368397Abstract: Disclosed is a method for monitoring an edge bead removal process for a copper metal interconnection. The method includes the steps of (a) forming a copper metal layer on a semiconductor wafer, (b) performing the edge bead removal (EBR) process of removing the copper metal layer formed in an edge area of the semiconductor wafer, and (c) determining whether copper residues exist by measuring a reflection coefficient Rc of the copper metal layer formed in a center area of the semiconductor wafer and a reflection coefficient (Rb) in the edge area of the semiconductor wafer which is subject to the edge bead removal (EBR) process.Type: GrantFiled: December 27, 2006Date of Patent: May 6, 2008Assignee: Dongbu Electronics Co., Ltd.Inventor: Ji Ho Hong
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Patent number: 7364666Abstract: Disclosed is a method for making flexible circuits in which portions of a tie layer are removed by etching the underlying polymer. Also disclosed are flexible circuits made by this method.Type: GrantFiled: December 6, 2005Date of Patent: April 29, 2008Assignee: 3M Innovative Properties CompanyInventors: Sridhar V. Dasaratha, James S. McHattie, James R. Shirck, Hideo Yamazaki, Yuji Hiroshige, Makoto Sekiguchi
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Patent number: 7357878Abstract: Provided are an etchant, a method for fabricating a wire using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant includes a material having the formula 1, ammonium acetic acid, and the remainder of deionized water, wherein the formula 1 is expressed by: M(OH)XLY??(1) where M indicates Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X indicates 2 or 3, L indicates H2O, NH3, CN, COR, or NH2R, Y indicates 0, 1, 2, or 3, and R indicates an alkyl group.Type: GrantFiled: February 9, 2006Date of Patent: April 15, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-sick Park, Shi-yul Kim, Jong-hyun Choung, Won-suk Shin
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Patent number: 7358195Abstract: In etching a metal line formed as a dual layer of aluminum alloy and molybdenum, the metal line consisting of the dual layer of aluminum alloy and molybdenum is etched through one-time wet etching by applying the etchant including HNO3, HClO4, a Ferric compound (Fe3+), and a Flouro compound (F?), the process can be reduced and a metal line having a good profile can be formed.Type: GrantFiled: September 28, 2004Date of Patent: April 15, 2008Assignee: LG.Philips LCD Co., Ltd.Inventors: Soon-Ho Choi, Hyuk-Cheol Son, Kum-Chul Oh, Seung-Hwan Chon, Young-Chul Park
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Patent number: 7341958Abstract: The formation of devices in semiconductor material. In one embodiment, a method of forming a semiconductor device is provided. The method comprises forming at least one hard mask overlaying at least one layer of resistive material. Forming at least one opening to a working surface of a silicon substrate of the semiconductor device. Cleaning the semiconductor device with a diluted HF/HCL process. After cleaning with the diluted HF/HCL process, forming a silicide contact junction in the at least one of the opening to the working surface of the silicon substrate and then forming interconnect metal layers.Type: GrantFiled: April 8, 2005Date of Patent: March 11, 2008Assignee: Intersil Americas Inc.Inventors: John T. Gasner, John Stanton, Dustin A. Woodbury, James D. Beasom
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Patent number: 7342637Abstract: A method for manufacturing the LCD device includes forming a thin film transistor array having gate and data lines crossing to each other, defining pixel regions on a substrate, and thin film transistors arranged at crossings of the gate and data lines; forming a passivation layer over the entire surface of the substrate; forming a contact hole in the passivation layer exposing drain electrodes of each thin film transistor; forming an amorphous indium tin oxide film on the passivation layer; selectively crystallizing portions of the amorphous indium tin oxide film within the pixel regions by selectively irradiating light onto the amorphous indium tin oxide thin film; and forming a pixel electrode by selectively removing uncrystallized portions of the amorphous indium tin oxide thin film.Type: GrantFiled: March 28, 2003Date of Patent: March 11, 2008Assignee: LG.Philips LCD Co., Ltd.Inventor: Cheol Se Kim
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Publication number: 20080045035Abstract: A metal etching solution may include nitric acid, hydrochloric acid, organic acid and water. A semiconductor product fabricating method may include forming a seed layer on a substrate with a metal pad, forming a sacrificial layer that may have an opening exposing the seed layer on the substrate with the seed layer, forming a gold bump that may fill the opening of the sacrificial layer by performing gold electroplating, removing the sacrificial layer, and etching the seed layer exposed by the gold bump, using an etching solution that may include nitric acid, hydrochloric acid, organic acid and water.Type: ApplicationFiled: April 13, 2007Publication date: February 21, 2008Inventors: Ji-Sung Lee, Dong-Min Kang, Young Nam Kim, Young-Sam Lim, Yun-Deok Kang
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Publication number: 20080038924Abstract: A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one embodiment, the wet etchant is utilized to pattern a metal layer in a semiconductor structure. In another embodiment, a highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is used to pattern a metal gate electrode in a replacement gate processing scheme.Type: ApplicationFiled: August 8, 2006Publication date: February 14, 2008Inventors: Willy Rachmady, Jack T. Kavalieros, Mark Y. Liu, Mark L. Doczy
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Patent number: 7326650Abstract: In an etching method for achieving a dual damascene structure by using at least one layer of a low-k film and at least one layer of a hard mask, a dummy film, which is ultimately not left in the dual damascene structure, is formed in at least one layer over the hard mask in order to prevent shoulder sag. By adopting this method, a dual damascene structure in which the extent of the shoulder sag at the hard mask is minimized can be achieved through etching.Type: GrantFiled: October 1, 2001Date of Patent: February 5, 2008Assignee: Tokyo Electron LimitedInventors: Yoshihide Kihara, Shin Okamoto, Koichiro Inazawa, Tomoki Suemasa
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Patent number: 7320942Abstract: A method for removal of metallic residue from a substrate after a plasma etch process in a semiconductor substrate processing system by cleaning the substrate in a hydrogen fluoride solution.Type: GrantFiled: November 1, 2002Date of Patent: January 22, 2008Assignee: Applied Materials, Inc.Inventors: Xiaoyi Chen, Chentsau Ying, Padmapani C. Nallan, Ajay Kumar, Ralph C. Kerns, Ying Rui, Chun Yan, Guowen Ding, Wai-Fan Yau
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Patent number: 7314834Abstract: A semiconductor device fabrication method applies a diazo novolac photoresist to a semiconductor wafer, followed by light exposure of its entire surface to form an underlying resist layer; forms a surface resist layer thereover; performs patterned-light exposure and heat treatment to the photoresist film consisting of the two resist layers formed; and exposes its entire surface to light, followed by development to process the photoresist film into a resist pattern, where the surface resist layer is in an inverse tapered shape, while the underlying resist layer is in an undercut shape relative to the surface resist layer.Type: GrantFiled: June 16, 2005Date of Patent: January 1, 2008Assignee: Hitachi Cable, Ltd.Inventor: Genta Koizumi
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Patent number: 7309658Abstract: Systems and methods for molecular self-assembly are provided. The molecular self-assembly receives a substrate that includes one or more regions of dielectric material. A molecularly self-assembled layer is formed on an exposed surface of the dielectric material. The molecularly self-assembled layer includes material(s) having a molecular characteristic and/or a molecular type that includes one or more of a molecular characteristic and/or a molecular type of a head group of molecules of the material, a molecular characteristic and/or a molecular type of a terminal group of molecules of the material, and a molecular characteristic and/or a molecular type of a linking group of molecules of the material. The molecular characteristic(s) and molecular type(s) are selected according to at least one pre-specified property of the molecularly self-assembled layer.Type: GrantFiled: November 22, 2005Date of Patent: December 18, 2007Assignee: Intermolecular, Inc.Inventors: David E. Lazovsky, Tony P. Chiang, Majid Keshavarz
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Patent number: 7279425Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: October 17, 2006Date of Patent: October 9, 2007Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 7276455Abstract: This invention methods of etching an aluminum oxide comprising substrate, and methods of forming capacitors. In one implementation, a method of etching an aluminum oxide comprising substrate includes flowing water and ozone to aluminum oxide on the substrate, with at least one of the water and the ozone being at a temperature of at least 65° C. at the aluminum oxide effective to etch aluminum oxide from the substrate. In one implementation, aspects of the method are utilized in forming a capacitor.Type: GrantFiled: June 27, 2006Date of Patent: October 2, 2007Assignee: Micron Technology, Inc.Inventor: Kevin R. Shea
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Publication number: 20070218695Abstract: A method of forming a metal pattern comprising forming a metal film having a lower layer made of a metal and an upper layer made of a metal different from the metal of the lower layer, forming a resist film having a predetermined pattern on the upper layer, and patterning the metal film by etching the metal film using the resist film as a mask. Here, patterning the metal film comprises etching the upper layer, immersing the resist film and the upper layer in a pretreatment liquid containing a nonionic surfactant after the first etching process, and etching the lower layer after the immersing process.Type: ApplicationFiled: March 15, 2007Publication date: September 20, 2007Applicant: SEIKO EPSON CORPORATIONInventors: Shinya Momose, Kazushige Hakeda
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Patent number: 7270762Abstract: The polishing composition of this invention is useful for chemical-mechanical polishing of substrates containing noble metals such as platinum and comprises up to about 50% by weight of a adjuvant wherein said adjuvant is s elected from a group consisting of a metal-anion compound, a metal-cation compound or mixtures thereof; abrasive particles at about 0.5% to about 55% by weight of the polishing composition; and water-soluble organic additives up to about 10% by weight of the polishing composition. The abrasive particles are selected from the group consisting of alumina, ceria, silica, diamond, germania, zirconia, silicon carbide, boron nitride, boron carbide or mixtures thereof. The organic additives generally improve dispersion of the abrasive particles and also enhance metal removal rates and selectivity for metal removal by stabilizing the pH of the polishing composition and suppressing the dielectric removal rate.Type: GrantFiled: March 20, 2003Date of Patent: September 18, 2007Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.Inventors: Hongyu Wang, Terence M. Thomas, Qianqiu Ye, Heinz F. Reinhardt, Vikas Sachan
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Patent number: 7265040Abstract: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode technologies that have been spotlighted because of the capability to improve device operation characteristics.Type: GrantFiled: December 5, 2003Date of Patent: September 4, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Sang-Yong Kim, Kun-Tack Lee
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Patent number: 7256138Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF (preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.Type: GrantFiled: June 29, 2004Date of Patent: August 14, 2007Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Yongjun Jeff Hu
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Patent number: 7253119Abstract: A plurality of semiconductor nanoparticles having an elementally passivated surface are provided. These nanoparticles are capable of being suspended in water without substantial agglomeration and substantial precipitation on container surfaces for at least 30 days. The method of making the semiconductor nanoparticles includes reacting at least a first reactant and a second reactant in a solution to form the semiconductor nanoparticles in the solution. A first reactant provides a passivating element which binds to dangling bonds on a surface of the nanoparticles to passivate the surface of the nanoparticles. The nanoparticle size can be tuned by etching the nanoparticles located in the solution to a desired size.Type: GrantFiled: May 9, 2005Date of Patent: August 7, 2007Assignee: Rensselaer Polytechnic InstituteInventor: Partha Dutta
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Patent number: 7235494Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.Type: GrantFiled: January 27, 2005Date of Patent: June 26, 2007Assignee: Micron Technology, Inc.Inventor: Michael T. Andreas
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Patent number: 7202165Abstract: In the case that a stacked layer, in which another metal layer is stacked on an Al layer or Al alloy layer having a low resistance, is used as a wiring material, an etchant is provided which can etch to a substantially equal etching rate by executing only one etching on the each metal layer composing the stacked layer. A method of manufacturing a substrate for an electronic device uses the etchant, producing an electronic device having the substrate. In order to achieve the object, the etchant has fluoric acid, periodic acid and sulfuric acid wherein the total weight ratio of the fluoric acid and periodic acid is 0.05˜30 wt %, the weight ratio of the sulfuric acid is 0.05˜20 wt %, the weight ratio of periodic acid to fluoric acid is 0.01˜2 wt %. Also each layer of wiring (5, 12, 14) formed by stacking Al layer or Al alloy layer and Ti layer or Ti alloy layer can be uniformly etched to substantially equal etching rate by the etchant.Type: GrantFiled: September 5, 2001Date of Patent: April 10, 2007Assignee: LG.Philips LCD Co., LtdInventor: Gyoo Chul Jo
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Patent number: 7196013Abstract: Numerous embodiments of a method and apparatus for a capping layer are disclosed. In one embodiment, a method of forming a capping layer for a semiconductor device comprises forming one or more layers on at least a portion of the top surface of a semiconductor device, substantially planarizing at least one of the one or more layers, annealing at least a portion of the semiconductor device, and removing a substantial portion of the one or more layers, using one or more etching processes.Type: GrantFiled: December 12, 2002Date of Patent: March 27, 2007Assignee: Intel CorporationInventor: Mark Y. Liu
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Patent number: 7192835Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.Type: GrantFiled: May 27, 2004Date of Patent: March 20, 2007Assignees: NEC Electronics Corporation, NEC CorporationInventors: Hiroaki Tomimori, Hidemitsu Aoki, Toshiyuki Iwamoto
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Patent number: 7189656Abstract: Although an Ag—CdO-based material has excellent electric properties such as deposition resistance, arc resistance and low contact resistance, which are required for an electric contact, the discharge standard provision in Japan, EC Directive on Waste from Electrical and Electronic Equipment (WEEE) and the like have been directed toward disuse of Cd, as already known. Thus, the present invention is characterized in that after an atmosphere in a pressured oxidation furnace is replaced with oxygen, the temperature of an internal-oxidative Ag alloy prepared under a condition of a cold roll rate of 50 to 95% is gradually raised from a temperature of 200° C. or less in a pressured oxygen atmosphere with an oxygen pressure of 5 to 50 kg/cm2 and internal oxidation processing is performed with an upper limit temperature of 700° C.Type: GrantFiled: August 15, 2002Date of Patent: March 13, 2007Assignee: Tokuriki Honten Co. Ltd.Inventors: Sadao Sato, Hideo Kumita, Kohei Tsuda, Mitsuo Yamasita, Kunio Shiokawa, Kenichi Kamiura, Kiyoshi Sekiguchi
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Patent number: 7186657Abstract: A wafer has a trench, a STI layer formed in the trench, an HfO2-containing gate dielectric covering the wafer and the STI layer, a gate electrode formed on the HfO2-containing gate dielectric, and at least a spacer formed beside the gate electrode. The wafer is preheated and a bromine-rich gas plasma is provided to remove portions of the HfO2-containing gate dielectric.Type: GrantFiled: June 30, 2005Date of Patent: March 6, 2007Assignee: United Microelectronics Corp.Inventors: Jeng-Huey Hwang, Wei-Tsun Shiau, Chien-Ting Lin, Jiunn-Ren Hwang
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Patent number: 7183203Abstract: A method of forming a copper oxide film including forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of fabricating a semiconductor device including burying a copper film to be a wiring or a contact wiring in a wiring groove or a contact hole formed in a surface of an insulating film formed on a semiconductor substrate, or in both the wiring groove and the contact hole, forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method, and removing the copper oxide film from the copper film using acid or alkali.Type: GrantFiled: November 1, 2004Date of Patent: February 27, 2007Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Uozumi
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Patent number: 7172976Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.Type: GrantFiled: January 29, 2004Date of Patent: February 6, 2007Assignee: United Microelectronics Corp.Inventor: Chih-Ning Wu
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Patent number: 7166543Abstract: Methods of forming a metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device are provided. A metal oxide surface that is enriched with metal oxide in its higher oxidation state for use in a semiconductor device is also provided.Type: GrantFiled: August 30, 2004Date of Patent: January 23, 2007Assignee: Micron Technology, Inc.Inventors: Stephen W. Russell, Max Hineman
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Patent number: 7160482Abstract: The present invention is related to a composition comprising an oxidizing compound and a complexing compound with the chemical formula wherein R1, R2, R3 and R4 are selected from the group consisting of H and any organic side chain. The oxidizing compound can be in the form of an aqueous solution. The complexing compound is for complexing metal ions. Metal ions can be present in the solution or in an external medium being contacted with the solution.Type: GrantFiled: December 21, 2001Date of Patent: January 9, 2007Assignees: IMEC vzw, Air Products and Chemicals, Inc.Inventors: Rita Vos, Paul Mertens, Albrecht Fester, Oliver Doll, Bernd Kolbesen
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Patent number: 7153775Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.Type: GrantFiled: August 30, 2005Date of Patent: December 26, 2006Assignee: Micron Technology, Inc,Inventors: Joseph E. Geusic, Alan R. Reinberg
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Patent number: 7153782Abstract: A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by combining HF at 49% concentration with H2O2 at 29%–30% concentration in deionized water.Type: GrantFiled: July 17, 2003Date of Patent: December 26, 2006Assignee: Texas Instruments IncorporatedInventor: Mona M. Eissa
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Patent number: 7151057Abstract: A method for manufacturing a flexible MEMS transducer includes forming a sacrificial layer on a flexible substrate, sequentially depositing a membrane layer, a lower electrode layer, an active layer, and an upper electrode layer on the sacrificial layer by PECVD, sequentially patterning the upper electrode layer, the active layer, and the lower electrode layer, depositing an upper protective layer to cover the upper electrode layer, the lower electrode layer, and the active layer, patterning the upper protective layer to be connected to the lower electrode layer and the upper electrode layer, and then depositing a connecting pad layer and patterning the connecting pad layer to form a first connecting pad to be connected to the lower electrode layer and a second connecting pad to be connected to the upper electrode layer; and patterning the membrane layer to expose the sacrificial layer and removing the sacrificial layer.Type: GrantFiled: September 25, 2003Date of Patent: December 19, 2006Assignee: Samsung Electronics Co., Ltd.Inventors: Yun-woo Nam, Suk-han Lee
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Patent number: 7147798Abstract: The present invention provides an aluminum etchant solution for etching an aluminum surface in the presence of solder bumps. The etchant solution includes about 42% to about 80% phosphoric acid; about 0.1% to about 6% nitric acid; about 5% to about 40% acetic acid; about 0.005% to about 5% of an amine oxide surfactant; about 0.1% to about 8% of a Pb solubilizing additive; and about 5 to about 25% de-ionized water; wherein the solder bumps are substantially phosphate free after the etching. Also provided is a process for etching an exposed aluminum surface in a semiconductor structure in the presence of solder bumps including the steps of: contacting the exposed aluminum surface with the etchant solution; rinsing the semiconductor structure with de-ionized water; and drying the semiconductor structure to remove residual water; wherein the solder bumps are substantially phosphate free after the etching.Type: GrantFiled: August 19, 2004Date of Patent: December 12, 2006Assignee: Arch Specialty Chemicals, Inc.Inventors: Frank Gonzalez, Emil Kneer, Michelle Elderkin, Vince Leon
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Patent number: 7138342Abstract: Process for combined chemical cleaning and etching of parts made of aluminum and/or aluminum alloys including: (a) providing a cleaning and etching solution including 5–30 grams/liter of phosphoric acid; 5–30 grams/liter of hydrogen fluoride; 120–220 grams/liter of sulfamic acid; 55–85.0 grams/liter of glycol ether; and balance water; (b) contacting the parts with the solution for a time sufficient to achieve the desired amount of cleaning and etching; (c) periodically measuring the etching rate of the solution; (d) when the etching rate is below the required minimum rate, adding sufficient hydrogen fluoride to restore the etching rate above the required minimum rate; and (e) periodically adding sufficient sulfamic acid to prevent the formation of scale made of hydrated aluminum fluoride.Type: GrantFiled: October 31, 2003Date of Patent: November 21, 2006Assignee: The Boeing CompanyInventors: Cathleen H. Chang, Terry C. Tomt
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Patent number: 7135444Abstract: A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is ascorbic acid or is an organic acid having two or more carboxylic acid groups (e.g., citric acid). The water can be present in about 40 wt. % to about 85 wt. % of the composition, the phosphoric acid can be present in about 0.01 wt. % to about 10 wt. % of the composition, and the organic acid can be present in about 10 wt. % to about 60 wt. % of the composition. The composition can be used for cleaning various surfaces, such as, for example, patterned metal layers and vias by exposing the surfaces to the composition.Type: GrantFiled: July 1, 2002Date of Patent: November 14, 2006Assignee: Micron Technology, Inc.Inventors: Donald L. Yates, Max F. Hineman
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Patent number: 7132367Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.Type: GrantFiled: May 20, 2003Date of Patent: November 7, 2006Assignee: Hitachi, Ltd.Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
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Patent number: 7128844Abstract: A metal layer 12 of aluminum or an aluminum alloy is formed on at least one side of a ceramic substrate 10, and a resist 14 having a predetermined shape is formed on the metal layer 12. Then, an etchant of a mixed solution prepared by mixing ferric chloride with water without adding any acids is used for etching and removing an undesired portion of the metal layer 12 to form a metal circuit 12 on the at least one side of the ceramic substrate 10.Type: GrantFiled: May 27, 2004Date of Patent: October 31, 2006Assignee: Dowa Mining Co., Ltd.Inventors: Nobuyoshi Tsukaguchi, Michihiro Kosaka
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Patent number: 7129160Abstract: A method and apparatus for simultaneously removing conductive materials from a microelectronic substrate. A method in accordance with one embodiment of the invention includes contacting a surface of a microelectronic substrate with an electrolytic liquid, the microelectronic substrate having first and second different conductive materials. The method can further include controlling a difference between a first open circuit potential of the first conducive material and a second open circuit potential of the second conductive material by selecting a pH of the electrolytic liquid. The method can further include simultaneously removing at least portions of the first and second conductive materials by passing a varying electrical signal through the electrolytic liquid and the conductive materials. Accordingly, the effects of galvanic interactions between the two conductive materials can be reduced and/or eliminated.Type: GrantFiled: August 29, 2002Date of Patent: October 31, 2006Assignee: Micron Technology, Inc.Inventor: Dinesh Chopra
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Patent number: 7129182Abstract: A method for etching a metal layer is described. That method comprises forming a metal layer on a substrate, then exposing part of the metal layer to a wet etch chemistry that comprises an active ingredient with a diameter that exceeds the thickness of the metal layer.Type: GrantFiled: November 6, 2003Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: Justin K. Brask, Mark L. Doczy, Jack Kavalieros, Uday Shah, Matthew V. Metz, Robert S. Chau, Robert B. Turkot, Jr.
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Patent number: 7122484Abstract: A method for removing organic material from an opening in a low k dielectric layer and above a metal layer on a substrate is disclosed. An ozone water solution comprised of one or more additives such as hydroxylamine or an ammonium salt is applied as a spray or by immersion. A chelating agent may be added to protect the metal layer from oxidation. A diketone may be added to the ozone water solution or applied in a gas or liquid phase in a subsequent step to remove any metal oxide that forms during the ozone treatment. A supercritical fluid mixture that includes CO2 and ozone can be used to remove organic residues that are not easily stripped by one of the aforementioned liquid solutions. The removal method prevents changes in the dielectric constant and refractive index of the low k dielectric layer and cleanly removes residues which improve device performance.Type: GrantFiled: April 28, 2004Date of Patent: October 17, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Baw-Ching Perng, Yi-Chen Huang, Jun-Lung Huang, Bor-Wen Chan, Peng-Fu Hsu, Hsin-Ching Shih, Lawrance Hsu, Hun-Jan Tao
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Patent number: 7115526Abstract: The present invention discloses an electrode structure of a light emitted diode and manufacturing method of the electrodes. After formed a pn junction of a light emitted diode on a substrate, a layer of SiO2 is deposited on the periphery of the die of the LED near the scribe line of the wafer, then a transparent conductive layer is deposited blanketly, then a layer of gold or AuGe etc. is formed with an opening on the center of the die. After forming alloy with the semiconductor by heat treatment to form ohmic contact, a strip of aluminum (Al) is formed on one side of the die on the front side for wire bonding and to be the positive electrode of the LED. The negative electrode is formed on the substrate by metal contact.Type: GrantFiled: March 18, 2002Date of Patent: October 3, 2006Assignee: Grand Plastic Technology Corporation TaiwanInventors: Hsieh Yue Ho, Chih-Cheng Wang, Hsiao Shih-Yi, Kang Tsung-Kuei, Bing-Yue Tsui, Chih-Feng Huang, Jann-Shyang Liang, Ming-Huan Tsai, Hun-Jan Tao, Baw-ching Perng
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Patent number: 7115527Abstract: This invention methods of etching an aluminum oxide comprising substrate, and methods of forming capacitors. In one implementation, a method of etching an aluminum oxide comprising substrate includes flowing water and ozone to aluminum oxide on the substrate, with at least one of the water and the ozone being at a temperature of at least 65° C. at the aluminum oxide effective to etch aluminum oxide from the substrate. In one implementation, aspects of the method are utilized in forming a capacitor.Type: GrantFiled: July 19, 2004Date of Patent: October 3, 2006Assignee: Micron Technology, INc.Inventor: Kevin R. Shea
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Patent number: 7104267Abstract: A process for treating a copper or copper alloy substrate surface with a composition and corrosion inhibitor solution to minimize defect formation and surface corrosion, the method including applying a composition including one or more chelating agents, a pH adjusting agent to produce a pH between about 3 and about 11, and deionized water, and then applying a corrosion inhibitor solution. The composition may further comprise a reducing agent and/or corrosion inhibitor. The method may further comprise applying the corrosion inhibitor solution prior to treating the substrate surface with the composition.Type: GrantFiled: November 29, 2000Date of Patent: September 12, 2006Assignee: Applied Materials Inc.Inventors: Ramin Emami, Shijian Li, Sen-Hou Ko, Fred C. Redeker, Madhavi Chandrachood
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Patent number: 7101809Abstract: In the case that a stacked layer, in which another metal layer is stacked on an Al layer or Al alloy layer having a low resistance, is used as a wiring material, an etchant is provided which can etch to a substantially equal etching rate by executing only one etching on the each metal layer composing the stacked layer. A method of manufacturing a substrate for an electronic device uses the etchant, producing an electronic device having the substrate. In order to achieve the object, the etchant has fluoric acid, periodic acid and sulfuric acid wherein the total weight ratio of the fluoric acid and periodic acid is 0.05˜30 wt %, the weight ratio of the sulfuric acid is 0.05˜20 wt %, the weight ratio of periodic acid to fluoric acid is 0.01˜2 wt %. Also each layer of wiring (5, 12, 14) formed by stacking Al layer or Al alloy layer and Ti layer or Ti alloy layer can be uniformly etched to substantially equal etching rate by the etchant.Type: GrantFiled: February 2, 2005Date of Patent: September 5, 2006Assignee: LG.Philips LCD Co., Ltd.Inventor: Gyoo Chul Jo
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Patent number: 7098136Abstract: Embedded flush circuitry features are provided by providing a carrier foil having an electrically conductive layer therein and coating the electrically conductive layer with a dielectric material. Circuitry features are formed in the dielectric material and conductive metal is plated to fill the circuitry features.Type: GrantFiled: August 20, 2004Date of Patent: August 29, 2006Assignee: International Business Machines CorporationInventors: Ronald Clothier, Jeffrey Alan Knight, Robert David Sebesta
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Patent number: 7094131Abstract: A microelectronic substrate and method for removing conductive material from a microelectronic substrate. In one embodiment, the microelectronic substrate includes a conductive or semiconductive material with a recess having an initially sharp corner at the surface of the conductive material. The corner can be blunted or rounded, for example, by applying a voltage to an electrode in fluid communication with an electrolytic fluid disposed adjacent to the corner. Electrical current flowing through the corner from the electrode can oxidize the conductive material at the corner, and the oxidized material can be removed with a chemical etch process.Type: GrantFiled: June 21, 2001Date of Patent: August 22, 2006Assignee: Micron Technology, Inc.Inventors: Whonchee Lee, Scott G. Meikle, Scott E. Moore
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Patent number: 7093356Abstract: A wiring substrate with bumps protruding from a surface of the substrate covers one side of a metallic base with an electrical insulating film thereon, having open holes exposing the base, etching the base through the open holes to form concavities in the base, electroplating the interior faces of the concavities to form a barrier metal film thereon filling the concavities with a bump material by electroplating, and forming a barrler layer on the bump material in each concavity. A stack of wiring patterns is formed on the insulating film, adjacent wiring patterns being separated by a respective intervening insulating layer and being electrically connected to each other through vias in the intervening insulating layer, and to the bump material filled in the concavities. Thereafter, the base and barrier metal film are removed.Type: GrantFiled: September 15, 2003Date of Patent: August 22, 2006Assignee: Shinko Electric Industries Co., Ltd.Inventors: Kei Imafuji, Tadashi Kodaira, Takeshi Chino, Jyunichi Nakamura, Miwa Abe
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Patent number: 7087534Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.Type: GrantFiled: August 31, 2004Date of Patent: August 8, 2006Assignee: Micron Technology, Inc.Inventor: Gary Chen
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Patent number: 7067465Abstract: A composition for use in semiconductor processing wherein the composition comprises water, phosphoric acid, and an organic acid; wherein the organic acid is ascorbic acid or is an organic acid having two or more carboxylic acid groups (e.g., citric acid). The water can be present in about 40 wt. % to about 85 wt. % of the composition, the phosphoric acid can be present in about 0.01 wt. % to about 10 wt. % of the composition, and the organic acid can be present in about 10 wt. % to about 60 wt. % of the composition. The composition can be used for cleaning various surfaces, such as, for example, patterned metal layers and vias by exposing the surfaces to the composition.Type: GrantFiled: July 1, 2002Date of Patent: June 27, 2006Assignee: Micron Technology, Inc.Inventors: Donald L. Yates, Max F. Hineman
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Patent number: 7067016Abstract: A method for post-etch cleaning of a substrate with MRAM structures and MJT structures and materials is disclosed. The method includes inserting the substrate into a first brush box configured for double-sided mechanical cleaning of the substrate. A non-HF, copper compatible chemistry is introduced into the first brush box for cleaning the active and backside surfaces of the substrate. The substrate is then inserted into a second brush box which is also configured to provide double-sided mechanical cleaning of the active and backside surfaces of the substrate. A burst of chemistry is introduced into the second brush box followed by a DIW rinse. The substrate is then processed through an SRD apparatus for final rinse and dry.Type: GrantFiled: March 31, 2003Date of Patent: June 27, 2006Assignee: Lam Research CorporationInventors: Katrina Mikhaylichenko, Michael Ravkin