Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/754)
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Patent number: 7060631Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl?, NO3? and F?. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.Type: GrantFiled: May 16, 2005Date of Patent: June 13, 2006Assignee: Micron Technology, Inc.Inventor: Paul A. Morgan
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Patent number: 7049245Abstract: A method for manufacturing a semiconductor device that comprises defining a semiconductor substrate, forming a gate oxide on the semiconductor substrate, forming a polycrystalline silicon layer over the gate oxide, forming a tungsten silicide layer over the polycrystalline silicon layer; providing a mask over the tungsten silicide layer, defining the mask to expose at least one portion of the tungsten silicide layer, etching the exposed tungsten silicide layer with a first etchant, wherein some tungsten silicide layer remains, etching the remaining tungsten silicide layer with a second etchant to expose at least one portion of the polycrystalline silicon layer, annealing the tungsten silicide layer, etching the exposed polycrystalline silicon layer, and oxidizing sidewalls of the tungsten silicide layer and the polycrystalline silicon layer.Type: GrantFiled: September 12, 2003Date of Patent: May 23, 2006Assignee: ProMOS Technologies, Inc.Inventors: Fang-Yu Yeh, Chi Lin, Chia-Yao Chen
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Patent number: 7037849Abstract: A method of patterning a layer of high-k dielectric material is provided, which may be used in the fabrication of a semiconductor device. A first etch is performed on the high-k dielectric layer. A portion of the high-k dielectric layer being etched with the first etch remains after the first etch. A second etch of the high-k dielectric layer is performed to remove the remaining portion of the high-k dielectric layer. The second etch differs from the first etch. Preferably, the first etch is a dry etch process, and the second etch is a wet etch process. This method may further include a process of plasma ashing the remaining portion of the high-k dielectric layer after the first etch and before the second etch.Type: GrantFiled: June 27, 2003Date of Patent: May 2, 2006Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsien-Kuang Chiu, Baw-Ching Perng, Hun-Jan Tao
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Patent number: 7030033Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.Type: GrantFiled: September 16, 2003Date of Patent: April 18, 2006Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
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Patent number: 7029937Abstract: A depression is formed from a first surface of a semiconductor substrate. An insulating layer is provided on the bottom surface and an inner wall surface of the depression. A conductive portion is provided inside the insulating layer. A second surface of the semiconductor substrate is etched by a first etchant having characteristics such that the etching amount with respect to the semiconductor substrate is greater than the etching amount with respect to the insulating layer, and the conductive portion is caused to project while covered by the insulating layer. At least a portion of the insulating layer formed on the bottom surface of the depression is etched with a second etchant having characteristics such that at least the insulating layer is etched without forming a residue on the conductive portion, to expose the conductive portion.Type: GrantFiled: November 10, 2003Date of Patent: April 18, 2006Assignee: Seiko Epson CorporationInventor: Ikuya Miyazawa
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Patent number: 7030032Abstract: A method for passivating a photodiode so as to reduce dark current, Isdark, due to the exposed semiconductor material on the sidewall of the device. The method includes etching away sidewall surface damage using a succinic acid-hydrogen peroxide based sidewall etch. This is followed by a subsequent hydrochloric acid (HCl)-based surface treatment which completes the surface treatment and reduces the dark current Isdark. Finally, a polymer coating of benzocyclobutene (BCB) is applied after the surface treatment to stabilize the surface and prevent oxidation and contamination which would otherwise raise the dark current were the diodes left with no coating. The BCB is then etched away from the contact pad areas to allow wirebonding and other forms of electrical contact to the diodes. Such method effectively stabilizes the etched surfaces of photodiodes resulting in significantly reduced and stable dark current.Type: GrantFiled: May 13, 2003Date of Patent: April 18, 2006Assignee: Raytheon CompanyInventors: Philbert Francis Marsh, Colin Steven Whelan
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Patent number: 7018939Abstract: A method is provided herein for cleaning a semiconductor device. In accordance with the method, a semiconductor device is provided (11), and a micellar solution is applied (13) to the semiconductor device. The method is particularly useful for cleaning copper and silicon surfaces and removing processing residues from the surfaces of vias or trenches.Type: GrantFiled: July 11, 2003Date of Patent: March 28, 2006Assignee: Motorola, Inc.Inventor: Balgovind K. Sharma
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Patent number: 7001849Abstract: A method for treatment of the surface of a CdZnTe (CZT) crystal that provides a native dielectric coating to reduce surface leakage currents and thereby, improve the resolution of instruments incorporating detectors using CZT crystals. A two step process is disclosed, etching the surface of a CZT crystal with a solution of the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, passivating the CZT crystal surface with a solution of 10 w/o NH4F and 10 w/o H2O2 in water.Type: GrantFiled: December 19, 2002Date of Patent: February 21, 2006Assignee: Sandia National LaboratoriesInventors: Gomez W. Wright, Ralph B. James, Arnold Burger, Douglas A. Chinn
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Patent number: 6998352Abstract: A cleaning solution having an oxidation-reduction potential lower than that of pure water and a pH value of 4 or below is used to remove metal contamination, thereby efficiently removing the metal contamination adhered onto a surface of a substrate without damaging an underlayer.Type: GrantFiled: October 31, 2002Date of Patent: February 14, 2006Assignee: NEC Electronics CorporationInventors: Hidemitsu Aoki, Hiroaki Tomimori, Kenichi Yamamoto
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Patent number: 6992342Abstract: A magnetic memory device, in which a tunnel magneto resistance element that establishes a connection between a write word line (first interconnection) and a bit line (second interconnection) is provided within a region in which the write word line and the bit line cross in a grade-separated manner. The magnetic memory device comprises a through hole that is provided in such a manner that is insulated from the write word line and also extending through the write word line so as to establish a connection between the tunnel magneto resistance element and a second landing pad (interconnection layer) lower than the write word line, and a contact that is formed in the through hole through a side wall barrier film so as to establish a connection between the tunnel magneto resistance element and the second landing pad.Type: GrantFiled: July 2, 2003Date of Patent: January 31, 2006Assignee: Sony CorporationInventors: Makoto Motoyoshi, Minoru Ikarashi
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Patent number: 6987063Abstract: A metal-containing semiconductor layer having a high dielectric constant is formed with a method that avoids inclusion of contaminant elements that reduce dielectric constant of metals. The metal-containing semiconductor layer is formed overlying a substrate in a chamber. A precursor is introduced to deposit at least a portion of the metal-containing semiconductor layer. The precursor contains one or more elements that, if allowed to deposit in the metal-containing layer, would become impurity elements. A reactant gas is used to purify the metal-containing layer by removing impurity elements from the metal-containing layer which were introduced into the chamber by the precursor.Type: GrantFiled: June 10, 2004Date of Patent: January 17, 2006Assignee: Freescale Semiconductor, Inc.Inventors: Olubunmi O. Adetutu, James K. Schaeffer, Dina H. Triyoso
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Patent number: 6984585Abstract: A method for removal of residues after plasma etching a film stack comprising a first layer and a sacrificial layer. The method treats a substrate containing the film stack after the first layer of the film stack has been etched to remove residue produced during the etching process. The treatment is performed in a buffered oxide etch wet dip solution that removes the residue and the sacrificial layer.Type: GrantFiled: August 12, 2002Date of Patent: January 10, 2006Inventors: Chentsau Ying, Xiaoyi Chen, Padmapani C. Nallan, Ajay Kumar
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Patent number: 6972257Abstract: A patterning method includes providing a first material (e.g., copper) and transforming at a least a surface region of the first material to a second material (e.g., copper oxide). One or more portions of the second material (e.g., copper oxide) are converted to one or more converted portions of first material (e.g., copper) while one or more portions of the second material (e.g., copper oxide) remain. One or more portions of the remaining second material (e.g., copper oxide) are removed selectively relative to converted portions of first material (e.g., copper). Further, a thickness of the converted portions may be increased. Yet further, a diffusion barrier layer may be used for certain applications.Type: GrantFiled: June 16, 2003Date of Patent: December 6, 2005Assignee: Micron Technology, Inc.Inventors: Joseph E. Geusic, Alan R. Reinberg
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Patent number: 6969688Abstract: A wet etchant solution composition and method for etching oxides of hafnium and zirconium including at least one solvent present at greater than about 50 weight percent with respect to an arbitrary volume of the wet etchant solution; at least one chelating agent present at about 0.1 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution; and, at least one halogen containing acid present from about 0.0001 weight percent to about 10 weight percent with respect to an arbitrary volume of the wet etchant solution.Type: GrantFiled: October 8, 2002Date of Patent: November 29, 2005Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Baw-Ching Perng, Fang-Cheng Chen, Hun-Jan Tao, Peng-Fu Hsu, Yue-Ho Hsieh, Chih-Cheng Wang, Shih-Yi Hsiao
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Patent number: 6967174Abstract: A wafer chuck includes alignment members that allows a semiconductor wafer to be properly aligned on the chuck without using a separate alignment stage. The alignment members may be cams, for example, attached to arms of the wafer chuck. These members may assume an alignment position when a robot arm places the wafer on the chuck. In this position, they guide the wafer into a proper alignment position with respect to the chuck. During rotation at a particular rotational speed, the alignment members move away from the wafer to allow liquid etchant to flow over the entire edge region of the wafer. At still higher rotational speeds, the wafer is clamped into position to prevent it from flying off the chuck. A clamping cam or other device (such as the alignment member itself) may provide the clamping.Type: GrantFiled: February 3, 2003Date of Patent: November 22, 2005Assignee: Novellus Systems, Inc.Inventors: Steven T. Mayer, Steve Taatjes, Andy McCutcheon, Jim Schall, Jingbin Feng
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Patent number: 6960529Abstract: Methods for protecting the sidewall of a metal interconnect component using Physical Vapor Deposition (PVD) processes and using a single barrier metal material. After forming the metal interconnect component, a single barrier metal is deposited on its sidewall using PVD. A subsequent anisotropic etching of the barrier metal removes the barrier metal from the horizontal surface except for some that still remains on the top surface of the metal interconnect layer. A dielectric layer is then formed over the metal interconnect component and the barrier metal. The unlanded via is etched through the dielectric layer to the metal interconnect component, and then filled with a second metal to thereby allow the metal interconnect component to electrically connect with one or more upper metal layers.Type: GrantFiled: February 24, 2003Date of Patent: November 1, 2005Assignee: AMI Semiconductor, Inc.Inventors: Mark M. Nelson, Brett N. Williams, Jagdish Prasad
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Patent number: 6955992Abstract: A method of dry etching a PCMO stack, includes preparing a substrate; depositing a barrier layer; depositing a bottom electrode; depositing a PCMO thin film; depositing a top electrode; depositing a hard mask layer; applying photoresist and patterning; etching the hard mask layer; dry etching the top electrode; dry etching the PCMO layer in a multi-step etching process; dry etching the bottom electrode; and completing the PCMO-based device.Type: GrantFiled: September 30, 2003Date of Patent: October 18, 2005Assignee: Sharp Laboratories of America, Inc.Inventors: Fengyan Zhang, Sheng Teng Hsu
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Patent number: 6949397Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer having a lower redox potential than said material, the sacrificial metal layer being electrically connected to said noble metal layer.Type: GrantFiled: January 11, 2002Date of Patent: September 27, 2005Assignee: International Business Machines CorporationInventors: Michel Despont, Roy H. Magnuson, Ute Drechsler
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Patent number: 6949470Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 formed by laminating a first conductive film 11 and a second conductive film 12 is covered with a photoresist layer PR having opening portions 13 with inclined surfaces 13S, a conductive wiring layer 14 is formed in the opening portions by electrolytic plating to form inverted inclined surfaces 14R, and then, when covering the same with the sealing resin layer 21, an anchoring effect is produced by making the sealing resin layer 21 bite into the inverted inclined surfaces 14R so as to strengthen bonding of the sealing resin layer 21 with the conductive wiring layer 14.Type: GrantFiled: September 17, 2003Date of Patent: September 27, 2005Assignees: Sanyo Electric Co., Ltd., Kanto Sanyo Semiconductors Co., Ltd.Inventors: Yusuke Igarashi, Hideki Mizuhara, Noriaki Sakamoto
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Patent number: 6946402Abstract: A fabricating method of a polycrystalline silicon thin film transistor includes forming a polycrystalline silicon layer on a substrate having first and second regions through a crystallization process using nickel silicide (NiSix) as a catalyst, patterning the polycrystalline silicon layer to form an active layer at the first region, leaving a nickel silicide residue at the second region, etching the nickel silicide residue with a solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2), forming a gate electrode over the active layer and forming a source and drain in the active layer.Type: GrantFiled: December 16, 2002Date of Patent: September 20, 2005Assignee: LG. Philips LCD Co., Ltd.Inventors: Hyun-Sik Seo, Binn Kim
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Patent number: 6927082Abstract: Defective contact plug fills can be detected by applying an etching solution, which in some embodiments preferentially etches in the <111> direction. The etching solution is some embodiments may also produce a characteristic type of undercutting underneath the contact plug fill. Contact plug fills with defects in them have undercutting underneath as a result of the etchant exposure, while defective contact plug fills have no such undercutting. The contact plug fills that are now undercut by etching exposure are unable to dissipate surface charge or surface applied potential and can be detected using voltage contrast methods or conventional electrical testing techniques, for example.Type: GrantFiled: March 10, 2004Date of Patent: August 9, 2005Assignee: Intel CorporationInventors: Swaminathan Sivakumar, Oleg Golonzka, Timothy F. Crimmins
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Patent number: 6919276Abstract: A CMP process for selectively polishing an overlying material layer with an underlying layer comprising at least one material in a semiconductor device fabrication process including providing a semiconductor wafer process surface including a first material layer overlying a second layer including one material; mixing at least two slurry mixtures including a first CMP slurry formulation optimized for removing the first material layer and a second CMP slurry formulation optimized for removing the at least a second layer to form a slurry formulation mixture; and, carrying out a CMP process using the slurry formulation mixture to remove the first material layer and at least a portion of the at least a second layer.Type: GrantFiled: April 24, 2003Date of Patent: July 19, 2005Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Shen-Nan Lee, Ying-Ho Chen, Syun-Ming Jang, Tzu-Jen Chou, Jin-Yiing Song
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Patent number: 6908782Abstract: A p-type transparent conducting oxide film is provided which is consisting essentially of, the transparent conducting oxide and a molecular doping source, the oxide and doping source grown under conditions sufficient to deliver the doping source intact onto the oxide.Type: GrantFiled: August 17, 2001Date of Patent: June 21, 2005Assignee: Midwest Research InstittueInventors: Yanfa Yan, Shengbai Zhang
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Patent number: 6905974Abstract: A method for cleaning substrates to remove Group VIII metal-containing, particularly platinum-containing, residue using a cleaning composition that includes a peroxide-generating compound.Type: GrantFiled: August 8, 2002Date of Patent: June 14, 2005Assignee: Micron Technology, Inc.Inventor: Paul A. Morgan
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Patent number: 6900128Abstract: The present invention provides approaches for electroless deposition of conductive materials onto the surface of oxide-based materials, including nonconductive metal oxides, in a manner that does not require intervening conductive pastes, nucleation layers, or additional seed or activation layers formed over the surface of the oxide-based layer. According to one embodiment of the present invention, a layer of a titanium-based material is formed over an oxide-based surface. The layer of titanium-based material is subsequently removed from the surface of the oxide-based layer in a manner such that the surface of the oxide-based layer is activated for electroless deposition. A metal or metal alloy is then plated over the oxide-based surface using electroless plating techniques.Type: GrantFiled: August 30, 2004Date of Patent: May 31, 2005Assignee: Micron Technology, Inc.Inventor: Nishant Sinha
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Patent number: 6893893Abstract: A method for preventing electrical short circuits in a multi-layer magnetic film stack comprises providing a film stack that includes a layer of magnetic material having an exposed surface. A protective layer is deposited on the exposed surface of the magnetic layer. The protective layer may comprise, for example, a fluorocarbon or a hydrofluorocarbon. The film stack is etched and the protective layer protects the exposed surface from a conductive residue produced while etching the film stack. The method may be used in film stacks to form a magneto-resistive random access memory (MRAM) device.Type: GrantFiled: September 4, 2002Date of Patent: May 17, 2005Inventors: Padmapani C. Nallan, Ajay Kumar, Jeng H. Hwang, Guangxiang Jin, Ralph Kerns
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Patent number: 6892452Abstract: A Dry-Film resist formed of, for example, a photosensitive film is stacked on the electroconductive material and these portions, other than a projection electrode formation area, formed on a wiring board's electrode serving as a portion of a circuit pattern are masked with a mask. After this, the wiring board is exposed to light and, after the removal of the mask, a development process is performed, thus eliminating the Dry-Film resist on the wiring board at the portion other than the projection electrode formation area. Then the electroconductive material of the wiring board is etched under an etching process to provide a projection electrode having a bump with a pointed tapering end in vertical cross-section. Finally, the wiring board is exposed to a Dry-Film resist elimination solution to remove remaining Dry-Film resist from the projection electrode. And a plating process is performed on the electroconductive material to form a plated layer and hence complete the projection electrode.Type: GrantFiled: April 26, 2001Date of Patent: May 17, 2005Assignee: DDK Ltd.Inventors: Yasuo Fukuda, Masakatsu Nagata, Shoji Iwasaki, Osamu Nakao
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Patent number: 6878573Abstract: The invention relates to a method of manufacturing a semiconductor device (10), wherein a semiconductor element (1) provided with a number of connection regions (2) is fitted between a first, electroconductive plate (3) and a second plate (4), wherein two connection conductors (3A, 3B) are formed, from the first plate (3), for the two connection regions (2A, 2B) of the element (1), wherein a passivating encapsulation (5) is provided between the plates (3, 4) and around the element (1), and wherein the device (10) is formed by applying a mechanical separating technique in two mutually perpendicular directions (L, M). In a method according to the invention, the connection conductors (3A, 3B) are formed by providing a mask (6) on the first conducting plate (3) in such a manner that a part (3C) of the plate (3) situated between the connection regions (2A, 2B) remains exposed, which part is subsequently removed by etching.Type: GrantFiled: June 17, 2002Date of Patent: April 12, 2005Assignee: Koninklijke Philips Electronics N.V.Inventors: Johannus Wilhelmus Weekamp, Marc Andre De Samber, Durandus Kornelius Dijken
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Patent number: 6872659Abstract: The present invention provides approaches for electroless deposition of conductive materials onto the surface of oxide-based materials, including nonconductive metal oxides, in a manner that does not require intervening conductive pastes, nucleation layers, or additional seed or activation layers formed over the surface of the oxide-based layer. According to one embodiment of the present invention, a layer of a titanium-based material is formed over an oxide-based surface. The layer of titanium-based material is subsequently removed from the surface of the oxide-based layer in a manner such that the surface of the oxide-based layer is activated for electroless deposition. A metal or metal alloy is then plated over the oxide-based surface using electroless plating techniques.Type: GrantFiled: August 19, 2002Date of Patent: March 29, 2005Assignee: Micron Technology, Inc.Inventor: Nishant Sinha
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Patent number: 6869889Abstract: A metal carbide film may be etched in an etchant bath using sonication. The sonication may drive the reaction and, particularly, the gaseous byproducts in the form of carbon dioxide. Thus, the use of sonication invokes a favorable equilibrium to pattern metal carbide films, for example, for use as metal gate electrodes.Type: GrantFiled: April 7, 2004Date of Patent: March 22, 2005Assignee: Intel CorporationInventors: Justin K. Brask, Jack Kavalieros, Mark L. Doczy, Matthew V. Metz, Suman Datta, Uday Shah, Terence Bacuita, Robert S. Chau
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Method of forming patterned nickel and doped nickel films via microcontact printing and uses thereof
Patent number: 6866791Abstract: The process of derivatization and patterning of surfaces, and more particularly to the formation of self-assembled molecular monolayers on metal oxide surfaces using microcontact printing and the derivative articles produced thereby.Type: GrantFiled: May 2, 2000Date of Patent: March 15, 2005Assignee: International Business Machines CorporationInventors: Tricia L. Breen, Peter M. Fryer, Robert L. Wisnieff, John Christopher Flake -
Patent number: 6864177Abstract: A method for manufacturing of a metal line contact plug of a semiconductor device by performing a two step CMP process using (1) a first slurry solution having high etching selectivity of metal/insulating film and (2) a second slurry solution having small etching selectivity of metal/insulating film, thereby minimizing dependency on CMP devices and separating easily a metal line contact plug.Type: GrantFiled: December 26, 2002Date of Patent: March 8, 2005Assignee: Hynix Semiconductor Inc.Inventors: Jong Goo Jung, Ki Cheol Ahn, Pan Ki Kwon
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Patent number: 6838368Abstract: In a semiconductor device, a plurality of wiring films are formed on a front surface of a base comprising an insulating resin and having electrode-forming holes, the surfaces of the wiring films and the surface of the base being positioned on the same plane and at least parts of the wiring films overlapping with the electrode-forming holes; a conductive material is embedded into the electrode-forming holes to form external electrodes on the back surface, away from the wiring films, of the base; a semiconductor element is positioned on the front surface of the base with an insulating film therebetween, the back surface of the semiconductor element being bonded to said front surface of the base; wires bond the electrodes of the semiconductor element to the corresponding wiring films; and a resin seals the wiring films and the wires.Type: GrantFiled: November 10, 2000Date of Patent: January 4, 2005Assignee: Sony CorporationInventors: Kenji Ohsawa, Tomoshi Ohde
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Patent number: 6830500Abstract: A method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer includes use of a fixed-abrasive type polishing pad with a substantially abrasive-free slurry in which copper is removed at a rate that is substantially the same as or faster than a rate at which a material, such as tungsten, of the barrier layer is removed. The slurry is formulated so as to oxidize copper at substantially the same rate as or at a faster rate than a material of the barrier layer is oxidized. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry or the oxidation energy of the barrier layer material in the slurry may be greater than that of copper. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.Type: GrantFiled: April 25, 2002Date of Patent: December 14, 2004Assignee: Micron Technology, Inc.Inventors: Dinesh Chopra, Nishant Sinha
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Publication number: 20040242017Abstract: Gate lines including a lower Al—Nd layer and an upper MoW layer, data lines including a MoW layer, and pixel electrodes including an IZO layer are patterned using a single etchant. The etchant contains a phosphoric acid of about 50-60%, a nitric acid of about 6-10%, an acetic acid of about 15-25%, a stabilizer of about 2-5% stabilizer, and deionized water. The stabilizer includes oxy-hydride inorganic acid represented by M(OH)XLY, where M includes at least one of Zn, Sn, Cr, Al, Ba, Fe, Ti, Si and B, L includes at least one of H2O, NH3, CN and NH2R (where R is alkyl group), X is 2 or 3, and Y is 0, 1, 2 or 3.Type: ApplicationFiled: February 6, 2004Publication date: December 2, 2004Applicant: Samsung Electronics Co., Ltd.Inventors: Hong-Sick Park, Hong-Je Cho, Sung-Chul Kang, Pong-Ok Park, An-Na Park
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Publication number: 20040242018Abstract: An etching method that uses an etch reactant retained within at least a semi-solid media (120, 220, 224, 230). The etch reactant media is applied to selectively etch a surface layer (106, 218, 222). The etch reactant media may be applied to remove metal shorts (222), smearing and eaves resulting from CMP or in failure analysis for uniform removal of a metal layer (218) without damaging the vias, contact, or underlying structures.Type: ApplicationFiled: April 22, 2004Publication date: December 2, 2004Inventor: Darwin Rusli
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Publication number: 20040229474Abstract: The present invention provides a method for treating the wafer surface, suitable for removing residues on the wafer surface. The method includes forming a photo-sensitive material layer over the wafer surface covering the bumps and the under bump metallurgy layer on the wafer surface. Using the bumps as masks, the photo-sensitive material layer is exposed and developed, to expose the wafer surface between the bumps. A wet etching process is then performed to remove residues on the exposed wafer surface and then the remained photo-sensitive material layer is removed. Therefore, no residues remain on the wafer surface, and the yield of the bumps is increased.Type: ApplicationFiled: March 2, 2004Publication date: November 18, 2004Inventors: Chi-Long Tsai, Min-Lung Huang
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Patent number: 6818556Abstract: A method of forming a copper oxide film includes forming a copper oxide film including an ammonia complex by causing a mixed solution of aqueous ammonia and aqueous hydrogen peroxide, which has been adjusted to have pH of 8 to 10 or pH of 9 to 10, to contact a surface of a copper film. A method of fabricating a semiconductor device includes burying a copper film to be a wiring or a contact wiring in a wiring groove or a contact hole formed in a surface of an insulating film formed on a semiconductor substrate, or in both the wiring groove and the contact hole, forming a copper oxide film including an ammonia complex on a surface of the copper film by using the copper oxide film forming method, and removing the copper oxide film from the copper film using acid or alkali.Type: GrantFiled: September 4, 2002Date of Patent: November 16, 2004Assignee: Kabushiki Kaisha ToshibaInventor: Yoshihiro Uozumi
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Publication number: 20040224518Abstract: The invention relates to a ball-limiting metallurgy (BLM) etching system and process. The BLM stack is provided for an electrical device that contains an aluminum layer disposed upon a metal first layer. A metal upper layer is disposed above the metal second layer, and an alternative metal third layer is disposed between the metal second layer and the metal upper layer. The etching system and process utilizes an etching solution that includes a nitrogen-containing heterocyclic compound, an ammonium hydroxide compound, an oxidizer, and a metal halide compound. Etching conditions prevent any metallization that is dissolved from redepositing, thus avoiding lowered yields.Type: ApplicationFiled: June 14, 2004Publication date: November 11, 2004Inventors: Donald Danielson, Tzeun-luh Huang, Dawn L. Scovell, Keith Willis
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Patent number: 6815368Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.Type: GrantFiled: January 15, 2003Date of Patent: November 9, 2004Assignee: Micron Technology, Inc.Inventor: Gary Chen
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Method to reduce residual particulate contamination in CVD and PVD semiconductor wafer manufacturing
Patent number: 6812156Abstract: A method of reducing particulate contamination in a deposition process including providing a semiconductor wafer having a process surface for depositing a deposition layer thereover according to one of a physical vapor deposition (PVD) and a chemical vapor deposition (CVD) process; depositing at least a portion of the deposition layer over the process surface; cleaning the semiconductor wafer including the process surface according to an ex-situ cleaning process to remove particulate contamination including at least one of spraying and scrubbing; and, repeating the steps of depositing and cleaning at least once to include reducing a level of occluded particulates.Type: GrantFiled: July 2, 2002Date of Patent: November 2, 2004Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Dyson Day, Mei-Yen Li, Ming-Te More, Hsing-Yuan Chu -
Patent number: 6806206Abstract: A silver or silver alloy thin layer on a substrate is etched by an etching liquid uniformly without producing an etching residue while avoiding side etching due to over etching. The etching liquid contains silver ions in a range from 0.005 to 1 weight %. The etching liquid is fed to a tank or an etching liquid feeding apparatus, and then brought into contact with the silver or silver alloy thin layer on the substrate.Type: GrantFiled: July 18, 2002Date of Patent: October 19, 2004Assignees: Sony Corporation, St Liquid Crystal Display Corporation, Mitsubishi Chemical CorporationInventors: Masaki Munakata, Hirohito Komatsu, Satoshi Kumon, Kazuma Teramoto, Nobuhiro Goda, Masakazu Motoi, Noriyuki Saitou, Toshiaki Sakakihara, Makoto Ishikawa
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Patent number: 6803323Abstract: A passive integrated component (10) is formed overlying a semiconductor substrate by etching a composite conductive layer using a solution of sodium persulfate or ceric ammonium nitrate to remove a lower portion of the composite copper layer (64) exposed by an upper portion of the composite copper layer (74, 76, 78) to expose an underlying surface (62).Type: GrantFiled: May 30, 2002Date of Patent: October 12, 2004Assignee: Freescale Semiconductor, Inc.Inventors: Lakshmi Narayan Ramanathan, Douglas G. Mitchell, Varughese Mathew
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Patent number: 6800564Abstract: In a method of fabricating a TFT array substrate, a gate wire is formed on an insulating substrate. The gate wire has gate lines, gate electrodes, and gate pads connected to the gate lines. A gate insulating layer and a semiconductor layer are formed in sequence. A data wire is formed, which includes data lines intersecting the gate lines, source electrodes connected to the data lines and placed close to the gate electrodes, drain electrodes opposite the source electrodes with respect to the gate electrodes, and data pads connected to the data lines. A protective layer is deposited, and is patterned to form contact holes exposing at least the drain electrodes. A silver or silver alloy conductive layer is deposited on the protective layer.Type: GrantFiled: July 5, 2002Date of Patent: October 5, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Hong-Sick Park, Sung-Chul Kang
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Patent number: 6797638Abstract: A method for etching phase shift layers of half-tone phase masks includes etching a phase shift layer by using a plasma which is obtained from CH3F and O2. A high cathode power is used for the etching. The method has a very high selectivity between the substrate and the phase shift layer, so that half-tone phase masks with a high imaging quality can be produced.Type: GrantFiled: May 31, 2002Date of Patent: September 28, 2004Assignees: Infineon Technologies AG, Applied Materials GmbHInventors: Norbert Falk, Günther Ruhl
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Patent number: 6794307Abstract: A method for removing a dielectric anti-reflective coating (DARC) of silicon oxynitride material from a layer of insulative material which is formed over a substrate in a semiconductor device involves contacting the DARC material with a mixture of tetramethylammonium fluoride and at least one acid such as hydrofluoric acid, hydrochloric acid, nitric acid, phosphoric acid, acetic acid, citric acid, sulfuric acid, carbonic acid or ethylenediamine tetraacetic acid. Contact with the mixture is for a time period sufficient to remove substantially all of the DARC material. The mixture has a high etch rate selectivity such that the DARC coating can be removed with minimal effect on the underlying insulative layer.Type: GrantFiled: May 2, 2003Date of Patent: September 21, 2004Assignee: Micron Technology, Inc.Inventors: Gary Chen, Li Li
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Patent number: 6794304Abstract: A method of making a semiconductor device includes providing a first element formed of a first substantially electrically conductive material and having an upper surface. A second element adjacent to the first element is provided. The second element is formed of a first substantially non-electrically conductive material. An upper surface of the second element slopes downwardly toward the upper surface of the first element. A first layer of a second substantially non-electrically conductive material is disposed over the upper surface of the first element and the upper surface of the second element. The first layer has a thickness in the vertical direction that is greater in an area over the downward slope of the second element than in an area over the first element. An etching process is performed such that the layer is perforated above the upper surface of the first element and imperforated in the vertically thicker area above the downwardly sloping upper surface of the second element.Type: GrantFiled: July 31, 2003Date of Patent: September 21, 2004Assignee: LSI Logic CorporationInventors: Shiqun Gu, Masaichi Eda, Peter McGrath, Hong Lin, Jim Elmer
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Patent number: 6794292Abstract: An extrusion-free wet cleaning process for post-etch Cu-dual damascene structures is developed. The process includes the following steps: (1). providing a wafer having a silicon substrate and at least one post-etch Cu-dual damascene structure, the post-etch Cu-dual damascene structure having a via structure exposing a portion of a Cu wiring line electrically connected with an N+ diffusion region of the silicon substrate, and a trench structure formed on the via structure; (2). applying a diluted H2O2 solution on the wafer to slightly oxidize the surface of the exposed Cu wiring line; (3). washing away cupric oxide generated in the oxidation step by means of an acidic cupric oxide cleaning solution containing diluted HF, NH4F or NH2OH; and (4). providing means for preventing Cu reduction reactions on the Cu wiring line.Type: GrantFiled: July 16, 2001Date of Patent: September 21, 2004Assignee: United Microelectronics Corp.Inventor: Chih-Ning Wu
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Patent number: 6790711Abstract: A method of manufacturing a semiconductor device using a lead frame composed of a plate-like body having a non-planar upper surface and a planar under surface. The plate-like body includes a first thin portion for mounting a semiconductor chip with pad electrodes, first thick portions radially arranged for forming lead electrodes respectively corresponding to the pad electrodes of the semiconductor chip, a second thin portion between pairs of the first thick portions, a third thin portion peripherally surrounding the first thick portions, and a second thick portion surrounding the third thin portion. The semiconductor chip and the lead electrodes are sealed to the same surface as all of the thin portions with a resin, after making a connection between the pad electrodes and the lead electrodes with connecting wires.Type: GrantFiled: September 17, 2003Date of Patent: September 14, 2004Assignee: Mitsubishi Denki Kabushiki KaishaInventor: Yoshiharu Takahashi
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Patent number: 6790786Abstract: The invention includes semiconductor processing methods, including methods of forming capacitors. In one implementation, a semiconductor processing method includes providing a semiconductor substrate comprising a layer comprising at least one metal in elemental or metal alloy form. The metal comprises an element selected from the group consisting of platinum, ruthenium, rhodium, palladium, iridium, and mixtures thereof. At least a portion of the layer is etched in a halogenide, ozone and H2O comprising ambient.Type: GrantFiled: March 5, 2002Date of Patent: September 14, 2004Assignee: Micron Technology, Inc.Inventors: Paul A. Morgan, Patrick M. Flynn, Janos Fucsko