Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/754)
  • Patent number: 8075791
    Abstract: A chemical treatment apparatus and a method for performing a chemical treatment of a wafer, etc., by supplying a chemical via a cell. The apparatus includes a cylindrical inner cell and a cylindrical outer cell with open ends disposed at an outer circumference of the inner cell. The outer cell is axially movable to vary the width of a slit formed between a bottom end of the outer cell and a top surface of the substrate-holding means by the axial movement, thereby adjusting the discharge rate of the chemical and varying the pressure of the chemical.
    Type: Grant
    Filed: September 26, 2008
    Date of Patent: December 13, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Yoshiaki Tomari
  • Patent number: 8062429
    Abstract: The present invention relates to aqueous compositions comprising amidoxime compounds and methods for cleaning plasma etch residue from semiconductor substrates including such dilute aqueous solutions. The compositions of the invention may optionally contain one or more other acid compounds, one or more basic compounds, and a fluoride-containing compound and additional components such as organic solvents, chelating agents, amines, and surfactants. The invention also relates to a method of removing residue from a substrate during integrated circuit fabrication.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 22, 2011
    Assignee: EKC Technology, Inc.
    Inventor: Wai Mun Lee
  • Patent number: 8057689
    Abstract: According to one embodiment, a method of manufacturing a magnetic recording medium includes forming a first hard mask, a second hard mask and a resist on a magnetic recording layer, imprinting a stamper to the resist to transfer patterns of protrusions and recesses to the resist, removing residues remaining in the recesses of the patterned resist by means of a first etching gas, etching the second hard mask by means of the first etching gas using the patterned resist as a mask to transfer the patterns to the second hard mask, etching the first hard mask by means of a second etching gas different from the first etching gas using the second hard mask as a mask to transfer the patterns to the first hard mask, and performing ion beam etching in order to deactivate the magnetic recording layer exposed in the recesses and to remove the second hard mask.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: November 15, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Isowaki, Kaori Kimura, Yoshiyuki Kamata, Masatoshi Sakurai
  • Patent number: 8052882
    Abstract: A method of manufacturing a wiring substrate of the present invention, includes the steps of forming a seed layer on an underlying layer, forming a plating resist in which an opening portion is provided on the seed layer, forming a copper plating layer in the opening portion by an electroplating, removing the plating resist, wet-etching the seed layer using the copper plating layer as a mask to obtain the wiring layer, roughening a surface of the wiring layer by a blackening process, and forming an insulating layer on the wiring layer, wherein a surface of the copper plating layer is soft-etched simultaneously in the step of etching the seed layer, whereby a soft etching step of the wiring layer carried out prior to the step of the blackening process is omitted.
    Type: Grant
    Filed: April 17, 2009
    Date of Patent: November 8, 2011
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventor: Hitoshi Kondo
  • Publication number: 20110269311
    Abstract: The present disclosure relates to an implantable medical device. The implantable medical device includes a component comprising a first substrate bonded to a second substrate. A method for forming the component includes removing a first portion of tin (Sn) from gold tin (AuSn) through a halogen plasma. A first portion of gold (Au) is exposed in response to removing the first portion of the Sn. The first portion of the Au through a wet etch. A second portion of the Sn is exposed in response to removing the first portion of Au.
    Type: Application
    Filed: April 28, 2011
    Publication date: November 3, 2011
    Applicant: Medtronic, Inc.
    Inventor: Bruce C. Fleischhauer
  • Patent number: 8042261
    Abstract: A method for fabricating the embedded thin film resistors of a printed circuit board is provided. The embedded thin film resistors are formed using a resistor layer built in the printed circuit board. In comparison with conventional discrete resistors, embedded thin film resistors contribute to a smaller printed circuit board as the space for installing conventional resistors is saved, and better signal transmission speed and quality as the parasitic capacitive reactance effect caused by two contact ends of the conventional resistors is also avoided. The method for fabricating the embedded thin film resistors provided by the invention can be conducted using the process and equipment for conventional printed circuit boards and thereby saving the investment on new types of equipment. The method can be applied in the mass production of printed circuit boards and thereby reduce the manufacturing cost significantly.
    Type: Grant
    Filed: January 20, 2009
    Date of Patent: October 25, 2011
    Inventor: Sung-Ling Su
  • Patent number: 8043974
    Abstract: A semiconductor wet etchant includes deionized water, a fluorine-based compound, an oxidizer and an inorganic salt. A concentration of the fluorine-based compound is 0.25 to 10.0 wt % based on a total weight of the etchant, a concentration of the oxidizer is 0.45 to 3.6 wt % based on a total weight of the etchant, and a concentration of the inorganic salt is 1.0 to 5.0 wt % based on a total weight of the etchant. The inorganic salt comprises at least one of an ammonium ion (NH4+) and a chlorine ion (Cl?).
    Type: Grant
    Filed: July 8, 2008
    Date of Patent: October 25, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Dae Park, Young You, Tae-Hyo Choi, Hun-Jung Yi, Kun-Hyung Lee
  • Patent number: 8029682
    Abstract: According to one embodiment, a method of manufacturing a magnetic recording medium includes forming a first hard mask, a second hard mask and a resist on a magnetic recording layer, imprinting a stamper to the resist to transfer patterns of protrusions and recesses to the resist, removing residues remaining in the recesses of the patterned resist, etching the second hard mask by using the patterned resist as a mask to transfer the patterns of protrusions and recesses to the second hard mask, etching the first hard mask by using the second hard mask as a mask to transfer the patterns of protrusions and recesses to the first hard mask, subjecting the magnetic recording layer exposed in the recesses to modifying treatment to change an etching rate, and deactivating the magnetic recording layer exposed in the recesses.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: October 4, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Isowaki, Kaori Kimura, Yoshiyuki Kamata, Masatoshi Sakurai
  • Publication number: 20110223772
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Application
    Filed: May 26, 2011
    Publication date: September 15, 2011
    Inventors: Steven T. Mayer, Daniel A. Koos, Eric Webb
  • Patent number: 8012361
    Abstract: According to one embodiment, a method of manufacturing a magnetic recording medium includes forming a first hard mask, a second hard mask and a resist on a magnetic recording layer, imprinting a stamper to the resist to transfer patterns of protrusions and recesses to the resist, removing residues remaining in the recesses of the patterned resist, etching the second hard mask by using the patterned resist as a mask to transfer the patterns of protrusions and recesses to the second hard mask, etching the first hard mask by using the second hard mask as a mask to transfer the patterns of protrusions and recesses to the first hard mask, removing the second hard mask remaining on the protrusions of the first hard mask, and deactivating the magnetic recording layer exposed in the recesses by means of ion beam irradiation.
    Type: Grant
    Filed: February 12, 2010
    Date of Patent: September 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kaori Kimura, Yousuke Isowaki, Yoshiyuki Kamata, Masatoshi Sakurai
  • Patent number: 8012883
    Abstract: Methods are provided for manufacturing optical display devices which remove an etch resist and residual post-etch metal in a single step. These methods are particularly useful in the manufacture of LCDs.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: September 6, 2011
    Assignee: Rohm and Haas Electronic Materials LLC
    Inventors: Luis A. Gomez, Jason A. Reese
  • Patent number: 7993536
    Abstract: According to one embodiment, a method of manufacturing a magnetic recording medium includes forming a first hard mask, a second hard mask and a resist film on a magnetic recording layer, imprinting a stamper on the resist film to transfer patterns of recesses and protrusions, removing residues remained in recess of the patterned resist film, etching the second hard mask using the patterned resist film as a mask to transfer patterns of recesses and protrusions, etching the first hard mask using the patterned second hard mask as a mask to transfer patterns of recesses and protrusions, and deactivating magnetism of the magnetic recording layer exposed in the recesses together with removing the second hard mask by ion-beam etching.
    Type: Grant
    Filed: December 11, 2009
    Date of Patent: August 9, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yousuke Isowaki, Kaori Kimura, Yoshiyuki Kamata, Masatoshi Sakurai
  • Patent number: 7988878
    Abstract: The polishing solution is useful for removing a barrier from a semiconductor substrate. The solution contains by weight percent 0.001 to 25 oxidizer, 0.0001 to 5 anionic surfactant, 0 to 15 inhibitor for a nonferrous metal, 0 to 40 abrasive, 0 to 20 complexing agent for the nonferrous metal, 0.01 to 12 barrier removal agent selected from imine derivative compounds, hydrazine derivative compounds and mixtures thereof, and water; and the solution has an acidic pH.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: August 2, 2011
    Assignee: Rohm and Haas Electronic Materials CMP Holdings, Inc.
    Inventor: Jinru Bian
  • Patent number: 7985671
    Abstract: Structures with improved solder bump connections and methods of fabricating such structures are provided herein. The method includes forming an upper wiring layer in a dielectric layer and depositing one or more dielectric layers on the upper wiring layer. The method further includes forming a plurality of discrete trenches in the one or more dielectric layers extending to the upper wiring layer. The method further includes depositing a ball limiting metallurgy or under bump metallurgy in the plurality of discrete trenches to form discrete metal islands in contact with the upper wring layer. A solder bump is formed in electrical connection to the plurality of the discrete metal islands.
    Type: Grant
    Filed: December 29, 2008
    Date of Patent: July 26, 2011
    Assignee: International Business Machines Corporation
    Inventors: Timothy H. Daubenspeck, Jeffrey P. Gambino, Christopher D. Muzzy, Wolfgang Sauter, Timothy D. Sullivan
  • Publication number: 20110174799
    Abstract: A micro-hotplate is provided in the form of a device comprising a sensor and one or more resistive heaters within the micro-hotplate arranged to heat the sensor. Furthermore a controller is provided for applying a bidirectional drive current to at least one of the heaters to reduce electromigration. The controller also serves to drive the heater at a substantially constant temperature. Such an arrangement is advantageous over an arrangement in which a unidirectional DC drive current is applied to the heater. This is because the unidirectional drive current causes electromigration which results in an increase in resistance over time. This is undesirable because it can lead to failure of the micro-hotplate. In contrast, the application of the bidirectional current reduces electromigration and as a result there is insignificant change in the resistance of the heater over time and under high temperature.
    Type: Application
    Filed: January 21, 2010
    Publication date: July 21, 2011
    Inventors: Syed Zeeshan ALI, Florin Udrea, Julian William Gardner
  • Patent number: 7972911
    Abstract: The method for forming first and second metal-based materials comprises providing a substrate comprising an area made from a first semi-conductor material and an area made from a second semi-conductor material comprising germanium separated by a pattern made from dielectric material, depositing a metal layer and performing a first heat treatment in an atmosphere comprising a quantity of oxygen comprised between 0.01% and 5%. The metal layer reacts with the first semi-conductor material and the second semi-conductor material comprising germanium to respectively form the first metal-based material and the second metal-based material containing germanium.
    Type: Grant
    Filed: December 10, 2010
    Date of Patent: July 5, 2011
    Assignee: Commissariat A l'Energie Atomique Et Aux Energies Alternatives
    Inventors: Veronique Carron, Fabrice Nemouchi
  • Patent number: 7972970
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Grant
    Filed: July 30, 2007
    Date of Patent: July 5, 2011
    Assignee: Novellus Systems, Inc.
    Inventors: Steven T. Mayer, Daniel A. Koos, Eric Webb
  • Patent number: 7960289
    Abstract: An etching method is provided in which selective etching can be carried out for an amorphous oxide semiconductor film including at least one of gallium and zinc, and indium. In the etching method, the selective etching is performed using an alkaline etching solution. The alkaline etching solution contains especially ammonia in a specific concentration range.
    Type: Grant
    Filed: November 20, 2007
    Date of Patent: June 14, 2011
    Assignee: Canon Kabushiki Kaisha
    Inventor: Chienliu Chang
  • Patent number: 7955521
    Abstract: Provided are an etchant, a method for fabricating a wire using the etchant, and a method for fabricating a thin film transistor (TFT) substrate using the etchant. The etchant includes a material having the formula 1, ammonium acetic acid, and the remainder of deionized water, wherein the formula 1 is expressed by: M(OH)XLY??(1) where M indicates Zn, Sn, Cr, Al, Ba, Fe, Ti, Si, or B, X indicates 2 or 3, L indicates H2O, NH3, CN, COR, or NH2R, Y indicates 0, 1, 2, or 3, and R indicates an alkyl group.
    Type: Grant
    Filed: February 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-sick Park, Shi-yul Kim, Jong-hyun Choung, Won-suk Shin
  • Patent number: 7927498
    Abstract: A solar cell and a method of texturing a solar cell are disclosed. The method includes coating an ink containing metal particles on a surface of a substrate, drying the ink to attach the metal particles to the surface of the substrate, and differentially etching the surface of the substrate using the metal particles as a catalyst to form an uneven portion.
    Type: Grant
    Filed: February 13, 2009
    Date of Patent: April 19, 2011
    Assignee: LG Electronics Inc.
    Inventors: Younggu Do, Junyong Ahn, Gyeayoung Kwag
  • Patent number: 7927959
    Abstract: A method of patterning a metal (141, 341, 841) on a vertical sidewall (132, 332, 832) of an excavated feature (130, 330, 830) includes placing a material (350) in the excavated feature such that a portion (435) of the metal is exposed in the excavated feature above the material, etching the exposed portion of the metal away from the vertical sidewall using a first wet etch chemistry, and removing the material from the excavated feature by etching it away using a second wet etch chemistry. The described method may be used to produce a MIM capacitor (800) suitable for an eDRAM device.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: April 19, 2011
    Assignee: Intel Corporation
    Inventors: Steven J. Keating, Nick Lindert, Nadia Rahhal-Orabi, Brian Doyle, Satyarth Suri, Swaminathan Sivakumar, Lana Jong, Lin Sha
  • Publication number: 20110081785
    Abstract: The present disclosure relates to a solution for selectively removing metal, such as Ta or TaN, from a substrate, such as an aluminum containing substrate. The solution comprises an acid, such as HF or buffered HF, an ingredient comprising a fluorine ion, such as ammonium fluoride (NH4F), ethylene glycol, and water. A method of selectively removing metal from a substrate using this solution is also disclosed.
    Type: Application
    Filed: December 7, 2010
    Publication date: April 7, 2011
    Inventors: Jeremy W. Epton, John Deem
  • Patent number: 7902081
    Abstract: A method of etching polysilicon includes exposing a substrate comprising polysilicon to a solution comprising water, HF, and at least one of a conductive metal nitride, Pt, and Au under conditions effective to etch polysilicon from the substrate. In one embodiment, a substrate first region comprising polysilicon and a substrate second region comprising at least one of a conductive metal nitride, Pt, and Au is exposed to a solution comprising water and HF. The solution is devoid of any detectable conductive metal nitride, Pt, and Au prior to the exposing. At least some of the at least one are etched into the solution upon the exposing. Then, polysilicon is etched from the first region at a faster rate than any etch rate of the first region polysilicon prior to the etching of the at least some of the conductive metal nitride, Pt, and Au.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: March 8, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Prashant Raghu, Vishwanath Bhat, Niraj Rana
  • Patent number: 7888265
    Abstract: This method for assaying copper in silicon wafers includes the steps of: forming a polysilicon layer on the surface of a p-type silicon wafer having the same characteristics as the silicon wafers being assayed; heat treating the p-type silicon wafer after it has been polished; dissolving the polysilicon layer on the heat-treated p-type silicon wafer with a mixed acid composed of at least hydrofluoric acid and nitric acid; and quantitatively determining the copper components within the mixed acid following dissolution of the polysilicon layer.
    Type: Grant
    Filed: February 20, 2007
    Date of Patent: February 15, 2011
    Assignee: Sumco Corporation
    Inventors: Katsuya Hirano, Mohammad B. Shabani
  • Patent number: 7875558
    Abstract: The present invention is directed to a microetching composition comprising a source of cupric ions, acid, a nitrile compound, and a source of halide ions. Other additive, including organic solvents, a source of molybdenum ions, amines, polyamines, and acrylamides may also be included in the composition of the invention. The present invention is also directed to a method of microetching copper or copper alloy surfaces to increase the adhesion of the copper surface to a polymeric material, comprising the steps of contacting a copper or copper alloy surface with the composition of the invention, and thereafter bonding the polymeric material to the copper or copper alloy surface.
    Type: Grant
    Filed: August 14, 2007
    Date of Patent: January 25, 2011
    Inventors: Kesheng Feng, Nilesh Kapadia, Steven A. Castaldi
  • Patent number: 7850866
    Abstract: An etchant includes hydrogen peroxide (H2O2), and a mixed solution including at least one of an organic acid, an inorganic acid, and a neutral salt.
    Type: Grant
    Filed: July 13, 2004
    Date of Patent: December 14, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Gyoo-Chul Jo, Ki-Sung Chae
  • Publication number: 20100304573
    Abstract: The present invention relates to new storage-stable solutions which can be used in semiconductor technology to effect specific etching of copper metallization layers and also Cu/Ni layers. With the new etch solutions it is possible to carry out etching and patterning of all-copper metallizations, layers of copper/nickel alloys, and also successive copper and nickel layers.
    Type: Application
    Filed: August 7, 2006
    Publication date: December 2, 2010
    Applicant: BASF SE
    Inventors: Martin Fluegge, Raimund Mellies, Thomas Goelzenleuchter, Marianne Schwager, Ruediger Oesten
  • Patent number: 7838483
    Abstract: The invention relates to processes for producing and using amidoxime compounds with low trace metal impurities. The invention further relates to compositions comprising amidoxime compounds with low trace metal impurities, such compositions useful for cleaning or removing residues from semiconductor substrates and/or equipment.
    Type: Grant
    Filed: October 29, 2008
    Date of Patent: November 23, 2010
    Assignee: EKC Technology, Inc.
    Inventors: Wai Mun Lee, Charles C. Y. Chen
  • Publication number: 20100267225
    Abstract: A method of manufacturing a semiconductor device, the method including forming a photoresist film on a substrate, and removing the photoresist film from the substrate using a composition that includes a sulfuric acid solution, a hydrogen peroxide solution, and a corrosion inhibitor.
    Type: Application
    Filed: April 15, 2009
    Publication date: October 21, 2010
    Inventors: Hyo-san Lee, Bo-un Yoon, Kun-tack Lee, Dae-hyuk Kang, Jeong-nam Han, Jung-jae Myung, Hyung-pyo Hong, Hun-pyo Hong
  • Patent number: 7811938
    Abstract: An exemplary method for forming gaps in a micromechanical device includes providing a substrate. A first material layer is deposited over the substrate. A sacrificial layer is deposited over the first material layer. A second material layer is deposited over the sacrificial layer such that at least a portion of the sacrificial layer is exposed. The exposed portion of the sacrificial layer is etched by dry etching. The remaining portion of the sacrificial layer is etched by wet etching to form gaps between the first material layer and the second material layer. One or more bulges are formed at one side of the second material layer facing the first material layer, and are a portion of the sacrificial layer remaining after the wet etching.
    Type: Grant
    Filed: October 9, 2008
    Date of Patent: October 12, 2010
    Assignees: Tsinghua University, Hon Hai Precision Industry Co., Ltd.
    Inventors: Cheng-Rong Yi-Li, Qun-Qing Li, Shou-Shan Fan
  • Patent number: 7795155
    Abstract: An indium cap layer is formed by blanket depositing indium onto a surface of metallic interconnects separated by interlayer dielectric, and then selectively chemically etching the indium located on the interlayer dielectric leaving an indium cap layer. Etchants containing a strong acid are provided for selectively removing the indium.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: September 14, 2010
    Assignee: International Business Machines Corporation
    Inventors: Maurice McGlashan-Powell, Eugene J. O'Sullivan, Daniel C. Edelstein
  • Publication number: 20100184301
    Abstract: Methods for processing a microelectronic topography include selectively etching a layer of the topography using an etch solution which includes a fluid in a supercritical or liquid state. In some embodiments, the etch process may include introducing a fresh composition of the etch solution into a process chamber while simultaneously venting the chamber to inhibit the precipitation of etch byproducts. A rinse solution including the fluid in a supercritical or liquid state may be introduced into the chamber subsequent to the etch process. In some cases, the rinse solution may include one or more polar cosolvents, such as acids, polar alcohols, and/or water mixed with the fluid to help inhibit etch byproduct precipitation. In addition or alternatively, at least one of the etch solution and rinse solution may include a chemistry which is configured to modify dissolved etch byproducts within an ambient of the topography to inhibit etch byproduct precipitation.
    Type: Application
    Filed: January 20, 2009
    Publication date: July 22, 2010
    Applicant: LAM RESEARCH
    Inventors: Mark I. Wagner, James P. DeYoung
  • Publication number: 20100167518
    Abstract: A method for fabricating a CMOS integrated circuit (IC) includes providing a semiconductor including wafer having a topside semiconductor surface, a bevel semiconductor surface, and a backside semiconductor surface. A gate dielectric layer is formed on at least the topside semiconductor surface. A metal including gate electrode material including at least a first metal is deposited on the gate dielectric layer on the topside semiconductor surface and on at least a portion of the bevel semiconductor surface and at least a portion of the backside semiconductor surface. The metal including gate electrode material on the bevel semiconductor surface and the backside semiconductor surface are selectively removed to form substantially first metal free bevel and backside surfaces while protecting the metal gate electrode material on the topside semiconductor surface.
    Type: Application
    Filed: December 26, 2008
    Publication date: July 1, 2010
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventor: BRIAN K. KIRKPATRICK
  • Patent number: 7741230
    Abstract: A highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is described. In one embodiment, the wet etchant is utilized to pattern a metal layer in a semiconductor structure. In another embodiment, a highly selective metal wet etchant with an active ingredient comprising one or more types of molecules having two or more oxygen atoms is used to pattern a metal gate electrode in a replacement gate processing scheme.
    Type: Grant
    Filed: August 8, 2006
    Date of Patent: June 22, 2010
    Assignee: Intel Corporation
    Inventors: Willy Rachmady, Jack T. Kavalieros, Mark Y. Liu, Mark L. Doczy
  • Patent number: 7741203
    Abstract: A method of forming a gate pattern of a flash memory device may include forming a tunnel dielectric layer, a conductive layer for a floating gate, a dielectric layer, a conductive layer for a control gate, a metal electrode layer, and a hard mask film over a semiconductor substrate. The metal electrode layer may be etched such that a positive slope of an upper sidewall may be formed larger than a positive slope of a lower sidewall of the metal electrode layer. The conductive layer for the control gate, the dielectric layer, and the conductive layer for the floating gate may then be etched. High molecular weight argon gas, for example, may be used to improve an anisotropic etch characteristic of plasma. Over etch of a metal electrode layer may be decreased to reduce a bowing profile. Resistance of word lines can be decreased and electrical properties can be improved.
    Type: Grant
    Filed: December 21, 2007
    Date of Patent: June 22, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventor: In No Lee
  • Patent number: 7736956
    Abstract: Embodiments of the invention provide a device with a metal gate, a high-k gate dielectric layer, source/drain extensions a distance beneath the metal gate, and lateral undercuts in the sides of the metal gate.
    Type: Grant
    Filed: March 26, 2008
    Date of Patent: June 15, 2010
    Assignee: Intel Corporation
    Inventors: Suman Datta, Justin K. Brask, Jack Kavalieros, Brian S. Doyle, Gilbert Dewey, Mark L. Doczy, Robert S. Chau
  • Patent number: 7737033
    Abstract: The present embodiments relate to an etchant and a method of fabricating an electric device including a thin film transistor. The etchant includes a fluorine ion (F?) source, hydrogen peroxide (H2O2), a sulfate, a phosphate, an azole-based compound, and a solvent. The etchant and method of fabricating an electric device including a thin film transistor, can etch a multi-layered film including copper layer, and a titanium or titanium alloy layer in a batch and can provide a thin film transistor having a good pattern profile at high yield. When reusing the etchant, uniform etching performance can be maintained with a long replacement period of the etchant, and therefore costs can be saved.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: June 15, 2010
    Assignee: Samsung Mobile Display Co., Ltd.
    Inventors: Gyoo-Chul Jo, Kwang-Nam Kim
  • Patent number: 7732251
    Abstract: One exemplary embodiment includes a semiconductor device. The semiconductor device can include a channel including one or more of a metal oxide including zinc-gallium, cadmium-gallium, cadmium-indium.
    Type: Grant
    Filed: October 11, 2007
    Date of Patent: June 8, 2010
    Assignee: Hewlett-Packard Development Company, L.P.
    Inventors: Randy L. Hoffman, Gregory S. Herman, Peter P. Mardilovich
  • Patent number: 7732284
    Abstract: A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.
    Type: Grant
    Filed: December 26, 2008
    Date of Patent: June 8, 2010
    Assignee: Texas Instruments Incorporated
    Inventors: Brian K. Kirkpatrick, Jinhan Choi, Deborah J. Riley
  • Patent number: 7727901
    Abstract: A method of forming an ink, the ink configured to form a conductive densified film is disclosed. The method includes providing a set of Group IV semiconductor particles, wherein each Group IV semiconductor particle of the set of Group IV semiconductor particles includes a particle surface with a first exposed particle surface area. The method also includes reacting the set of Group IV semiconductor particles to a set of bulky capping agent molecules resulting in a second exposed particle surface area, wherein the second exposed particle surface area is less than the first exposed particle surface area. The method further includes dispersing the set of Group IV semiconductor particles in a vehicle, wherein the ink is formed.
    Type: Grant
    Filed: April 30, 2008
    Date of Patent: June 1, 2010
    Assignee: Innovalight, Inc.
    Inventors: Elena V. Rogojina, Manikandan Jayaraman, Karel Vanheusden
  • Patent number: 7727415
    Abstract: A fine treatment agent according to the present invention is a fine treatment agent for the fine treatment of a multilayer film, including a tungsten film and a silicon oxide film comprising at least one from among hydrogen fluoride, nitric acid, ammonium fluoride and ammonium chloride. Thus, a fine treatment agent which makes fine treatment on a multilayer film, including a tungsten film and a silicon oxide film, possible by controlling the etching rate and a fine treatment method using the same can be provided.
    Type: Grant
    Filed: December 19, 2005
    Date of Patent: June 1, 2010
    Assignee: Stella Chemifa Corporation
    Inventors: Hirohisa Kikuyama, Masahide Waki, Kanenori Ito, Takanobu Kujime, Keiichi Nii, Rui Hasebe, Hitoshi Tsurumaru, Hideki Nakashima
  • Patent number: 7718532
    Abstract: According to the present invention, high-k film can be etched to provide a desired geometry without damaging the silicon underlying material. A silicon oxide film 52 is formed on a silicon substrate 50 by thermal oxidation, and a high dielectric constant insulating film 54 comprising HfSiOx is formed thereon. Thereafter, polycrystalline silicon layer 56 and high dielectric constant insulating film 54 are selectively removed in stages by a dry etching through a mask of the resist layer 58, and subsequently, the residual portion of the high dielectric constant insulating film 54 and the silicon oxide film 52 are selectively removed by wet etching through a mask of polycrystalline silicon layer 56. A liquid mixture of phosphoric acid and sulfuric acid is employed for the etchant solution. The temperature of the etchant solution is preferably equal to or lower than 200 degree C., and more preferably equal to or less than 180 degree C.
    Type: Grant
    Filed: January 31, 2007
    Date of Patent: May 18, 2010
    Assignees: NEC Electronics Corporation, NEC Corporation
    Inventors: Hiroaki Tomimori, Hidemitsu Aoki, Toshiyuki Iwamoto
  • Patent number: 7713388
    Abstract: A structure has at least one structure component formed of a first material residing on a substrate, such that the structure is out of a plane of the substrate. A first coating of a second material then coats the structure. A second coating of a non-oxidizing material coats the structure at a thickness less than a thickness of the second material.
    Type: Grant
    Filed: February 27, 2006
    Date of Patent: May 11, 2010
    Assignee: Palo Alto Research Center Incorporated
    Inventors: Christopher L. Chua, Thomas Hantschel, David K. Fork, Koenraad F. Van Schuylenbergh, Yan Yan Yang
  • Patent number: 7709393
    Abstract: A method for manufacturing a semiconductor device is provided. In particular, a method for removing unwanted material layers from an edge and lower bevel region of a wafer is provided. The method includes performing a first etch of an edge region of a wafer having material layers formed thereon, coating the wafer with a photoresist layer, and patterning the photoresist layer to expose at least the edge and an upper bevel region of the wafer for etching the material layers remaining after performing the first etch.
    Type: Grant
    Filed: December 18, 2006
    Date of Patent: May 4, 2010
    Assignee: Dongbu Electronics Co., Ltd.
    Inventor: In Su Kim
  • Patent number: 7709353
    Abstract: A method for producing a semiconductor device includes the steps of forming a predetermined device in a device layer grown on a semiconductor substrate with a sacrificial layer provided therebetween; and removing the sacrificial layer by etching to separate the semiconductor substrate from the device layer while a supporting substrate is bonded to the side of the device layer, wherein in the step of removing the sacrificial layer, a groove extending from the device layer to the sacrificial layer is formed before the sacrificial layer is removed, and the etching solution is allowed to penetrate to the sacrificial layer through the groove.
    Type: Grant
    Filed: August 16, 2007
    Date of Patent: May 4, 2010
    Assignee: Sony Corporation
    Inventors: Hideki Ono, Satoshi Taniguchi
  • Patent number: 7704767
    Abstract: A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: April 27, 2010
    Assignee: LG Display Co., Ltd.
    Inventors: Oh-Nam Kwon, Kyoung-Mook Lee, Heung-Lyul Cho, Seung-Hee Nam, Cyoo-Chul Jo
  • Publication number: 20100087066
    Abstract: An etching process is employed to selectively pattern an exposed magnetic layer of a magnetic thin film structure. The etching process includes exposing the magnetic layer to an etchant composition including at least one weakly absorbing acid, a surfactant inhibitor soluble in the at least one weakly absorbing acid, and at least one cation additive. The presence of the at least one cation additive increases dissolution inhibition of an underlying tunnel barrier layer (i.e., increases etch selectivity) and permits the use of more soluble surfactant inhibitors in the etchant composition.
    Type: Application
    Filed: October 3, 2008
    Publication date: April 8, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventor: Eugene J. O'Sullivan
  • Publication number: 20100068890
    Abstract: The present invention relates to novel printable etching media having improved properties for use in the process for the production of solar cells. These are corresponding particle-containing compositions by means of which extremely fine lines and structures can be etched very selectively without damaging or attacking adjacent areas.
    Type: Application
    Filed: October 5, 2007
    Publication date: March 18, 2010
    Applicant: MERCK PATENT GESELLSCHAFT
    Inventors: Werner Stockum, Armin Kuebelbeck
  • Patent number: 7662725
    Abstract: A composition for etching a double metal layer, a method of fabricating an array substrate using the composition, and a method of forming a double metal line using the composition are provided. The composition includes about 63.5% to about 64.5% by weight of a phosphoric acid; about 8% to about 9% by weight of a nitric acid; about 8% to about 12% by weight of an acetic acid; and an anionic additive.
    Type: Grant
    Filed: November 28, 2005
    Date of Patent: February 16, 2010
    Assignee: LG Display Co., Ltd.
    Inventor: Oh-Nam Kwon
  • Publication number: 20100035435
    Abstract: The present invention relates to a method for treating copper or copper alloy surfaces for tight bonding to polymeric substrates, for example solder masks found in multilayer printed circuit boards. The substrate generally is a semiconductor-device, a lead frame or a printed circuit board.
    Type: Application
    Filed: October 23, 2006
    Publication date: February 11, 2010
    Applicant: ATOTECH DEUTSCHLAND GMBH
    Inventors: Dirk Tews, Christian Sparing