Electrically Conductive Material (e.g., Metal, Conductive Oxide, Etc.) Patents (Class 438/754)
  • Patent number: 7651896
    Abstract: An object is to provide a method for manufacturing a semiconductor device, in which the number of photolithography steps can be reduced, the manufacturing process can be simplified, and manufacturing can be performed with high yield at low cost.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: January 26, 2010
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tatsuya Honda, Yasuyuki Arai
  • Patent number: 7648920
    Abstract: A method of manufacturing a semiconductor device includes the steps of: forming recesses (a via hole and wiring grooves) in a insulation film; forming a seal layer on inside surfaces of the recesses by using a gas based on a silane having an alkyl group as a precursor; applying EB-cure or UV-cure to the seal layer; and filling up the recesses with a conductor.
    Type: Grant
    Filed: September 20, 2007
    Date of Patent: January 19, 2010
    Assignee: Sony Corporation
    Inventor: Shinichi Arakawa
  • Patent number: 7629265
    Abstract: A novel cleaning method for preventing defects and particles resulting from post tungsten etch back or tungsten chemical mechanical polish is provided. The cleaning method comprises providing a stack structure of a semiconductor device including a tungsten plug in a dielectric layer. The tungsten plug has a top excess portion. A surface of the stack structure is then contacted with a cleaning solution comprising hydrogen peroxide. Next, the surface of the stack structure is contacted with dilute hydrofluoric acid. The cleaning solution and hydrofluoric acid are capable of removing the top excess portion and particles on the surface of the stack structure.
    Type: Grant
    Filed: February 13, 2006
    Date of Patent: December 8, 2009
    Assignee: Macronix International Co., Ltd.
    Inventors: Chia-Wei Wu, Tuung Luoh, Ling-Wuu Yang, Kuang-Chao Chen
  • Patent number: 7625825
    Abstract: A method of making a microelectromechanical system (MEMS) device is disclosed. The method includes forming a stationary layer over a substrate. A sacrificial layer is formed over the stationary layer. The sacrificial layer is formed of a first material. A mechanical layer is formed over the sacrificial layer. A hard mask layer is formed over the mechanical layer. The hard mask layer is formed of a second material. The first and second materials are etchable by a single etchant which is substantially selective for etching the first and second materials relative to the mechanical layer. The hard mask layer is patterned after forming the hard mask layer. Subsequently, the mechanical layer is etched through the patterned hard mask layer. The patterned hard mask layer is removed simultaneously with the sacrificial layer after etching the mechanical layer.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: December 1, 2009
    Assignee: QUALCOMM MEMS Technologies, Inc.
    Inventor: Wen-Sheng Chan
  • Patent number: 7625826
    Abstract: The invention relates to a method of manufacturing a semiconductor device (10) with a substrate (1) and a semiconductor body (11) which comprises at least one semiconductor element, wherein, after formation of the element, a layer structure is formed which comprises at least one electrically insulating layer (2) or an electrically conductive layer (3), wherein an opening is formed in the layer structure with the aid of a patterned photoresist layer (4) and an etching process, wherein residues are formed on the surface of the semiconductor body (11) during the etching process, and wherein the photoresist layer (4) is ashed, after the etching process, by means of a treatment with an oxygen-containing compound, after which the surface is subjected to a cleaning operation using a cleaning agent comprising a diluted solution of an acid in water and being heated to a temperature above room temperature, thereby causing the residues formed to be removed.
    Type: Grant
    Filed: July 8, 2004
    Date of Patent: December 1, 2009
    Assignee: NXP B.V.
    Inventors: Ingrid Annemarie Rink, Reinoldus Bernardus Maria Vroom
  • Patent number: 7624742
    Abstract: Described are methods of removing aluminum fluoride contaminants from aluminum, anodized aluminum, and sprayed ceramic surfaces. Hydrofluoric acid, long known to be effective at removing certain contaminants, has not been used to dissolve aluminum fluoride on aluminum-containing surfaces because the hydrofluoric acid strongly attacks such surfaces, and consequently damages sensitive components. Methods used in accordance with some embodiments remove aluminum fluoride using a mixture of hydrofluoric acid and one or more anhydrous acid. Suitable anhydrous acids include acetic acid.
    Type: Grant
    Filed: February 22, 2006
    Date of Patent: December 1, 2009
    Assignee: Quantum Global Technologies, LLC.
    Inventor: David S. Zuck
  • Publication number: 20090273086
    Abstract: During the patterning of via openings in sophisticated metallization systems of semi-conductor devices, the opening may extend through a conductive cap layer and an appropriate ion bombardment may be established to redistribute material of the underlying metal region to exposed sidewall portions of the conductive cap layer, thereby establishing a protective material. Consequently, in a subsequent wet chemical etch process, the probability for undue material removal of the conductive cap layer may be greatly reduced.
    Type: Application
    Filed: March 4, 2009
    Publication date: November 5, 2009
    Inventors: Christin Bartsch, Daniel Fischer, Matthias Schaller
  • Patent number: 7608547
    Abstract: Provided are an etchant used for a transparent conductive oxide layer and a method for fabricating a liquid crystal display (LCD) using the etchant. The etchant includes 2-5 wt % sulfuric acid, 0.02-10 wt % hydrogen sulfate of alkali metal, and deionized water as the remainder.
    Type: Grant
    Filed: July 13, 2006
    Date of Patent: October 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-sick Park, Shi-yul Kim, Jong-hyun Choung, Won-suk Shin
  • Patent number: 7605091
    Abstract: The present invention provides a method for manufacturing a thin film transistor (TFT) array panel by forming a gate line having a gate electrode on an insulating substrate; sequentially depositing a gate insulating layer and a semiconductor layer on the gate line; forming a drain electrode and a data line having a source electrode on the gate insulating and semiconductor layers; and forming a pixel electrode connected to the drain electrode. These elements can be formed by photo-etching using an etchant containing 65 wt % to 75 wt % of phosphoric acid, 0.5 wt % to 15 wt % of nitric acid, 2 wt % to 15 wt % of acetic acid, 0.1 wt % to 8.0 wt % of a potassium compound, and deionized water. Each element of the TFT array panel can be patterned with the etchant of the invention under similar conditions, which simplifies a manufacturing process and saves costs and results in TFT elements having a good profile.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: October 20, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hong-Sick Park, Sung-Ho Kang, Hong-Je Cho
  • Patent number: 7585698
    Abstract: A thin film transistor has a semiconductor thin film including zinc oxide, a protection film formed on entirely the upper surface of the semiconductor thin film, a gate insulating film formed on the protection film, a gate electrode formed on the gate insulating film above the semiconductor thin film, and a source electrode and drain electrode formed under the semiconductor thin film so as to be electrically connected to the semiconductor thin film.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: September 8, 2009
    Assignee: Casio Computer Co., Ltd.
    Inventor: Hiromitsu Ishii
  • Patent number: 7585782
    Abstract: The invention includes methods of selectively removing metal-containing copper barrier materials (such as tantalum-containing materials, titanium-containing materials and tungsten-containing materials) relative to oxide (such as silicon dioxide) and/or copper. The selective removal can utilize etchant solutions containing hydrofluoric acid and one or more carboxylic acids. The etchant solutions can contain less than 6 weight percent water, and/or can have a dielectric constant below 40.
    Type: Grant
    Filed: April 11, 2006
    Date of Patent: September 8, 2009
    Assignee: Micron Technology, Inc.
    Inventors: Joseph N. Greeley, Paul A. Morgan
  • Publication number: 20090221152
    Abstract: Etching solution for etching a layer system that has at least one layer of aluminum, at least one layer of copper and at least one third layer, selected from nickel vanadium, nickel and alloys thereof, which is arranged between the at least one aluminum layer and the at least one copper layer, wherein the solution contains phosphoric acid, nitric acid, deionized water and at least one salt that can release halogen ions, or comprises these components. The claimed etching solution is the basis for a one-step structuring method of a UBM layer system which is used in the production of components that are produced by semiconductor technology methods.
    Type: Application
    Filed: February 16, 2007
    Publication date: September 3, 2009
    Inventors: Frank Dietz, Klaus Kohlmann-Von Platen, Hans-Joachim Quenzer
  • Patent number: 7582570
    Abstract: A composition and methods for using the composition in removing processing byproducts is provided. The composition can be non-aqueous or semi-aqueous. The non-aqueous composition includes a non-aqueous solvent and one or more components including a fluoride compound and a pyridine compound. The semi-aqueous composition includes glacial acetic acid and one or more components including a fluoride compound and a pyridine compound. The composition can be used in removing processing byproducts from substrate assembly, including MRAM devices, that include at least a metal containing region and processing byproducts, where removing the processing byproducts includes exposing the substrate assembly to the composition for a time effective to remove at least a portion of the processing byproducts.
    Type: Grant
    Filed: December 20, 2005
    Date of Patent: September 1, 2009
    Assignee: Micron Technology, Inc.
    Inventor: Donald L. Yates
  • Publication number: 20090194157
    Abstract: Certain example embodiments of this invention relate to a photovoltaic (PV) device including an electrode such as a front electrode/contact, and a method of making the same. In certain example embodiments, the front electrode has a textured (e.g., etched) surface that faces the photovoltaic semiconductor film of the PV device. In certain example embodiments, the front electrode is formed on a flat or substantially flat (non-textured) surface of a glass substrate (e.g., via sputtering), and the surface of the front electrode is textured (e.g., via etching). In certain example embodiments, a combination of two or more different etchants can be used in order to provide the front electrode with a textured surface having at least two different feature sizes. In completing manufacture of the PV device, the etched surface of the front electrode faces the active semiconductor film of the PV device.
    Type: Application
    Filed: October 2, 2008
    Publication date: August 6, 2009
    Applicant: Guardian Industries Corp.
    Inventors: Willem den Boer, Alexey Krasnov, John A. Vanderploeg
  • Patent number: 7563716
    Abstract: A polishing technique wherein scratches, peeling, dishing and erosion are suppressed, a complex cleaning process and slurry supply/processing equipment are not required, and the cost of consumable items such as slurries and polishing pads is reduced. A metal film formed on an insulating film comprising a groove is polished with a polishing solution containing an oxidizer and a substance which renders oxides water-soluble, but not containing a polishing abrasive.
    Type: Grant
    Filed: March 29, 2007
    Date of Patent: July 21, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Seiichi Kondo, Yoshio Homma, Noriyuki Sakuma, Kenichi Takeda, Kenji Hinode
  • Patent number: 7553341
    Abstract: One embodiment of the present invention provides a process for fabricating an electrode for a capacitor using carbon nanotubes (CNTs), wherein the electrode comprises a metal substrate and a layer of active material (CNTs) coated onto the metal substrate. Specifically, the process starts by dispersing CNTs in a solvent to form a suspension. Next, the CNTs are charged in the suspension. The metal substrate is then immersed in the suspension. Next, the CNTs are deposited onto the metal substrate using electrophoretic deposition (EPD) to form the layer of active material on the metal substrate. In particular, the layer of active material is formed on the metal substrate without using a binder, which effectively reduces contact resistance between the active material and the metal substrate.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: June 30, 2009
    Assignee: The Regents of the University of California
    Inventors: Ning Pan, Chunsheng Du
  • Publication number: 20090149014
    Abstract: At step S101, a TiW film is formed by a sputtering method so as to cover a surface protection film and pad electrodes formed on a surface of a semiconductor element. Subsequently, an Au film is formed on the TiW film. At step S103, Au bumps are formed on the Au film using the Au film as a plating electrode. At step S105, unnecessary parts of the Au film are removed. At step S106, unnecessary parts of the TiW film are removed. At step S107, iodine left in areas where the unnecessary parts of the TiW film have been removed, is removed.
    Type: Application
    Filed: April 7, 2008
    Publication date: June 11, 2009
    Inventors: Norimitsu NIE, Masahiro HORIO, Keiichi SAWAI, Yuji WATANABE, Yasuhiro KOYAMA, Katsuji KAWAKAMI
  • Publication number: 20090146266
    Abstract: A method of fabricating memory devices is provided. First, a charge storage structure including a gate dielectric structure is formed on the substrate in sequence to form a charge trapping layer. Then, a gate conductive layer is formed above the charge storage structure. Afterwards, the gate conductive layer and at least a part of the charge storage structure are patterned. The cross section of the patterned charge storage structure is then become a trapezoid or a trapezoid analogue, which has the shorter side near the gate conductive layer and the longer side near the substrate.
    Type: Application
    Filed: June 16, 2008
    Publication date: June 11, 2009
    Applicant: MACRONIX International Co., Ltd.
    Inventors: Chih-Lin Chen, Kuang-Wen Liu, Hsin-Huei Chen
  • Patent number: 7537943
    Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: May 26, 2009
    Assignee: Renesas Technology Corp.
    Inventors: Akio Hasebe, Yasuhiro Motoyama, Yasunori Narizuka, Seigo Nakamura
  • Publication number: 20090124090
    Abstract: A known method of forming organic semiconductor devices employs the deposition of a conductive polymer onto a substrate to form electrodes or conductive tracks and then to apply an electrical material such as an organic semiconductor on top of these tracks. Although the conductive polymer serves as a highly efficient injector of electrons into the semiconductor, it is not a good conductor. This introduces undesirable inefficient in the supply of current to and from the semiconductor. Worse still the conductivity may deteriorate with time. A solution to this problem has been found by printing the polymer (7) onto a conductive layer (6) carried on a substrate (5). The printed polymer (7) is then used as a resist during a process in which parts of the conductive polymer not protected by the polymer are removed. The resulting device benefits from the good electron injection qualities of the conductive polymer (7) and efficient conduction by virtue of the underlying conductive layer (6).
    Type: Application
    Filed: April 11, 2007
    Publication date: May 14, 2009
    Inventor: Kate Jessie Stone
  • Publication number: 20090124091
    Abstract: The present invention aims to provide an etching solution composition which enables to etch a metal film in a controllable manner, form a desired definite tapered shape, and obtain a smooth surface without causing etching solution exudation trace. Said problems have been solved by the present invention, which is an etching solution composition for etching metal films containing one or more surfactants selected from the group consisting of alkyl sulfate or perfluoroalkenyl phenyl ether sulfonic acid and the salts thereof.
    Type: Application
    Filed: January 12, 2009
    Publication date: May 14, 2009
    Applicants: Kanto Kagaku Kabushiki Kaisha, Sanyo Electric Co., Ltd., Sanyo Semiconductor Manufacturing Co., Ltd.
    Inventors: Kazuhiro Fujikawa, Tsuguhiro Tago
  • Patent number: 7531463
    Abstract: An etching process for selectively etching exposed metal surfaces of a substrate and forming a conductive capping layer over the metal surfaces is described. In some embodiments, the etching process involves oxidation of the exposed metal to form a metal oxide that is subsequently removed from the surface of the substrate. The exposed metal may be oxidized by using solutions containing oxidizing agents such as peroxides or by using oxidizing gases such as those containing oxygen or ozone. The metal oxide produced is then removed using suitable metal oxide etching agents such as glycine. The oxidation and etching may occur in the same solution. In other embodiments, the exposed metal is directly etched without forming a metal oxide. Suitable direct metal etching agents include any number of acidic solutions. The process allows for controlled oxidation and/or etching with reduced pitting.
    Type: Grant
    Filed: October 24, 2006
    Date of Patent: May 12, 2009
    Assignee: Novellus Systems, Inc.
    Inventors: Daniel A. Koos, Steven T. Mayer, Heung L. Park, Timothy Patrick Cleary, Thomas Mountsier
  • Publication number: 20090111277
    Abstract: Methods for stripping a photoresist from a substrate and for fabricating wafer bumps are provided herein. In some embodiments, a method of stripping a photoresist from a substrate includes providing a substrate having a patterned photoresist deposited thereon; and stripping the photoresist from the substrate using a stripping solution comprising ozone in a solvent, wherein the solvent comprises acetic anhydride. In some embodiments, a method of stripping a photoresist from a wafer in a wafer bump formation process includes forming a plurality of wafer bumps on a wafer through a patterned photoresist layer; and stripping the photoresist layer using a stripping solution comprising ozone in a solvent, wherein the solvent comprises acetic anhydride.
    Type: Application
    Filed: October 29, 2007
    Publication date: April 30, 2009
    Applicant: APPLIED MATERIALS, INC.
    Inventor: STEVEN VERHAVERBEKE
  • Patent number: 7524752
    Abstract: In a method of manufacturing a semiconductor device which method is made up of a process of forming a wiring groove using a hard mask, a metal hard mask 107 is used to form a wiring groove 111, allowing the shape of the wiring groove 111 to be stabilized. Furthermore, a part or all of the metal hard mask 107 is removed before the formation of TaN and Cu layers in the wiring groove 111. This enables a reduction in possible damage, which may increase the dielectric constant of the surface of low-dielectric-constant film, and thus in possible inter-wire leakage current. As a result, a reliable semiconductor device can be provided.
    Type: Grant
    Filed: June 10, 2008
    Date of Patent: April 28, 2009
    Assignee: Panasonic Corporation
    Inventor: Makoto Tsutsue
  • Patent number: 7521366
    Abstract: A manufacturing method of an electro line for a liquid crystal display device includes depositing a barrier layer made of a conducting material on a substrate, depositing a copper layer (Cu) on the barrier layer, wet-etching the Cu layer using a first etchant, and dry-etching the barrier layer using a second etchant using the wet-etched Cu layer as an etch mask.
    Type: Grant
    Filed: December 10, 2002
    Date of Patent: April 21, 2009
    Assignee: LG Display Co., Ltd.
    Inventors: Oh-Nam Kwon, Kyoung-Mook Lee, Heung-Lyul Cho, Seung-Hee Nam, Cyoo-Chul Jo
  • Patent number: 7517810
    Abstract: A process for etching a thick aluminum contact layer of a semiconductor wafer comprises the formation of a wet etch photoresist mask and the opening of a window in the mask, followed by a wet etch of a first portion of the thickness of the contact layer exposed by the window and the inherent under cutting of the contact layer under the mask window. A dry etch is next carried out, using the same window as a mask, to cut the remaining web of the contact layer under the window. An etch stop layer of Ti or TiN can be formed within the body of the contact layer to define the depth of the initial wet etch into the contact layer.
    Type: Grant
    Filed: May 26, 2006
    Date of Patent: April 14, 2009
    Assignee: International Rectifier Corporation
    Inventors: David Paul Jones, Hugo R. G. Burke
  • Patent number: 7517811
    Abstract: A method for fabricating a floating gate of the flash memories is described. A pad oxide layer and a silicon nitride layer are formed sequentially on a substrate. A plurality of shallow trenches is formed in the substrate and an active area is defined by the shallow trenches. The silicon nitride layer is pulled back by isotropic etching to expose the corner of the trench. A corner-rounding process is performed to round the corner. An STI structure is formed in the shallow trench. Thereafter, the pad oxide layer and the silicon nitride layer are removed. A tunneling oxide layer and a first polysilicon layer are formed sequentially on the active area and the first polysilicon layer is as high as the STI structure. A second polysilicon layer is formed on the first polysilicon layer and the STI structures. A portion of the second polysilicon layer on the STI structure is removed to form the floating gate.
    Type: Grant
    Filed: April 8, 2003
    Date of Patent: April 14, 2009
    Assignee: Winbond Electronics Corporation
    Inventor: Wen-Kuei Hsieh
  • Publication number: 20090068846
    Abstract: The present invention is directed to compositions for copper passivation and methods of use of such compositions.
    Type: Application
    Filed: September 8, 2008
    Publication date: March 12, 2009
    Inventors: Catherine E. RADZEWICH, David Maloney
  • Publication number: 20090068847
    Abstract: Methods for removing contaminants from a semiconductor device that includes a plurality of aluminum-comprising bond pads on a semiconductor surface of a substrate. A plurality of aluminum-including bond pads are formed on the semiconductor surface of the substrate. A patterned passivation layer is then formed on the semiconductor surface, wherein the patterned passivation layer provides an exposed area for the plurality of bond pads. Wet etching with a basic etch solution is used to etch a surface of the exposed area of the aluminum-including bond pads, wherein the wet etching removes at least 100 Angstroms from the surface of the bond pads to form a cleaned surface.
    Type: Application
    Filed: September 11, 2008
    Publication date: March 12, 2009
    Inventors: Alfred J. Griffin, JR., Lisa A. Fritz, Lin Li, Lee Alan Stringer, Neel A. Bhatt, John Paul Campbell, Stephen Arlon Meisner, Charles Leighton
  • Publication number: 20090042401
    Abstract: Methods for preventing isotropic removal of materials at corners formed by seams, keyholes, and other anomalies in films or other structures include use of etch blockers to cover or coat such corners. This covering or coating prevents exposure of the corners to isotropic etch solutions and cleaning solutions and, thus, higher material removal rates at the corners than at smoother areas of the structure or film from which material is removed. Solutions, including wet etchants and cleaning solutions, that include at least one type of etch blocker are also disclosed, as are systems for preventing higher rates of material removal at corners formed by seams, crevices, or recesses in a film or other structure. Semiconductor device structures in which etch blockers are located so as to prevent isotropic etchants from removing material from corners of seams, crevices, or recesses in a surface of a film or other structure at undesirably high rates are also disclosed.
    Type: Application
    Filed: August 6, 2007
    Publication date: February 12, 2009
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Nishant Sinha, J. Neil Greeley
  • Patent number: 7468105
    Abstract: An antimicrobial cleaning composition and methods for cleaning semiconductor substrates, particularly after chemical mechanical planarization or polishing, are provided. In one embodiment, the cleaning composition combines a solvent, a cleaning agent such as a hydroxycarboxylic acid or salt thereof, and at least one antimicrobial agent resulting in a cleaning composition in which microbial growth is inhibited. Examples of suitable antimicrobial agents include a benzoic acid or salt such as potassium or ammonium benzoate, and sorbic acid or salt such as potassium sorbate. The composition is useful for cleaning a wafer and particularly for removing residual particles after a conductive layer has been planarized to a dielectric layer under the conductive layer in a chemical mechanical planarization of a semiconductor wafer with abrasive slurry particles, particularly after a CMP of copper or aluminum films.
    Type: Grant
    Filed: October 16, 2001
    Date of Patent: December 23, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Michael T. Andreas
  • Patent number: 7468316
    Abstract: A barrier layer is deposited over a layer of passivation including in an opening to a contact pad created in the layer of passivation. A column of three layers of metal is formed overlying the barrier layer and aligned with the contact pad and having a diameter that is about equal to the surface of the contact pad. The three metal layers of the column comprise, in succession when proceeding from the layer that is in contact with the barrier layer, a layer of pillar metal, a layer of under bump metal and a layer of solder metal. The layer of pillar metal is reduced in diameter, the barrier layer is selectively removed from the surface of the layer of passivation after which reflowing of the solder metal completes the solder bump of the invention.
    Type: Grant
    Filed: October 31, 2007
    Date of Patent: December 23, 2008
    Assignee: Megica Corporation
    Inventors: Jin-Yuan Lee, Mou-Shiung Lin, Ching-Cheng Huang
  • Patent number: 7456114
    Abstract: The present invention is directed to a microetching composition comprising a source of cupric ions, acid, a nitrile compound, and a source of halide ions. Other additive, including organic solvents, a source of molybdenum ions, amines, polyamines, and acrylamides may also be included in the composition of the invention. The present invention is also directed to a method of microetching copper or copper alloy surfaces to increase the adhesion of the copper surface to a polymeric material, comprising the steps of contacting a copper or copper alloy surface with the composition of the invention, and thereafter bonding the polymeric material to the copper or copper alloy surface.
    Type: Grant
    Filed: December 21, 2005
    Date of Patent: November 25, 2008
    Inventors: Kesheng Feng, Nilesh Kapadia, Steven A. Castaldi
  • Publication number: 20080280452
    Abstract: Disclosed is a method for stripping a photoresist comprising: (I) providing a photoresist pattern on a substrate where the substrate has at least a copper (Cu) wiring and a low-dielectric layer thereon, and selectively etching the low-dielectric layer by using the photoresist pattern as a mask; (II) contacting the substrate after the step (I), with ozone water and/or aqueous hydrogen peroxide; and (III) contacting the substrate after the step (II), with a photoresist stripping solution that contains at least a quaternary ammonium hydroxide.
    Type: Application
    Filed: July 16, 2008
    Publication date: November 13, 2008
    Inventors: Shigeru Yokoi, Kazumasa Wakiya, Takayuki Haraguchi
  • Patent number: 7439087
    Abstract: A technology for reducing distance between adjacent pixel electrodes to smaller than the limit set by conventional process margin and also preventing adjacent pixel electrodes from being short circuited is provided.
    Type: Grant
    Filed: December 23, 2003
    Date of Patent: October 21, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Akira Ishikawa, Yoshiharu Hirakata
  • Patent number: 7431861
    Abstract: An etchant for copper and copper alloys, includes an aqueous solution containing: 14 to 155 g/liter of cupric ion source in terms of a concentration of copper ions; 7 to 180 g/liter of hydrochloric acid; and 0.1 to 50 g/liter of azole, the azole including nitrogen atoms only as heteroatoms residing in a ring. A method for producing a wiring by etching of copper or copper alloys, includes the step of: etching a portion of a copper layer on an electrical insulative member that is not covered with an etching resist using the above-described etchant so as to form the wiring. Thereby, a fine and dense wiring pattern with reduced undercut can be formed.
    Type: Grant
    Filed: July 22, 2004
    Date of Patent: October 7, 2008
    Assignee: Mec Company Ltd.
    Inventors: Kenji Toda, Yukari Morinaga, Takahiro Teshima, Ai Kuroda
  • Patent number: 7432211
    Abstract: It is an object of the present invention to a method for manufacturing a semiconductor device, by which a reaction product formed when a conductive layer is etched can be removed. A method for manufacturing a semiconductor device according to the present invention includes a step of felling a reaction product adhering to a conductive layer so as to extend in a perpendicular direction so that the thickness of the reaction product with respect to a direction in which an active species excited by plasma discharge is accelerated. It is to be noted that the reaction product is produced when the conductive layer is etched.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: October 7, 2008
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Satoru Okamoto
  • Patent number: 7427569
    Abstract: A metal etching process is described. A substrate having a dielectric layer thereon is provided. An aluminum-copper alloy layer is formed on the dielectric layer. A hard mask layer is formed on the aluminum-copper alloy layer. A patterned photoresist layer is formed on the hard mask layer and then the hard mask layer is patterned. A thermal treatment process is performed. The thermal treatment process is carried out at a temperature of more than 300° C. for a period of at least 3 minutes. Thereafter, the aluminum-copper alloy layer is etched using the patterned hard mask layer as an etching mask. Due to the thermal treatment, the metal precipitate (CuAl2) within the aluminum-copper alloy layer is eliminated and hence the metal etching process is improved.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: September 23, 2008
    Assignee: ProMOS Technologies Inc.
    Inventors: Tza-Hao Wang, Jin-Yang Huang, Hung-Kwei Liao, Ming-Sheng Tung
  • Patent number: 7425278
    Abstract: An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to adjust the pH of the solution to between about 7.8 and about 9.1. The etchant is useful in removing a layer of an alloy of titanium and tungsten or a layer of tungsten from a precision surface.
    Type: Grant
    Filed: November 28, 2006
    Date of Patent: September 16, 2008
    Assignee: International Business Machines Corporation
    Inventors: Krystyna Waleria Semkow, Anurag Jain, Kamalesh K. Srivastava
  • Patent number: 7422696
    Abstract: Multicomponent nanorods having segments with differing electronic and/or chemical properties are disclosed. The nanorods can be tailored with high precision to create controlled gaps within the nanorods or to produce diodes or resistors, based upon the identities of the components-making up the segments of the nanorods. Macrostructural composites of these nanorods also are disclosed.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 9, 2008
    Assignee: Northwestern University
    Inventors: Chad A. Mirkin, Lidong Qin, Sungho Park, Ling Huang, Sung-Wook Chung
  • Patent number: 7413976
    Abstract: The top surfaces of conductive features are treated with a treatment solution before forming a passivation layer over the conductive features. The treatment solution includes a cleaning solution and a chemical grafting precursor. The treatment solution may also include a leveling and wetting agent to improve coverage uniformity of the chemical grafting precursor. The method results in a uniform passivation layer formed over conductive features across a surface of a workpiece.
    Type: Grant
    Filed: February 1, 2005
    Date of Patent: August 19, 2008
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Hsueh Shih, Hung-Wen Su, Minghsing Tsai
  • Patent number: 7402529
    Abstract: A method of fabricating a cladding region for use in MRAM devices includes the formation of a conductive bit line proximate to a magnetoresistive memory device. The conductive bit line is immersed in a first bath containing dissolved ions of a first conductive material for a time sufficient to displacement plate a first barrier layer on the conductive line. The first barrier layer is then immersed in an electroless plating bath to form a flux concentrating layer on the first barrier layer. The flux concentrating layer is immersed in a second bath containing dissolved ions of a second conductive material for a time sufficient to displacement plate a second barrier layer on the flux concentrating layer.
    Type: Grant
    Filed: May 26, 2005
    Date of Patent: July 22, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Jaynal A. Molla, John D'Urso, Kelly Kyler, Bradley N. Engel, Gregory W. Grynkewich, Nicholas D. Rizzo
  • Patent number: 7396708
    Abstract: An etching process of a metal layer of a display panel is provided. First, a substrate with at least one display panel region, a testing device region, and a non-device region is provided. Then, a metal layer is formed over the substrate to cover the display panel region, the testing device region, and the non-device region. Next, a mask is formed on the metal layer to expose a portion of the metal layer. The area of the metal layer exposed by the mask substantially occupies 70%˜88% of the total area of the metal layer. Thereafter, a wet etching process is performed to remove the metal layer exposed by the mask.
    Type: Grant
    Filed: March 23, 2007
    Date of Patent: July 8, 2008
    Assignee: Au Optronics Corporation
    Inventors: Shiun-Chang Jan, Yi Lu, Yi-Ming Shan, Yi-Chun Chen
  • Patent number: 7396773
    Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.
    Type: Grant
    Filed: December 6, 2002
    Date of Patent: July 8, 2008
    Assignee: Cypress Semiconductor Company
    Inventors: Alain Blosse, Krishnaswamy Ramkumar
  • Patent number: 7390754
    Abstract: A method of stripping a remnant metal is disclosed. The remnant metal is formed on a transitional silicide of a silicon substrate. Firstly, a surface oxidation process is performed on the transitional silicide, so as to form a protective layer on the transitional silicide. Then, a HPM stripping process is performed on the silicon substrate in order to strip the remnant metal.
    Type: Grant
    Filed: July 20, 2006
    Date of Patent: June 24, 2008
    Assignee: United Microelectronics Corp.
    Inventors: Chun-Chieh Chang, Tzung-Yu Hung, Chao-Ching Hsieh, Yi-Wei Chen, Yu-Lan Chang
  • Patent number: 7387970
    Abstract: A method for processing semiconductor wafers is disclosed. A semiconductor wafer is provided to a semiconductor processing stage where a block copolymer surfactant (BCS) is applied to the wafer surface. In one embodiment, the BCS includes a hydrophobic portion and a hydrophilic portion. Alternatively, the BCS may be a silicone-containing BCS. In one embodiment, the BCS is within an aqueous solution where the concentration of the BCS within the aqueous solution is less than one percent by weight. Also disclosed is an aqueous solution including abrasive particles and a BCS having a hydrophobic portion and a hydrophilic portion. The abrasive particles may include silica, alumina, or ceria.
    Type: Grant
    Filed: May 7, 2003
    Date of Patent: June 17, 2008
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kevin E. Cooper, John C. Flake, Johannes Groschopf, Yuri E. Solomentsev
  • Patent number: 7384799
    Abstract: A method for forming a MEMS device using an amorphous silicon layer as a release layer includes etching superjacent films and using the amorphous silicon layer as an etch stop layer. The amorphous silicon layer is resistant to attack during the post-etch solvent stripping operation due to the oxidation of exposed portions of the amorphous silicon layer by use of an oxygen plasma.
    Type: Grant
    Filed: January 26, 2005
    Date of Patent: June 10, 2008
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Fei-Yun Chen, Ni-Hwi Kuan, Yuh-Hwa Chang, Yuan-Pang Lee, Yuan-Ko Hwang, Shuh-Shun Chen
  • Publication number: 20080124939
    Abstract: An etchant which includes an aqueous solution of between about 30% and about 38% concentrated hydrogen peroxide, said percentages being by volume, based on the total volume of the solution; between about 3.5 ml and about 20 ml per liter of phosphoric acid; and an amount of potassium hydroxide to adjust the pH of the solution to between about 7.8 and about 9.1. The etchant is useful in removing a layer of an alloy of titanium and tungsten or a layer of tungsten from a precision surface.
    Type: Application
    Filed: November 28, 2006
    Publication date: May 29, 2008
    Applicant: International Business Machines Corporation
    Inventors: Krystyna Waleria Semkow, Anurag Jain, Kamalesh K. Srivastava
  • Publication number: 20080119056
    Abstract: A solution for wet etching a copper film within a ball limiting metallurgy (BLM) of a semiconductor device includes, in an exemplary embodiment, an ammonium persulfate etching agent, a potassium sulfate passivation agent for protecting a PbSn solder material, and a pH modifier for controlling the etch rate of the copper film.
    Type: Application
    Filed: November 16, 2006
    Publication date: May 22, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Carla A. Bailey, Tien-Jen Cheng, Robert Henry, Anurag Jain, Vall F. McLean, Krystyna W. Semkow, Kamalesh K. Srivastava
  • Patent number: 7371333
    Abstract: The invention includes methods of etching nickel silicide and cobalt silicide, and methods of forming conductive lines. In one implementation, a substrate comprising nickel silicide is exposed to a fluid comprising H3PO4 and H2O at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch nickel silicide from the substrate. In one implementation, at least one of nickel silicide or cobalt silicide is exposed to a fluid comprising H2SO4, H2O2, H2O, and HF at a temperature of at least 50° C. and at a pressure from 350 Torr to 1100 Torr effective to etch the at least one of nickel silicide or cobalt silicide from the substrate.
    Type: Grant
    Filed: June 7, 2005
    Date of Patent: May 13, 2008
    Assignee: Micron Technology, Inc.
    Inventor: Prashant Raghu