Abstract: The present invention is to provide a method for fabricating semiconductor devices capable of eliminating a height difference on a base member caused by a residual plating seed layer remained in a portion where an electrode comes into contact and is thus prevented from contacting with an electrolytic polishing fluid, where such height difference has been a problem in introducing the electrolytic polishing process into wafer process. The method comprises the steps of forming a plating seed layer on the base member; forming by the plating process a plated film on the plating seed layer in an area excluding the outer peripheral portion of the base member; polishing the plated film together with the plating seed layer by the electrolytic polishing process; and selectively removing the plating seed layer remaining on the outer peripheral portion of the base member.

Abstract: Methods for removing residuals from the surface of an integrated circuit device. Such methods find particular application in the fabrication of a dual damascene structure following removal of excess portions of a silver-containing metal layer from a device surface. The methods facilitate removal of particulate residuals as well as unremoved portions of the metal layer in a single cleaning process. The cleaning solutions for use with the methods are dilute aqueous solutions containing hydrogen peroxide and at least one acidic component and are substantially free of particulate material. Acidic components include carboxylic acids and their salts.

Abstract: The present invention includes a method of providing a first substrate; forming an insulator over the first substrate; forming an opening in the insulator; forming a conductor over the insulator and in the opening; removing the conductor over the insulator with a first chemical-mechanical polish process to leave the conductor in the opening; and reducing thickness of the insulator with a second chemical-mechanical process to permit the conductor in the opening to protrude. The present invention further includes a structure having such a conductor that protrudes.

Abstract: A method of fabricating a ferroelectric capacitor is disclosed. The method comprises decreasing a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. The method comprises forming an oxygen doped iridium layer and forming a ferroelectric dielectric layer thereover. During the formation of the ferroelectric, the oxygen doped iridium layer converts to an iridium oxide layer.

Abstract: A method of making ink jet printer head body provides a silicon wafer forming a restrictor plate over the silicon wafer by doping an impurity component. A nozzle plate is formed under the silicon wafer by doping an impurity component and a nozzle is formed by etching after the forming of the nozzle plate. A channel going through the restrictor plate and silicon wafer is formed by etching after the forming of the restrictor plate. The channel is formed of a wide upper portion and a narrow lower portion by patterning the silicon wafer and restrictor plate narrowly and etching the silicon wafer and restrictor plate, and then patterning the silicon wafer and restrictor plate widely and etching the silicon wafer and restrictor plate, except for the lower end of the silicon wafer. A restrictor at the restrictor plate is formed by etching after the patternings of the restrictor plate.

Abstract: A chemical mechanical polishing slurry comprising a film forming agent, an oxidizer, a complexing agent and an abrasive, and a method for using the chemical mechanical polishing slurry to remove copper alloy, titanium, and titanium nitride containing layers from a substrate.

Abstract: The present invention relates to a method of fabrication of ZnO nanowires, which uses the sputter deposition technique to form the ZnO nanowires on non-single-crystal the copper metallized substrate.

Abstract: Development efficiency and mass production efficiency of a semiconductor chip (LSI) is improved, whereby the LSI on which an integrated circuit is formed has plural pad parts connecting the integrated circuit with an external circuit. The pad part is provided with a first junction consisting of a window formed in the protective film and the pad exposed from the window, and a second junction consisting of a window formed in the protective film and a bump deposited on the pad exposed from the window. When it is required that the LSI is to be connected with an external circuit by wire bonding, the first junction is connected with the external circuit using a wire. When it is required to connect the LSI with an external circuit by the TAB method or the COG method, the second junction is directly connected to the external circuit.

Abstract: The invention relates to the fabrication of a gate stack or other layered structure in a semiconductor device, and more particularly to methods to selectively etch a metal silicide layer, such as tungsten silicide (WSix), without etching excessive amounts of an underlying polysilicon or gate dielectric layer. The methods of the invention employ an etch chemistry that minimizes or eliminates the formation of lateral growth structures on a metal silicide layer during oxidation steps following etch of a gate stack. A preferred etch composition comprises ammonium fluoride and less than 2% by volume hydrogen peroxide in an aqueous solution with a pH control agent to maintain the solution at about pH 7 to 10.

Abstract: A metal gate structure and method of making the same provides a tracer layer over a first metal or metal compound layer. When etching a metal gate, formed of tungsten, for example, with a first etchant chemistry optimized for etching tungsten, detection of the tracer layer through optical emission spectroscopy, for example, indicates the imminent clearing of the tungsten. A second etchant chemistry is then employed that is selective to the first metal or metal compound layer, such as TiN, overlying the gate dielectric. This provides a controlled etching of the TiN and thereby prevents degradation of the underlying gate dielectric material.

Abstract: A fabricating method of a polycrystalline silicon thin film transistor includes forming a polycrystalline silicon layer on a substrate having first and second regions through a crystallization process using nickel silicide (NiSix) as a catalyst, patterning the polycrystalline silicon layer to form an active layer at the first region, leaving a nickel silicide residue at the second region, etching the nickel silicide residue with a solution including hydrofluoric acid (HF) and hydrogen peroxide (H2O2), forming a gate electrode over the active layer and forming a source and drain in the active layer.

Abstract: Chemical etching methods and associated modules for performing the removal of metal from the edge bevel region of a semiconductor wafer are described. The methods and systems apply liquid etchant in a precise manner at the edge bevel region of the wafer under viscous flow conditions, so that the etchant is applied on to the front edge area and flows over the side edge and onto the back edge in a viscous manner. The etchant thus does not flow or splatter onto the active circuit region of the wafer. An edge bevel removal embodiment involving that is particularly effective at obviating streaking, narrowing the metal taper and allowing for subsequent chemical mechanical polishing, is disclosed.

Abstract: A leadless plastic chip carrier comprising a die attach pad, a semiconductor die mounted to a portion of the die attach pad and at least one row of contact pads circumscribing the die attach pad. The row of contact pads have a thickness greater than the thickness of the portion of the die attach pad. A plurality of wire bonds connect the die attach pad and the contact pads. An overmold covers the semiconductor die and all except one surface of the at least one row of contact pads and the die attach pad.

Abstract: A method of manufacturing a wafer is disclosed. The method includes the steps of: (a) providing a substrate on which a number of semiconductor devices are formed and covered with a passivation layer; (b) exposing a number of contact pads in connection with the semiconductor devices by etching a portion of the passivation layer which are corresponding to the contact pads; and (c) cleaning the contact pads by soaking the substrate into a nitric acid solution and than rinsing. The concentration of the nitric acid solution can be about in the range between 0.01 vol. % and 30 vol. % and preferably about in the range between 1 vol. % and 10 vol. %. Thus, defects on wafers are greatly reduced with causing damages.

Abstract: A process for polishing a semiconductor wafer includes the steps of providing a plurality of wafers, forming a first layer, such as a barrier layer, over at least a portion of each wafer, and forming at least one layer including copper over at least a portion of each first layer. The process also includes the steps of providing a first polishing pad, providing a buffing pad, providing a plurality of operatively connected wafer carriers, and disposing a wafer within each of the wafer carriers. The process further includes the steps of disposing a first slurry composition on the first polishing pad and polishing a first wafer with the first polishing pad for a first length of time, in which the first polishing pad substantially removes the copper layer of the first wafer.

Abstract: A method of forming a semiconductor device that includes cleaning a substrate after forming a tungsten pattern thereon, comprises forming a tungsten layer on a substrate, etching the tungsten layer to form a tungsten pattern, and performing a cleaning process on the substrate having the tungsten pattern using a cleaning solution of a water solution containing 0.1 to 0.4 wt % fluoric acid and 0.5 to 2 wt % hydrogen peroxide. By using the method of the present invention, metal polymers and oxidized slurry residue generated while forming the tungsten pattern may be completely removed without attacking the tungsten pattern.

Abstract: The present invention provides a method of manufacturing a semiconductor device. In one embodiment, the method includes forming a positive relief structure from a material located on a substrate, the step of forming the positive relief structure leaving an unwanted remnant of said material proximate a base of the positive relief structure. The method further includes cleaning the positive relief structure. In addition, the method includes removing the unwanted remnant with a gas containing fluorine and that is substantially free of hydrogen.

Abstract: A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.

Abstract: Methods for the removal of anti-reflective layers during fabrication of integrated circuits are disclosed. In particular, an anti-reflective pattern or layer can be removed using a solution that includes a fluorine containing compound, an oxidant, and water. The fluorine containing compound in the solution can be hydrogen fluorine containing compound. Preferably, the oxidant in the solution is H2O2. The oxidant in the solution can also be ozone water. Related compositions are also disclosed.

Abstract: The present invention provides a method of manufacturing a MOS transistor of an embedded memory. The method of the present invention involves first defining a memory array area and a periphery circuit region on the surface of the semiconductor wafer and to deposit a gate oxide layer, an undoped polysilicon layer and a dielectric layer, respectively. Next, the undoped polysilicon layer in the memory array area is implanted to form a doped polysilicon layer followed by the removal of the dielectric layer in the memory array area. Thereafter, a metallic silicide layer and a passivation layer are formed, respectively, on the surface of the semiconductor wafer. The passivation layer, the metallic silicide layer and the doped polysilicon layer are then etched to form a plurality of gates in the memory array area. Next, the passivation layer, the metallic silicide layer and the dielectric layer in the periphery circuit region are removed.

Abstract: A method for the fabrication of electrical contacts using metal forming, masking, etching, and soldering techniques is presented. The method produces a plurality of specialized electrical contacts, capable of use in an interposer, or other device, including non-permanent or permanent electrical connections providing contact wipe, soft spring rates, durability, and significant amounts of travel.

Abstract: A process (100) for forming a metal interconnect (102) in a semiconductor device (82) using a photoresist layer (20) having a thickness (T) of no more than 0.66 microns without forming a notch in the side (30) of the interconnect. A reactive ion etching process (118) used to remove portions of a metal layer (16) to form the interconnect includes a burst etch step (108) wherein a first high flow rate (48) of passivation gas is delivered, followed by a main metal etch step (110) wherein the flow rate of passivation gas is reduced to a second lower value.

Abstract: A method for preventing or reducing corrosion of copper containing semiconductor features during chemical mechanical polishing (CMP) including providing a semiconductor wafer polishing surface including a copper layer overlying a copper filled anisotropically etched feature; polishing the semiconductor wafer polishing surface according to a first CMP process to remove at least a portion the copper layer to reveal a portion of an underlying barrier/adhesion layer; polishing the semiconductor wafer polishing surface according to a second CMP process including applying a neutralizing solution; polishing the semiconductor wafer polishing surface according to a third CMP process including applying a copper corrosion inhibitor solution; and, polishing the semiconductor wafer polishing surface according to at least a fourth CMP process to remove a remaining portion of the underlying barrier/adhesion layer.

Abstract: method for substantially simultaneously polishing a copper conductive structure of a semiconductor device structure and an adjacent barrier layer. The method includes use of a polishing pad with a slurry solution in which copper and a material, such as tungsten, of the barrier layer are removed at substantially the same rate. The slurry is formulated so as to oxidize copper and a material of the barrier layer at substantially the same rates. Thus, copper and the barrier layer material have substantially the same oxidation energies in the slurry. Systems for substantially polishing copper conductive structures and adjacent barrier structures on semiconductor device structures are also disclosed.

Abstract: An electrically stabilized thin-film high-temperature superconductor includes a superconductive layer (32) applied over a flat metallic substrate (31) and connected to the metallic substrate (31) so that electrical contact between the superconductive layer (32) and the metallic substrate (31) is distributed over the area of the metallic substrate (31).

Abstract: A non-contact apparatus and method for removing a metal layer from a substrate are provided. The apparatus includes a rotatable anode substrate support member configured to support a substrate in a face-up position and to electrically contact the substrate positioned thereon. A pivotally mounted cathode fluid dispensing nozzle assembly positioned above the anode substrate support member is also provided. A power supply in electrical communication with the anode substrate support member and the cathode fluid dispensing nozzle is provided, and a system controller configured to regulate at least one of a rate of rotation of the anode substrate support member, a radial position of the cathode fluid dispensing nozzle, and an output power of the power supply is provided. The method provides for the removal of a metal layer from a substrate by rotating the substrate in a face up position on a rotatable substrate support member.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl−, NO3− and F−. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: The invention includes a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to a mixture having a basic pH and comprising Cl−, NO3− and F−. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: The present invention provides a chemical mechanical polishing composition for planarizing copper and a method for planarizing, or initiating the planarization of, copper using the composition. The chemical mechanical polishing composition includes an oxidizing agent and a copper (II) compound. The composition optionally includes one or more of the following compound types: a complexing agent; a corrosion inhibitor; an acid; and, an abrasive. In one embodiment, the oxidizing agent is hydrogen peroxide, ferric nitrate or an iodate. In another embodiment, the copper (II) compound is CuSO4. The chemical mechanical polishing method involves the step of polishing a copper layer using a composition that includes an oxidizing agent and a copper (II) compound. The composition is formed in a variety of ways. In one embodiment, it is formed by adding the copper (II) compound to a solution containing the oxidizing agent, and any included optional compound types, in deionized water.

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. The mineral acid may be selected from the group including HCl, H2SO4, H3PO4, HNO3, and dilute HF preferably the mineral acid is HCl) and the peroxide may be hydrogen peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one step process or a two step process. In the one step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide.

Abstract: In a method of fabricating a TFT array substrate, a gate wire is formed on an insulating substrate. The gate wire has gate lines, gate electrodes, and gate pads connected to the gate lines. A gate insulating layer and a semiconductor layer are formed in sequence. A data wire is formed, which includes data lines intersecting the gate lines, source electrodes connected to the data lines and placed close to the gate electrodes, drain electrodes opposite the source electrodes with respect to the gate electrodes, and data pads connected to the data lines. A protective layer is deposited, and is patterned to form contact holes exposing at least the drain electrodes. A silver or silver alloy conductive layer is deposited on the protective layer.

Abstract: The invention describes a method for lowering particle count after tungsten etch back, in which method a plasma ashing step is performed after a brush cleaning step to eliminate polymer residues that remain on the metal barrier layer after tungsten etch back. Another tungsten etch back process is further performed to remove a tungsten oxide film that is formed by reacting the tungsten layer with an O2 gas used in the plasma ashing step.

Abstract: Efficient methods are disclosed for fabricating metal plated spring structures in which the metal is plated onto the spring structure after release. A conductive release layer is deposited on a substrate and a spring metal layer is then formed thereon. A first mask is then used to form a spring metal finger, but etching is stopped before the release layer is entirely removed. A second mask is then deposited that defines a release window used to remove a portion of the release layer and release a free end of the spring metal finger. The second mask is also used to plate at least some portions of the free end of the finger and selected structures exposed through the second mask. Remaining portions of the release layer are utilized as electrodes during electroplating. The resulting spring structure includes plated metal on both upper and lower surfaces of the finger.

Abstract: A method for treatment of the surface of a CdZnTe (CZT) crystal that provides a native dielectric coating to reduce surface leakage currents and thereby, improve the resolution of instruments incorporating detectors using CZT crystals. A two step process is disclosed, etching the surface of a CZT crystal with a solution of the conventional bromine/methanol etch treatment, and after attachment of electrical contacts, passivating the CZT crystal surface with a solution of 10 w/o NH4F and 10 w/o H2O2 in water.

Abstract: A method for forming ultra-fine width lines on a substrate avoids occurrence of overetch/underetch defects in the many etching steps, as solder layer or copper film etching steps. With the present method the line shape is able to be achieved close to an ideal shape, so that the quality of the lines is high and the integration of the substrate is also high.

Abstract: Elastomeric stamps facilitate direct patterning of electrical, biological, chemical, and mechanical materials. A thin film of material is deposited on a substrate. The deposited material, either originally present as a liquid or subsequently liquefied, is patterned by embossing at low pressure using an elastomeric stamp having a raised pattern. The patterned liquid is then cured to form a functional layer. The deposition, embossing, and curing steps may be repeated numerous times with the same or different liquids, and in two or three dimensions. The various deposited layers may, for example, have varying electrical characteristics, interacting so as to produce an integrated electronic component.

Abstract: A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.

Abstract: A novel method of Cu seed layer deposition for ULSI metalization is disclosed. The method of Cu seed layer deposition for ULSI metalization comprises forming a diffusion barrier on a substrate, forming a poly silicon layer, amorphous silicon layer or TaSix layer on said diffusion barrier, replacing said poly silicon layer with copper to form a copper seed layer, and electroplating a thick copper film on said copper seed layer. In this invention, a chemical replacing solution comprising a replacing reactant and at least one etchant is used to replace the poly silicon layer with copper and to reduce the quantity of byproducts of the reaction.

Abstract: A nanosyringe is constructed using micro fabrication and nano fabrication techniques on a silicon substrate. The nanosyringe includes a membrane of silicon carbide. The position and operation of individual nanosyringes, arranged in an array of nanosyringes, can be independently controlled. A nanosyringe array can inject or extract a fluid from one or more cells or other structures. Microfluidic structures coupled to the nanosyringe allow external pumping or extraction. A cell matrix or organelles of individual cells can be non-destructively sampled in real time.

Abstract: In order to prevent the contamination of wafers made of a transition metal in a semiconductor mass production process, the mass production method of a semiconductor integrated circuit device of the invention comprises the steps of depositing an Ru film on individual wafers passing through a wafer process, removing the Ru film from outer edge portions of a device side and a back side of individual wafers, on which said Ru film has been deposited, by means of an aqueous solution containing orthoperiodic acid and nitric acid, and subjecting said individual wafers, from which said Ru film has been removed, to a lithographic step, an inspection step or a thermal treating step that is in common use relation with a plurality of wafers belonging to lower layer steps (an initial element formation step and a wiring step prior to the formation of a gate insulating film).

Abstract: Methods for removing titanium-containing layers from a substrate surface where those titanium-containing layers are formed by chemical vapor deposition (CVD) techniques. Titanium-containing layers, such as titanium or titanium nitride, formed by CVD are removed from a substrate surface using a sulfuric acid (H2SO4) solution. The H2SO4 solution permits selective and uniform removal of the titanium-containing layers without detrimentally removing surrounding materials, such as silicon oxides and tungsten. Where the titanium-containing layers are applied to the sidewalls of a hole in the substrate surface and a plug material such as tungsten is used to fill the hole, subsequent spiking of the H2SO4 solution with hydrogen peroxide (H2O2) may be used to recess the titanium-containing layers and the plug material below the substrate surface.

Abstract: A method for etching a surface of an integrated circuit. A layer of photoresist is applied to the surface of the integrated circuit. The layer of photoresist is exposed and developed, and the surface of the integrated circuit is etched with an etchant that contains chlorine. The surface of the integrated circuit is exposed to tetra methyl ammonium hydroxide to neutralize the chlorine, and rinsed with water.

Abstract: The present invention relates to non-selective slurries for chemical-mechanical polishing of a metal layer and a method for manufacturing thereof, and further to a method for forming a plug in an insulating layer on a wafer using such a slurry. More particularly, a slurry is provided for polishing chemically and mechanically simultaneously a metal layer, a barrier layer and an insulating layer used in a semiconductor integrated circuit, which maintains a pH in the range of weak acidity to weak alkalinity by including a first oxidizing agent to reduce a second oxidizing agent, the second oxidizing agent originally being reduced by oxidizing a metal layer. The second oxidizing agent is recycled by recovering the oxidizing power of the first oxidizing agent. An additive increases a polishing rate of the barrier layer and an abrasive is provided to the slurry in an aqueous medium.

Abstract: A method of forming fine patterns of semiconductor devices comprises patterning one material layer using at least two sub-photomasks. The material layer is formed on a semiconductor substrate, and the material layer is patterned at least twice using each of the sub-photomasks. The shapes and sizes of the patterns on one sub-photomask are different to those of the other sub-photomask, and the patterns of one sub-photomask may partially overlap those of the other sub-photomask. The profiles of all patterns formed on the one material layer can thereby be optimized.

Abstract: A leadless plastic chip carrier is constructed by half etching one or both sides of the package design onto a leadframe strip. After wire bonding and molding, a further etching is performed to isolate and expose contact pads. Singulation of individual chip packages from the leadframe strip may then be performed by saw singulation or die punching.

Abstract: A method for integrating a thin film resistor (60) into an interconnect process flow. Metal interconnect lines (40) are formed over a semiconductor body (10). An interlevel dielectric (50) is then formed over the metal interconnect lines (40). Conductively filled vias (62) are then formed through the interlevel dielectric (50) to the metal interconnect lines (40). A thin film resistor (60) is then formed connecting between at least two of the conductively filled vias (62) using a single mask step. Connection to the resistor (60) is from below using a via process sequence already required for connecting between interconnect layers (40, 64). Thus, only one additional mask step is required to incorporate the resistor (60).

Abstract: A multi-layer electronic circuit board design 10 having selectively formed apertures or cavities 26, and which includes grooves or troughs 20, 22 which are effective to selectively entrap liquefied adhesive material, thereby substantially preventing the adhesive material from entering the apertures 26.

Abstract: A method for avoiding erosion of a conductor structure during a procedure of removing etching residues is provided. The method provides a semiconductor structure and the conductor structure formed therein. A cap layer is formed on the conductor structure and the semiconductor and a dielectric layer formed thereon. The dielectric layer and the cap layer are then etched to partially expose the conductor structure. The etching residues are removed with an amine-containing solution and the amine-containing solution is removed with an intermediate solvent to avoid erosion of the exposed conductor structure. As a key step of the present invention, the intermediate solvent comprises N-methylpyrrolidone or isopropyl alcohol and can protect the conductor structure from erosion.

Abstract: Copper can be pattern etched at acceptable rates and with selectivity over adjacent materials using an etch process which utilizes a solely physical process which we have termed “enhanced physical bombardment”. Enhanced physical bombardment requires an increase in ion density and/or an increase in ion energy of ionized species which strike the substrate surface. To assist in the removal of excited copper atoms from the surface being etched, the power to the ion generation source and/or the substrate offset bias source may be pulsed. In addition, when the bombarding ions are supplied from a remote source, the supply of these ions may be pulsed. Further, thermal phoresis may be used by maintaining a substrate temperature which is higher than the temperature of a surface in the etch chamber.

Abstract: A titanium dioxide layer serving as a mask used in a manufacturing process of integrated circuit and its removed method are disclosed. The method includes the steps of forming a titanium dioxide layer on the integrated circuit device to serve as a mask, and using an etchant to selectively remove the titanium dioxide layer. The titanium dioxide layer is formed by the steps of providing a titanium-containing material, adding an acid substance to the titanium-containing material to form a mixture, and exposing the integrated circuit device to the mixture to form the titanium dioxide layer thereon.