Abstract: The present invention is generally directed to various methods of controlling wet chemical processes in forming metal silicide regions, and a system for performing same. In one illustrative embodiment, the method comprises providing a substrate having a layer of unreacted refractory metal and at least one metal silicide region formed thereabove, performing a wet chemical process to remove at least a portion of the layer of unreacted refractory metal, measuring at least one characteristic of the portion of the layer of unreacted refractory metal while the wet chemical process is being performed, and controlling at least one parameter of the wet chemical process based upon the measured at least one characteristic of the portion of the layer of unreacted refractory metal.

Abstract: Method and apparatus are provided for polishing conductive materials with low dishing of features and reduced or minimal remaining residues. In one aspect, a method is provided for processing a substrate by polishing the substrate to remove bulk conductive material and polishing the substrate by a ratio of carrier head rotational speed to platen rotational speed of between about 2:1 and about 3:1 to remove residual conductive material. In another aspect, a method is provided for processing a substrate including polishing the substrate at a first relative linear velocity between about 600 mm/second and about 1900 mm/second at the center of the substrate, and polishing the substrate at a second relative linear velocity between about 100 mm/second and about 550 mm/second at the center of the substrate.

Abstract: A method of forming an array substrate for use in a thin film transistor liquid crystal display (TFT-LCD) device includes forming a first metal layer on a substrate, patterning the first metal layer to form a gate line and a gate electrode extended from the gale line, forming a gate insulation layer on the substrate to cover the patterned first metal layer, forming an active layer on the gate insulation layer and over the gate electrode, forming an ohmic contact layer on the active layer, forming a second metal layer on the gate insulation layer to rover the ohmic contact layer and the active layer, forming a third copper metal layer on the second metal layer, simultaneously patterning the second metal layer and the third copper metal layer to form a double-layered data line, a double-layered source electrode and a double-layered drain electrode using an etchant that includes hydrogen peroxide (H2O2), a H2O2 stabilizer, and a neutral salt, and forming a pixel electrode contacting the double-layered drain elec

Abstract: A method for plating solder is provided. In accordance with the method, a die having a seed metallization thereon is provided. The seed metallization is microetched (85) with a solution comprising an acid and an oxidizer, thereby forming an etched seed metallization. An under bump metallization (UBM) is then electroplated (87) onto the etched seed metallization, and a lead-free solder composition, such as SnCu, is electroplated (91) onto the UBM. A method for reflowing solder is also provided, which may be used in conjunction with the method for plating solder. In accordance with this later method, the substrate is subjected to a seed metallization etch (137), followed by a microetch (141). A solder flux is then dispensed onto the substrate (147) and the solder is reflowed (149).

Abstract: There is provided a method and apparatus for etching a ruthenium film which can sufficiently etch away a ruthenium film formed on or adhering to the peripheral region, especially a no-device-formed region, backside or other portions of a substrate. The method comprises etching a ruthenium film formed on a substrate with a chemical liquid having a pH of not less than 12 and an oxidation-reduction potential of not less than 300 mVvsSHE.

Abstract: A silicon nitride layer having a silicon-rich sub-layer and a standard sub-layer is formed on a copper surface to obtain excellent electromigration characteristics due to the standard sub-layer that is in contact with the copper, while maintaining a superior diffusion barrier behavior due to the silicon-rich sub-layer. By combining these sub-layers, the overall thickness of the silicon nitride layer may be kept small compared to conventional silicon nitride barrier layers, thereby reducing the capacitive coupling of adjacent copper lines.

Abstract: A method for protecting a material of a microstructure comprising said material and a noble metal layer (8) against undesired galvanic etching during manufacture comprises forming on the structure a sacrificial metal layer (12) having a lower redox potential than said material, the sacrificial metal layer (12) being electrically connected to said noble metal layer (8).

Abstract: An etching method for use in integrated circuit fabrication includes providing a metal nitride layer on a substrate assembly, providing regions of cobalt silicide on first portions of the metal nitride layer, and providing regions of cobalt on second portions of the metal nitride layer. The regions of cobalt and the second portions of the metal nitride layer are removed with at least one solution including a mineral acid and a peroxide. Further, the removal of the regions of cobalt and the second portions of the metal nitride layer may include a one-step process or a two-step process. In the one-step process, the regions of cobalt and the second portions of the metal nitride layer are removed with a single solution including the mineral acid and the peroxide. In the two-step process, the regions of cobalt are removed with a first solution containing a mineral acid and a peroxide and the second portions of the metal nitride layer are removed with a second solution containing a peroxide.

Abstract: A cleaning solution selectively removes a titanium nitride layer and a non-reacting metal layer. The cleaning solution includes an acid solution and an oxidation agent with iodine. The cleaning solution also effectively removes a photoresist layer and organic materials. Moreover, the cleaning solution can be employed in tungsten gate electrode technologies that have been spotlighted because of the capability to improve device operation characteristics.

Abstract: The invention relates to a ball-limiting metallurgy (BLM) etching system and process. The BLM stack is provided for an electrical device that contains an aluminum layer disposed upon a metal first layer. A metal upper layer is disposed above the metal second layer, and an alternative metal third layer is disposed between the metal second layer and the metal upper layer. The etching system and process utilizes an etching solution that includes a nitrogen-containing heterocyclic compound, an ammonium hydroxide compound, an oxidizer, and a metal halide compound. Etching conditions prevent any metallization that is dissolved from redepositing, thus avoiding lowered yields.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl−, NO3− and F−. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: Metal nitride and metal oxynitride extrusions often form on metal suicides. These extrusions can cause short circuits and degrade processing yields. The present invention discloses a method of selectively removing such extrusions. In one embodiment, a novel wet etch comprising an oxidizing agent and a chelating agent selectively removes the extrusions from a wordline in a memory array. In another embodiment, the wet etch includes a base that adjusts the pH of the etch to selectively remove certain extrusions relative to other substances in the wordline. Accordingly, new metal silicide structures can be used to form novel wordlines and other types of integrated circuits.

Abstract: A thermoelectric device with improved efficiency is provided. In one embodiment, the thermoelectric device includes a first thermoelement and a second thermoelement electrically coupled to the first thermoelement. An array of first tips are in close physical proximity to, but not necessarily in physical contact with, the first thermoelement at a first set of discrete points. An array of second tips are in close physical proximity to, but not necessarily in physical contact with, the second thermoelement at a second set of discrete points. The first and second conical are constructed entirely from metal, thus reducing parasitic resistances.

Abstract: A method for reducing the surface roughness of a metal layer is provided. In some embodiments, the method may include polishing the metal layer to a level substantially above any layers arranged directly beneath the metal layer. In some cases, the semiconductor topography comprising the metal layer may be substantially absent of any material laterally adjacent to the metal layer during polishing. In either case, a semiconductor topography having a metal layer with a mean surface roughness less than the mean surface roughness obtained during the deposition of the metal layer may be obtained. As such, the method may include reducing the mean surface roughness of a metal layer. For example, the method may include reducing the mean surface roughness of a metal layer by at least a factor of ten.

Abstract: A process for selectively removing a conductive layer from a wafer that includes sub-micron sized noble metal interconnect features is disclosed. The wafer having sub-micron sized noble metal interconnect features and a conductive film to be removed is placed into an electrolyte solution. Also immersed in the electrolyte solution are a counter electrode, a reference electrode, and a working electrode. The wafer is coupled to the working electrode terminal on a potentiostat. The counter electrode is connected to the counter electrode terminal on a potentiostat, and the reference electrode is connected to a reference electrode terminal on the potentiostat. The potentiostat adjusts the electrical current flowing between the wafer and the counter electrode to maintain a constant voltage between the wafer and the reference electrode as the conductive layer is removed.

Abstract: A method for forming atomic-scale contacts and atomic-scale gaps between two electrodes is disclosed. The method provides for applying a voltage between two electrodes in a circuit with a resistor. The applied voltage etches metal ions off one electrode and deposits the metal ions onto the second electrode. The metal ions are deposited on the sharpest point of the second electrode, causing the second electrode to grow towards the first electrode until an atomic-scale contact is formed. By increasing the magnitude of the resistor, the etching and deposition process will terminate prior to contact, forming an atomic-scale gap. The atomic-scale contacts and gaps formed according to this method are useful as a variety of nanosensors including chemical sensors, biosensors, hydrogen ion sensors, heavy metal ion sensors, magnetoresistive sensors, and molecular switches.

Abstract: Priorly, semiconductor devices wherein a flexible sheet with a conductive pattern was employed as a supporting substrate, a semiconductor element was mounted thereon, and the ensemble was molded have been developed. In this case, problems occur that a multilayer wiring structure cannot be formed and warping of the insulating resin sheet in the manufacturing process is prominent. In order to solve these problems, a laminated plate 10 in which a thin first conductive film 11 and a thick second conductive film 12 have been laminated via a third conductive film 13 is used.

Abstract: A method to redistribute solid copper deposited by PVD on a wafer topography. The deposited copper is solubilized in a fluid for redistribution. The copper redistribution prevents inherent nonuniformity of the deposited copper film thickness by improving the uniformity of thickness of the copper film on the covered surfaces, such as vertical and bottom surfaces. The method provides the advantages of good adhesion and good grain growth and orientation that are achieved with copper deposited by PVD, and also provides the good step coverage as achieved with copper deposited by CVD.

Abstract: A first oxide film and a second oxide film 16 are formed in a first region 13a and a second region 13b, respectively, on the surface of the semiconductor substrate 10, via thermal oxidization method, and the first oxide film is removed while the second oxide film 16 is covered with the resist layer 18 formed thereon, and then the resist layer 18 is removed with a chemical solution containing an organic solvent such as isopropyl alcohol as a main component. Subsequently, a third oxide film 22 having different thickness than the second oxide film 16 is formed in the first region 13a.

Abstract: A method for the fabrication of a gate stack, in particular in very large scale integrated semiconductor memories, uses a combination of a damascene process and a CMP process to produce a gate stack which includes a polysilicon section, a silicide section and a covering-layer section thereabove. The gate stack can be fabricated by using conventional materials, has a very low sheet resistance of <1 ohm/unit area and may carry self-aligning contact sections.

Abstract: A embedded resistor printed circuit board fabrication includes the steps of preparing a substrate having a top conductive layer and a bottom insulating layer and etching the top conductive layer to form a first conductive layer having recesses in it; embedding resistive material in the recesses, enabling the first conductive layer to be electrically connected to lateral sides of the resistive material; plating a thin conductive film on the first conductive layer and the resistive material to form a second conductive layer; and etching the first conductive layer and second conductive layer to let the second conductive layer be electrically connected to the thin film type resistors.

Abstract: The present invention relates to a method for fabricating semiconductor capacitors, which enables the capacitance of the capacitors to be increased.

Abstract: In one embodiment, a testing regimen is implemented to reduce test time. Specifically, a structure and method to power up and stabilize all die on the wafer prior to testing each die is implemented. More specifically, parallel powering schemes including die stabilization procedures are used to ready the wafer for testing. A wafer probe tester is indexed from one die to the next for an uninterrupted testing of all die in the wafer subsequent to all die power up and stabilization.

Abstract: Provided is a method for fabricating a capacitor using an electrochemical deposition method and Ce(NH4)2(NO3)6 solution. The method includes the steps of: a) forming a contact hole in an insulation layer on a substrate; b) forming a plug including nitride in the contact hole; c) forming a Ru seed layer in the contact hole and on the insulation layer; d) forming a sacrificial layer including an open area overlapped with the contact hole on the Ru seed layer; e) forming a Ru layer for an electrode of the capacitor in the open area by performing electrochemical deposition; f) removing the sacrificial layer, whereby the Ru seed layer not covered with the Ru layer is exposed; and g) etching the exposed Ru seed layer by using an aqueous solution including Ce(NH4)2(NO3)6.

Abstract: A gradational etching method for high density wafer production. The gradational etching method acts on a substrate having a first passivation layer and a second passivation layer on a top surface and a bottom surface, respectively, of the substrate. A first etching process is performed to simultaneously etch the substrate and the first passivation layer to remove the first passivation layer. Finally, a second etching process is performed to etch the substrate to a designated depth that is used to control the thickness of the wafer after the second etching process.

Abstract: A semiconductor device, which uses a crystalline silicon film having high crystallinity and a flat surface with few ridges and has high characteristics, and a method of manufacturing the semiconductor device are provided. According to the manufacturing method, a first amorphous silicon film is crystallized by using a heat treatment. A second amorphous silicon film is formed on a first crystalline silicon film thus obtained as an under film, and the second amorphous silicon film is crystallized by irradiation of laser light, so that a silicon film having excellent crystallinity and a surface with few ridges is obtained. The first crystalline silicon film and the second crystalline silicon film having different crystal structures are used as an active layer of a thin film transistor.

Abstract: A method for manufacturing a semiconductor device includes a step of forming a first groove in a first insulating film, forming a conductive film in the first groove, a step of selectively forming a second insulating film on the conductive film and the first insulating film, a step of forming a second groove by removing part of the conductive film using the second insulating film as a mask, the second groove being formed so as to form a connecting portion of the conductive film under the second insulating film and form a first wiring layer by forming the connecting portion with a bottom of the first groove integrally with each other as one unit.

Abstract: Elastomeric stamps facilitate direct patterning of electrical, biological, chemical, and mechanical materials. A thin film of material is deposited on a substrate. The deposited material, either originally present as a liquid or subsequently liquefied, is patterned by embossing at low pressure using an elastomeric stamp having a raised pattern. The patterned liquid is then cured to form a functional layer. The deposition, embossing, and curing steps may be repeated numerous times with the same or different liquids, and in two or three dimensions. The various deposited layers may, for example, have varying electrical characteristics, interacting so as to produce an integrated electronic component.

Abstract: An electronic device having a component containing a refractory metal such as tungsten is cleaned by using a cleaning solution composed of an acidic solution which does not substantially contain aqueous hydrogen peroxide or an alkaline solution which does not substantially contain aqueous hydrogen peroxide.

Abstract: The present invention relates to a method of forming a damascene gate electrode of highly integrated MOS transistor capable of easily removing a dummy polysilicon layer. The disclosed comprises the steps of forming a dummy gate insulating layer and a polysilicon layer for a dummy gate on a wafer; forming an interlayer insulating layer on the wafer; polishing the interlayer insulating layer to expose a top surface of the dummy polysilicon layer; and wet etching the exposed dummy polysilicon layer using a spin etching process.

Abstract: A process for removing at least one thin-film layer from a surface of a workpiece pursuant to manufacturing a microelectronic interconnect or component is set forth. Generally stated, the process comprises the oxidation of at least a portion of the at least one thin-film layer and the etching of the oxidized thin-film layer using an etchant that selectively etches primarily the oxidized thin-film layer.

Abstract: A semiconductor device production method that is used to uniformly and efficiently reduce metal oxides produced on metal (copper, for example) which forms electrodes or wirings on a semiconductor device. An object to be treated on which copper oxides are produced is put into a process chamber and is heated by a heater to a predetermined temperature. Then carboxylic acid stored in a storage tank is vaporized by a carburetor. The vaporized carboxylic acid, together with carrier gas, is introduced into the process chamber via a treating gas feed pipe to reduce the copper oxides produced on the object to be treated to metal copper. As a result, metal oxides can be reduced uniformly without making the surfaces of electrodes or wirings irregular. Moreover, in this case, carbon dioxide and water are both produced in a gaseous state. This prevents impurities from remaining on the surface of copper.

Abstract: The method for forming an isolation film in a semiconductor device includes the steps of providing a semiconductor substrate having at least a first insulation film formed thereon, and forming a trench in the first insulation film and the semiconductor substrate. Next, an insulation film pattern is formed. The insulation film pattern fills the trench and extends from the trench over a portion of the first insulation film. Afterwards, the first insulation film is etched. The etching of the first insulation film also results in etching of the insulation film pattern, but the insulation film pattern at the upper side wall edges of the trench is not etched.

Abstract: A scanning probe microscope probe is formed by depositing probe material in a mold that has a cavity in a shape and of a size of the desired form of the scanning probe microscope probe that is being fabricated. In the preferred embodiment, the cavity is formed by lithographically defining, in the body of the mold, the shape and the size of the desired scanning probe microscope probe and etching the body of the mold to form the cavity. Prior to depositing the probe material in the cavity in the mold, the cavity is lined with a release layer which, upon activation after the probe has been formed, permits removal of the probe.

Abstract: A method for removal of metallic residue from a substrate after a plasma etch process in a semiconductor substrate processing system by cleaning the substrate in a hydrogen fluoride solution.

Abstract: The invention encompasses a semiconductor processing method of cleaning a surface of a copper-containing material by exposing the surface to an acidic mixture comprising Cl+, NO3+ and F+. The invention also includes a semiconductor processing method of forming an opening to a copper-containing substrate. Initially, a mass is formed over the copper-containing substrate. The mass comprises at least one of a silicon nitride and a silicon oxide. An opening is etched through the mass and to the copper-containing substrate. A surface of the copper-containing substrate defines a base of the opening, and is referred to as a base surface. The base surface of the copper-containing substrate is at least partially covered by at least one of a copper oxide, a silicon oxide or a copper fluoride.

Abstract: An integrated semiconductor substrate bevel cleaning system that enables transfer of substrates through the bevel cleaner either with or without substrate processing within the bevel cleaner. The invention provides an integrated bevel cleaning apparatus comprising a transfer position, a rinsing position and an etching position.

Abstract: A method and an apparatus for removing coating layers from the top of alignment marks on a wafer situated in a spin processor are described. The method may be carried out by first providing a spin process equipped with a rotatable wafer pedestal, then providing a wafer that has at least one alignment mark covered by a coating layer, mounting an edge ring on an outer periphery of the wafer pedestal, the edge ring has at least one tab section extending outwardly from an inner periphery of the edge ring, then positioning the wafer faced down and supported by an inert gas flow on the edge ring such that a narrow gap is formed between the tab section on the edge ring and the alignment marks and dispensing an etchant onto a backside of the wafer while rotating.

Abstract: Tungsten plugs are prevented from corrosion, during fabrication of semiconductor devices, where the tungsten plug is formed in a substrate and coupled with a wire formed on the substrate. The substrate is dipped into a non-ionic benign solvent which substantially discharges the charges accumulated on a surface of the wire, followed by a rinsing process to clean the surface of the wire and then spin-drying.

Abstract: A method of forming a top-metal fuse structure comprising the following steps. A structure having an intermetal dielectric layer is formed thereover, the structure including a fuse region and an RDL/bump/bonding pad region. A composite metal layer is formed over the intermetal dielectric layer. The composite metal layer including a second metal layer sandwiched between upper and lower first metal layers. The upper first metal layer is patterned to form an upper metal layer portion within the RDL/bump/bonding pad region. The second metal layer and the lower first metal layer are patterned: (1) within the RDL/bump/bonding pad region to form an RDL/bump/bonding pad; the RDL/bump/bonding pad having a patterned second metal layer portion/lower first metal portion with a width greater than that of the upper metal layer portion and forming a step profile; and (2) within the fuse region to form the top-metal fuse structure. The RDL/bump/bonding pad structure includes a step profile.

Abstract: Nanotube films and articles and methods of making the same are disclosed. A conductive article includes an aggregate of nanotube segments in which the nanotube segments contact other nanotube segments to define a plurality of conductive pathways along the article. The nanotube segments may be single walled carbon nanotubes, or multi-walled carbon nanotubes. The various segments may have different lengths and may include segments having a length shorter than the length of the article. The articles so formed may be disposed on substrates, and may form an electrical network of nanotubes within the article itself. Conductive articles may be made on a substrate by forming a nanotube fabric on the substrate, and defining a pattern within the fabric in which the pattern corresponds to the conductive article.

Abstract: Washing a microelectronic substrate with an ozonated solution following planarization and proceeding removal of a native oxide layer through acid etching.

Abstract: In integrated circuits produced by etching and damascene techniques, it is common for cracking to occur in dielectric material surrounding an interconnect metal layer integrated into the device, presumably as a result of the transfer of stresses from the interconnect metal layer to the surrounding dielectric material. The present invention addresses this problem by providing an interconnect metal layer that comprises rounded comers which are believed to reduce the stresses transferred to a surrounding dielectric layer.

Abstract: A method of manufacturing a semiconductor device, comprising the following processes of forming a structure in which a barrier metal containing at least of Ti and Ta and a copper wiring are exposed on its surface, or a structure in which at least one substance selected from the group consisting of Ti, W, and Cu and Al are exposed on its surface, above a semiconductor substrate, and supplying a hydrogen-dissolved solution dissolving hydrogen gas to the surface of the structure.

Abstract: A solution and method is described for etching TaN, TiN, Cu, FSG, TEOS, and SiN on a silicon substrate in silicon device processing. The solution is formed by combining HF at 49% concentration with H2O2 at 29%-30% concentration in deionized water.

Abstract: An etchant for patterning indium tin oxide, wherein the etchant is a mixed solution of HCl, CH3COOH, and water, and a method of fabricating a liquid crystal display device are disclosed in the present invention. The method includes forming a gate electrode on a substrate, forming a gate insulating layer and an amorphous silicon layer on the gate electrode including the substrate, forming an active area by patterning the amorphous silicon layer, forming a source electrode and a drain electrode on the active area, forming a passivation layer on the source electrode and the drain electrode and the gate insulating layer, forming a contact hole exposing a part of the drain electrode, forming an indium tin oxide layer on the passivation layer, and forming an indium tin oxide electrode by selectively etching the indium tin oxide layer using a mixed solution of HCl, CH3COOH, and water as an etchant.

Abstract: A method of forming metal fuses and bonding pads. A conductive layer is formed in a substrate. A dielectric layer is formed over the substrate. The dielectric layer has an opening that exposes a portion of the conductive layer. A metallic layer is formed over the dielectric layer. The metallic layer is patterned to form a metal fuse and a bonding pad. The bonding pad is electrically connected to the conductive layer via the opening. Both the metal fuse and the bonding pad have undercut sidewalls. Spacers are formed on the undercut sidewalls of the metal fuse and the bonding pad. Finally, a passivation layer that exposes the metal fuse and the bonding pad is formed over the substrate.

Abstract: A process and apparatus for locally removing any material, such as a refractory metal, in particular tungsten, from any desired area of a wafer, such as an alignment mark area of a silicon wafer in process during the formation of integrated circuits thereon.

Abstract: A method for removing contamination on a semiconductor substrate is disclosed. The contamination contains at least one element belonging to one of 3A group, 3B group and 4A group of long-period form of periodic system of elements. The method comprises first and second process steps. The first process is wet processing the semiconductor substrate by first remover liquid that contains one of acid and alkali. The second process is wet processing the semiconductor substrate by second remover liquid that contains oxidizing reagent and one of hydrofluoric acid and salt of hydrofluoric acid.

Abstract: A method and apparatus for analyzing a semiconductor surface obtains a sample from a localized section of a wafer. The sample is obtained by isolating a section of a wafer with a sampling apparatus, dispensing liquid onto the isolated section of the wafer, dissolving compounds of interest in the liquid, removing a portion of the liquid, and analyzing the liquid and dissolved compounds of interest. The liquid can be an etching solution, an organic solvent, or other suitable solvent. Samples and analyses can, thus, be obtained as a function of position on the wafer. Analyses as a function of depth can also be determined by sampling and analyzing an isolated portion of the wafer as a function of time.