Oxidation Patents (Class 438/770)
  • Patent number: 10409260
    Abstract: To provide an abnormality detection system capable of reducing work load of an engineer. An algorithm storage unit stores therein a detection algorithm corresponding to identification information of a detection target. An abnormality detection unit detects an abnormality in a detection target signal obtained from a monitor signal of the detection target using a corresponding detection algorithm in the algorithm storage unit. A detection target identification unit determines whether the detection algorithm corresponding to the identification information of the detection target is stored in the algorithm storage unit, and issues a generation request when it is not stored therein. An algorithm generation unit generates the detection algorithm using a corresponding detection target signal according to the generation request.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: September 10, 2019
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Masatoshi Kawatake
  • Patent number: 10062577
    Abstract: A method of fabricating III-V fin structures includes providing numerous fins. Then, a group III-V material layer is formed to encapsulate an upper portion of each of the fins. Later, part of the group III-V material layer is removed to expose an end of each of the fins, and divides the group III-V material layer into numerous U-shaped structures. Next, a first part of each of the fins and the entire silicon oxide layer are removed. Finally, part of each of the U-shaped structures is removed to segment each of the U-shaped structures into two III-V fin structures.
    Type: Grant
    Filed: July 11, 2017
    Date of Patent: August 28, 2018
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventor: Ching-Wen Hung
  • Patent number: 9972517
    Abstract: According to one embodiment, there is provided an anomaly detection system for a second unit incidental to a first unit that processes a substrate. The anomaly detection system includes a collecting unit, a first calculating unit, a second calculating unit, and a determining unit. The collecting unit is configured to collect a plurality of types of parameters related to a state of the second unit. The first calculating unit is configured to calculate a divergence of a coordinate point from a reference space in a virtual coordinate space of a plurality of types of parameters, the coordinate point being indicated by the plurality of types of collected parameters. The second calculating unit is configured to accumulate the calculated divergence and calculate a cumulative divergence. The determining unit is configured to compare the calculated cumulative divergence with a threshold value and determine an anomaly in the second unit.
    Type: Grant
    Filed: March 12, 2015
    Date of Patent: May 15, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Tsutomu Miki
  • Patent number: 9735006
    Abstract: A method of manufacturing a semiconductor device is disclosed. The method includes forming a thin film containing a predetermined element, boron, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times. The cycle includes forming a first layer containing boron and a halogen group by supplying a first precursor gas containing boron and the halogen group to the substrate; and forming a second layer containing the predetermined element, boron, carbon, and nitrogen by supplying a second precursor gas containing the predetermined element and an amino group to the substrate and modifying the first layer.
    Type: Grant
    Filed: July 6, 2015
    Date of Patent: August 15, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Atsushi Sano, Yoshiro Hirose
  • Patent number: 9587314
    Abstract: Provided is a substrate processing apparatus including a substrate processing chamber configured to process a substrate; a gas supply unit configured to alternately supply a first processing gas and a second processing gas to the substrate when processing the substrate; a substrate support unit including a support mechanism configured to support a portion of a back side of the substrate and a support unit configured to support the support mechanism; a heating unit configured to heat the substrate from the back side thereof; a standby chamber configured to accommodate the substrate support unit in standby position; and a control unit configured to control at least one of the gas supply unit and a gas exhaust unit in a manner that an inner pressure of the substrate processing chamber is higher than that of the standby chamber.
    Type: Grant
    Filed: November 24, 2014
    Date of Patent: March 7, 2017
    Assignee: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Taketoshi Sato, Hiroaki Hiramatsu, Yukitomo Hirochi
  • Patent number: 9589785
    Abstract: The present disclosure provides one embodiment of a method. The method includes applying a first cleaning fluid to a substrate, thereby cleaning the substrate and forming a protection layer on the substrate; and applying a removing process to the substrate, thereby removing the protection layer from the substrate. The first cleaning fluid includes a cleaning chemical, a protection additive and a solvent.
    Type: Grant
    Filed: August 28, 2014
    Date of Patent: March 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ya-Ling Cheng, Chien-Wei Wang
  • Patent number: 9552981
    Abstract: A metal oxide film forming method includes: repeating a cycle a first predetermined number of times, the cycle including supplying a gas containing an organic metal precursor into a processing chamber where an object to be processed is accommodated, and supplying oxygen gas into the processing chamber after the gas containing the organic metal precursor is supplied into the processing chamber; and supplying ozone gas into the processing chamber, wherein repeating the cycle and supplying the ozone gas are repeated a second predetermined number of times, so that a metal oxide film is formed on a surface of the object to be processed.
    Type: Grant
    Filed: February 4, 2015
    Date of Patent: January 24, 2017
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Kazuo Yabe, Jun Ogawa
  • Patent number: 9553160
    Abstract: Embodiments of mechanisms of monitoring metal impurity in a high-k dielectric film are provided. The method includes forming an interfacial layer over a substrate. The method also includes forming a high-k dielectric film on the interfacial layer, and the interfacial layer and the high-k dielectric film form a stacked structure over the substrate. The method further includes conducting the first thickness measurement on the stacked structure. In addition, the method includes performing a treatment to the stacked structure after the first thickness measurement, and the treatment includes an annealing process. The method also includes conducting the second thickness measurement on the stacked structure after the treatment.
    Type: Grant
    Filed: October 9, 2013
    Date of Patent: January 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Wei-Jen Chen, Yen-Yu Chen, Chang-Sheng Lee, Wei Zhang
  • Patent number: 9514960
    Abstract: This disclosure relates to a method for dissolving a silicon dioxide layer in a structure, including, from the back surface thereof to the front surface thereof, a supporting substrate, the silicon dioxide layer and a semiconductor layer, the dissolution method being implemented in a furnace in which structures are supported on a support, the dissolution method resulting in the diffusion of oxygen atoms included in the silicon dioxide layer through the semiconductor layer and generating volatile products, and the furnace including traps suitable for reacting with the volatile products, so as to reduce the concentration gradient of the volatile products parallel to the front surface of at least one structure.
    Type: Grant
    Filed: March 3, 2014
    Date of Patent: December 6, 2016
    Assignee: Soited
    Inventors: Didier Landru, Oleg Kononchuk
  • Patent number: 9508571
    Abstract: A method for cleaning a base for supporting an object to process in an apparatus configured to perform a heat process, the method comprising a first step of forming an oxide film on the base including silicon carbide, by subjecting the base to a heat process in a gas atmosphere including oxygen, and a second step of, after the first step, subjecting the base to a heat process in a gas atmosphere including steam, wherein the first step is performed for 10 hours at a temperature of 1000° C. or more.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: November 29, 2016
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Toshiyuki Ogawa, Nobutaka Ukigaya
  • Patent number: 9412603
    Abstract: Embodiments described herein generally relate to methods of forming sub-10 nm node FinFETs. Various processing steps are performed on a substrate to provide a trench defining a mandrel structure. Sidewalls of the mandrel structure and a bottom surface of the trench are oxidized and subsequently etched to reduce a width of the mandrel structure. The oxidation and etching of the mandrel structure may be repeated until a desired width of the mandrel structure is achieved. A semiconducting material is subsequently deposited on a regrowth region of the mandrel structure to form a fin structure. The oxidizing and etching the mandrel structure provides a method for forming the fin structure which can achieve sub-10 nm node dimensions and provide increasingly smaller FinFETs.
    Type: Grant
    Filed: November 19, 2014
    Date of Patent: August 9, 2016
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Ying Zhang, Hua Chung
  • Patent number: 9406574
    Abstract: A method of making a semiconductor structure is provided. The method includes forming a tunneling layer over a channel connecting a source and a drain formed in a surface of a substrate, forming a charge storage layer overlying the tunneling layer, and forming a blocking structure on the charge storage layer by plasma oxidation. A thickness of the charge storage layer is reduced through oxidation of a portion of the charge storage layer during the formation of the blocking structure. Other embodiments are also described.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: August 2, 2016
    Assignee: CYPRESS SEMICONDUCTOR CORPORATION
    Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
  • Patent number: 9343540
    Abstract: A metal-insulator-semiconductor field-effect transistor (MISFET) includes a SiC layer with source and drain regions of a first conductivity type spaced apart therein. A first gate insulation layer is on the SiC layer and has a net charge along an interface with the SiC layer that is the same polarity as majority carriers of the source region. A gate contact is on the first gate insulation layer over a channel region of the SiC layer between the source and drain regions. The net charge along the interface between the first gate insulation layer and the SiC layer may deplete majority carriers from an adjacent portion of the channel region between the source and drain regions in the SiC layer, which may increase the threshold voltage of the MISFET and/or increase the electron mobility therein.
    Type: Grant
    Filed: August 14, 2014
    Date of Patent: May 17, 2016
    Assignee: Cree, Inc.
    Inventors: Sarit Dhar, Sei-Hyung Ryu
  • Patent number: 9287113
    Abstract: Methods and apparatus to form films on sensitive substrates while preventing damage to the sensitive substrate are provided herein. In certain embodiments, methods involve forming a bilayer film on a sensitive substrate that both protects the underlying substrate from damage and possesses desired electrical properties. Also provided are methods and apparatus for evaluating and optimizing the films, including methods to evaluate the amount of substrate damage resulting from a particular deposition process and methods to determine the minimum thickness of a protective layer. The methods and apparatus described herein may be used to deposit films on a variety of sensitive materials such as silicon, cobalt, germanium-antimony-tellerium, silicon-germanium, silicon nitride, silicon carbide, tungsten, titanium, tantalum, chromium, nickel, palladium, ruthenium, or silicon oxide.
    Type: Grant
    Filed: November 7, 2013
    Date of Patent: March 15, 2016
    Assignee: Novellus Systems, Inc.
    Inventors: Hu Kang, Shankar Swaminathan, Adrien LaVoie, Jon Henri
  • Patent number: 9263256
    Abstract: Provided is a method of forming a seed layer as a seed of a thin film on an underlayer, which includes: forming a first seed layer on a surface of the underlayer by heating the underlayer, followed by supplying an aminosilane-based gas onto the surface of the heated underlayer; and forming a second seed layer on the surface of the underlayer with the first seed layer formed thereon by heating the underlayer, followed by supplying a disilane or higher order silane-based gas onto the surface of the heated underlayer.
    Type: Grant
    Filed: December 27, 2013
    Date of Patent: February 16, 2016
    Assignee: Tokyo Electron Limited
    Inventors: Tomoyuki Obu, Takahiro Miyahara, Tomoyuki Nagata
  • Patent number: 9231070
    Abstract: An object is to provide a technique to manufacture an insulating film having excellent film characteristics. In particular, an object is to provide a technique to manufacture a dense insulating film with a high withstand voltage. Moreover, an object is to provide a technique to manufacture an insulating film with few electron traps. An insulating film including oxygen is subjected to plasma treatment using a high frequency under the conditions where the electron density is 1×1011 cm?3 or more and the electron temperature is 1.5 eV or less in an atmosphere including oxygen.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: January 5, 2016
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuya Kakehata, Tetsuhiro Tanaka, Yoshinobu Asami
  • Patent number: 9219162
    Abstract: A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.
    Type: Grant
    Filed: May 27, 2014
    Date of Patent: December 22, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama
  • Patent number: 9184276
    Abstract: A method of manufacturing an SiC semiconductor device includes the steps of forming a first oxide film on a first surface of an SiC semiconductor, removing the first oxide film, and forming a second oxide film constituting the SiC semiconductor device on a second surface exposed as a result of removal of the first oxide film in the SiC semiconductor. Between the step of removing the first oxide film and the step of forming a second oxide film, the SiC semiconductor is arranged in an atmosphere cut off from an ambient atmosphere.
    Type: Grant
    Filed: February 25, 2011
    Date of Patent: November 10, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Takeyoshi Masuda, Keiji Wada, Satomi Itoh, Toru Hiyoshi
  • Patent number: 9184172
    Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.
    Type: Grant
    Filed: December 12, 2014
    Date of Patent: November 10, 2015
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Geun Jee, Seok-Hoon Kim, Su-Jin Shin, Woo-Sung Lee, Tae-Ouk Kwon
  • Publication number: 20150118861
    Abstract: A method of semiconductor fabrication includes providing an unpatterned lightly doped Czochralski bulk silicon substrate (LDCBS substrate) having a concentration of oxygen atoms of at least (?) 1017 atoms/cm3 with a boron doping or n-type doping concentration of between 1×1012 cm?3 and 5×1014 cm?3. Before any oxidization processing, the LDCBS substrate is annealed at a nucleating temperature between 550° C. and 760° C. for a nucleating time that nucleates the oxygen atoms in a sub-surface region of the LDCBS substrate to form oxygen precipitates therefrom. After the annealing, a surface of the LDCBS substrate or an epitaxial layer on the surface of the LDCBS substrate is initially oxidized in an oxidizing ambient at a peak temperature of between 800° C. and 925° C. for a time less than or equal (?) to 30 minutes.
    Type: Application
    Filed: October 22, 2014
    Publication date: April 30, 2015
    Inventors: BRADLEY DAVID SUCHER, RICK L. WISE, SCOTT GERARD BALSTER, SEUNG-SA PARK, PHILIP LELAND HOWER, JOHN LIN, GURU MATHUR, YONGXI ZHANG
  • Patent number: 9011601
    Abstract: A substrate processing apparatus capable of forming an oxide film on a substrate by forming a layer on the substrate by supplying a source gas into a process vessel accommodating the substrate via the first nozzle, and simultaneously supplying an oxygen-containing gas through a second nozzle and a hydrogen-containing gas through a first nozzle into the process vessel having an inside pressure thereof lower than atmospheric pressure; mixing and reacting the oxygen-containing gas with the hydrogen-containing gas in a non-plasma atmosphere within the process vessel to generate atomic oxygen; and oxidizing the layer with the atomic oxygen to change the layer into an oxide layer is disclosed.
    Type: Grant
    Filed: July 11, 2014
    Date of Patent: April 21, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Patent number: 9006115
    Abstract: A method of forming a silicone oxide film includes: forming a silicon oxide film on a plurality of target objects by supplying a chlorine-containing silicon source into a reaction chamber accommodating the plurality of target objects; and modifying the silicon oxide film, which is formed by forming the silicon oxide film, by supplying hydrogen and oxygen or hydrogen and nitrous oxide into the reaction chamber and making an interior of the reaction chamber be under a hydrogen-oxygen atmosphere or a hydrogen-nitrous oxide atmosphere.
    Type: Grant
    Filed: June 28, 2013
    Date of Patent: April 14, 2015
    Assignee: Tokyo Electron Limited
    Inventors: Tomoyuki Obu, Masaki Kurokawa
  • Patent number: 8999783
    Abstract: A method for producing a semiconductor device is disclosed. The method includes providing a semiconductor body having a first surface, and a second surface opposite the first surface, producing a first trench having a bottom and sidewalls and extending from the first surface into the semiconductor body, forming a dielectric layer along at least one sidewall of the trench, and filling the trench with a filling material. Forming the dielectric layer includes forming a protection layer on the least one sidewall such that the protection layer leaves a section of the at least one sidewall uncovered, oxidizing the semiconductor body in the region of the uncovered sidewall section to form a first section of the dielectric layer, removing the protection layer, and forming a second section of the dielectric layer on the at least one sidewall.
    Type: Grant
    Filed: February 6, 2013
    Date of Patent: April 7, 2015
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Franz Hirler, Andreas Meiser
  • Patent number: 8993458
    Abstract: Methods and apparatus for improving selective oxidation against metals in a process chamber are provided herein. In some embodiments, a method of oxidizing a first surface of a substrate disposed in a process chamber having a processing volume defined by one or more chamber walls may include exposing the substrate to an oxidizing gas to oxidize the first surface; and actively heating at least one of the one or more chamber walls to increase a temperature of the one or more chamber walls to a first temperature of at least the dew point of water while exposing the substrate to the oxidizing gas.
    Type: Grant
    Filed: February 11, 2013
    Date of Patent: March 31, 2015
    Assignee: Applied Materials, Inc.
    Inventors: Agus Tjandra, Christopher S. Olsen, Johanes Swenberg, Lara Hawrylchak
  • Patent number: 8993453
    Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.
    Type: Grant
    Filed: September 14, 2012
    Date of Patent: March 31, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Jeong Byun, Sagy Levy
  • Patent number: 8986921
    Abstract: A lithographic material stack including a metal-compound hard mask layer is provided. The lithographic material stack includes a lower organic planarizing layer (OPL), a dielectric hard mask layer, and the metal-compound hard mask layer, an upper OPL, an optional anti-reflective coating (ARC) layer, and a photoresist layer. The metal-compound hard mask layer does not attenuate optical signals from lithographic alignment marks in underlying material layers, and can facilitate alignment between different levels in semiconductor manufacturing.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Bryan G. Morris, Tuan A. Vo, Christopher J. Waskiewicz, Yunpeng Yin
  • Patent number: 8987124
    Abstract: A silicon carbide substrate having a main face is prepared. By applying thermal oxidation to the main face of the silicon carbide substrate at a first temperature, an oxide film is formed on the main face. After the oxide film is formed, heat treatment is applied to the silicon carbide substrate at a second temperature higher than the first temperature. An opening exposing a portion of the main face is formed at the oxide film. A Schottky electrode is formed on the main face exposed by the opening.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: March 24, 2015
    Assignee: Sumitomo Electric Industries, Ltd.
    Inventors: Tomihito Miyazaki, Toru Hiyoshi
  • Patent number: 8975194
    Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.
    Type: Grant
    Filed: November 13, 2013
    Date of Patent: March 10, 2015
    Assignees: Peking University Founder Group Co., Ltd., Founder Microelectronics International Co., Ltd.
    Inventor: Jinyuan Chen
  • Patent number: 8951919
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a specific element, oxygen, carbon, and nitrogen by performing a cycle a predetermined number of times. The cycle includes supplying a specific element-containing gas, supplying a carbon-containing gas, supplying an oxidizing gas, and supplying a nitriding gas. The act of supplying the nitriding gas is performed before the act of supplying the specific element-containing gas, and the act of supplying the carbon-containing gas and the act of supplying the oxidizing gas are not performed until the act of supplying the specific element-containing gas is performed.
    Type: Grant
    Filed: April 11, 2014
    Date of Patent: February 10, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshinobu Nakamura
  • Patent number: 8946097
    Abstract: A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer.
    Type: Grant
    Filed: April 11, 2013
    Date of Patent: February 3, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Shunpei Yamazaki
  • Patent number: 8946092
    Abstract: An insulating film having features such as a low dielectric constant, a low etching rate and a high insulating property is formed. An oxycarbonitride film is formed on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a gas containing an element to the substrate; (b) supplying a carbon-containing gas to the substrate; (c) supplying a nitrogen-containing gas to the substrate; and (d) supplying an oxygen-containing gas to the substrate.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: February 3, 2015
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Yushin Takasawa, Tsukasa Kamakura, Yoshinobu Nakamura, Ryota Sasajima
  • Patent number: 8940645
    Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes subjecting a substrate to a first oxidation process to form a tunnel oxide layer overlying a polysilicon channel, and forming over the tunnel oxide layer a multi-layer charge storing layer comprising an oxygen-rich, first layer comprising a nitride, and an oxygen-lean, second layer comprising a nitride on the first layer. The substrate is then subjected to a second oxidation process to consume a portion of the second layer and form a high-temperature-oxide (HTO) layer overlying the multi-layer charge storing layer. The stoichiometric composition of the first layer results in it being substantially trap free, and the stoichiometric composition of the second layer results in it being trap dense. The second oxidation process can comprise a plasma oxidation process or a radical oxidation process using In-Situ Steam Generation.
    Type: Grant
    Filed: July 1, 2012
    Date of Patent: January 27, 2015
    Assignee: Cypress Semiconductor Corporation
    Inventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
  • Publication number: 20150008483
    Abstract: The disclosure relates to a fin field effect transistor (FinFET). An exemplary FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material having the first lattice constant; a middle portion between the lower portion and upper portion, wherein the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant; and a pair of notches extending into opposite sides of the middle portion; and an isolation structure surrounding the fin structure, wherein a top surface of the isolation structure is higher than a top surface of the pair of notches.
    Type: Application
    Filed: July 3, 2013
    Publication date: January 8, 2015
    Inventors: Kuo-Cheng Ching, Chih-Hao Wang, Zhiqiang Wu, Carlos H. Diaz, Jean-Pierre Colinge
  • Patent number: 8927409
    Abstract: An apparatus includes a wafer annealing tool and a plurality of electrodes coupled to the wafer annealing tool, wherein the electrodes are configured to be in physical contact with a wafer so that, when the wafer is annealed, a negative electrical bias is formed across one or more gate stacks of the wafer.
    Type: Grant
    Filed: October 4, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventor: Martin M. Frank
  • Publication number: 20140377964
    Abstract: The disclosure relates to an apparatus for oxidation and annealing processes comprising: a chamber; an oxidizing unit located in the chamber, where an oxidizing process for a subject to be processed is conducted; and an annealing unit located in the chamber, where an annealing process for the subject to be processed is conducted. Further, The disclosure relates to a method for the oxidation and annealing processes comprising: preparing a chamber comprising an oxidizing unit and an annealing unit; preparing a subject to be processed on a susceptor located in the oxidizing unit; oxidizing the subject to be processed; converting atmosphere of the oxidizing unit; transferring the subject to be processed to the annealing unit; and annealing the subject to be processed.
    Type: Application
    Filed: August 10, 2012
    Publication date: December 25, 2014
    Applicant: LG INNOTEK CO., LTD.
    Inventors: Seon Heo, Chang Hyun Son
  • Patent number: 8889565
    Abstract: Oxygen is selectively removed from metal-containing materials in a partially-fabricated integrated circuit. In some embodiments, the partially-fabricated integrated circuit has exposed silicon and metal-containing materials, e.g., as part of a transistor. The silicon and metal-containing material are oxidized. Oxygen is subsequently removed from the metal-containing material by an anneal in an atmosphere containing a reducing agent. Advantageously, the silicon oxide formed by the silicon oxidation is maintained while oxygen is removed from the metal-containing material, thereby leaving a high quality metal-containing material along with silicon oxide.
    Type: Grant
    Filed: February 5, 2010
    Date of Patent: November 18, 2014
    Assignee: ASM International N.V.
    Inventors: Jerome Noiray, Ernst H. A. Granneman
  • Patent number: 8883641
    Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Alchimer
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 8871645
    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Patent number: 8853099
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 7, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140291680
    Abstract: A silicon member and a method of producing the silicon member are provided. Cracking is suppressed in the silicon member even if the silicon member is used in a condition where it is heated. The silicon member 10 includes a coating layer 11 that coats a surface of the silicon member 10, wherein the coating layer 11 is composed of a product of silicon formed by reaction of the silicon on the surface, and a thickness of the coating layer is 15 nm or more and 600 nm or less. It is preferable that the coating layer is a silicon oxide film or a silicon nitride film.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventor: Yoshinobu Nakada
  • Patent number: 8846544
    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 30, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tadashi Misumi, Shinya Iwasaki, Takahide Sugiyama
  • Publication number: 20140287594
    Abstract: A cleaning method includes (a) providing a process chamber after forming an oxide film on a substrate in the process chamber formed by a reaction tube and a manifold supporting the reaction tube by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate through a first nozzle in the manifold extending upward to an inside of the reaction tube, and supplying an oxidizing gas to the substrate through a second nozzle in the manifold extending upward to the inside of the reaction tube; and (b) cleaning an inside of the process chamber. The step (b) includes a first cleaning process of supplying a hydrogen fluoride gas into the reaction tube through the second nozzle; and a second cleaning process of supplying a hydrogen fluoride gas onto an inner wall surface of the manifold through a third nozzle disposed in the manifold.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Masato TERASAKI, Naonori AKAE, Hideki HORITA
  • Patent number: 8835909
    Abstract: Thin-film transistors are made using an organosilicate glass (OSG) as an insulator material. The organosilicate glasses may be SiO2-silicone hybrid materials deposited by plasma-enhanced chemical vapor deposition from siloxanes and oxygen. These hybrid materials may be employed as the gate dielectric, as a subbing layer, and/or as a back channel passivating layer. The transistors may be made in any conventional TFT geometry.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: September 16, 2014
    Assignee: The Trustees of Princeton University
    Inventors: Lin Han, Prashant Mandlik, Sigurd Wagner
  • Patent number: 8836001
    Abstract: A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Eun-Shil Park, Ju-Hyun Myung
  • Patent number: 8822349
    Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: September 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
  • Publication number: 20140239461
    Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: IMEC
    Inventors: Annelies Delabie, Matty Caymax
  • Patent number: 8815708
    Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 8815699
    Abstract: Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tong Weihua, Krishnan Bharat, Lun Zhao, Kim Seung, Lee Yongmeng, Kim Sun
  • Patent number: 8809204
    Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: August 19, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota