Oxidation Patents (Class 438/770)
  • Patent number: 8883641
    Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Alchimer
    Inventors: Vincent Mevellec, Dominique Suhr
  • Patent number: 8871645
    Abstract: Semiconductor devices suitable for narrow pitch applications and methods of fabrication thereof are described herein. In some embodiments, a semiconductor device may include a floating gate having a first width proximate a base of the floating gate that is greater than a second width proximate a top of the floating gate. In some embodiments, a method of shaping a material layer may include (a) oxidizing a surface of a material layer to form an oxide layer at an initial rate; (b) terminating formation of the oxide layer when the oxidation rate is about 90% or below of the initial rate; (c) removing at least some of the oxide layer by an etching process; and (d) repeating (a) through (c) until the material layer is formed to a desired shape. In some embodiments, the material layer may be a floating gate of a semiconductor device.
    Type: Grant
    Filed: September 11, 2009
    Date of Patent: October 28, 2014
    Assignee: Applied Materials, Inc.
    Inventors: Udayan Ganguly, Yoshita Yokota, Jing Tang, Sunderraj Thirupapuliyur, Christopher Sean Olsen, Shiyu Sun, Tze Wing Poon, Wei Liu, Johanes Swenberg, Vicky U. Nguyen, Swaminathan Srinivasan, Jacob Newman
  • Patent number: 8871615
    Abstract: According to one embodiment, a method includes forming a first SiGe layer having a first profile of a concentration of Ge on a semiconductor substrate, forming a second SiGe layer having a second profile of a concentration of Ge on the first SiGe layer, the second profile lower than a first peak of the first profile, forming a mask layer on the second SiGe layer, etching the first and second SiGe layers by anisotropic etching using the mask layer as a mask to form trenches, selectively removing the first SiGe layer exposed into the trenches to form a cavity under the second SiGe layer, and oxidizing side and lower surfaces of the second SiGe layer exposed in the trenches and the cavity to increase the concentration of Ge in the second SiGe layer.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: October 28, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Shinji Mori
  • Patent number: 8853099
    Abstract: A nonvolatile resistive memory element has a novel variable resistance layer that includes a metal nitride, a metal oxide-nitride, a two-metal oxide-nitride, or a multilayer stack thereof. One method of forming the novel variable resistance layer comprises an interlayer deposition procedure, in which metal oxide layers are interspersed with metal nitride layers and then converted into a substantially homogeneous layer by an anneal process. Another method of forming the novel variable resistance layer comprises an intralayer deposition procedure, in which various ALD processes are sequentially interleaved to form a metal oxide-nitride layer. Alternatively, a metal oxide is deposited, nitridized, and annealed to form the variable resistance layer or a metal nitride is deposited, oxidized, and annealed to form the variable resistance layer.
    Type: Grant
    Filed: December 16, 2011
    Date of Patent: October 7, 2014
    Assignees: Intermolecular, Inc., Kabushiki Kaisha Toshiba, SanDisk 3D LLC
    Inventors: Yun Wang, Tony P. Chiang, Imran Hashim, Tim Minvielle, Takeshi Yamaguchi
  • Publication number: 20140291680
    Abstract: A silicon member and a method of producing the silicon member are provided. Cracking is suppressed in the silicon member even if the silicon member is used in a condition where it is heated. The silicon member 10 includes a coating layer 11 that coats a surface of the silicon member 10, wherein the coating layer 11 is composed of a product of silicon formed by reaction of the silicon on the surface, and a thickness of the coating layer is 15 nm or more and 600 nm or less. It is preferable that the coating layer is a silicon oxide film or a silicon nitride film.
    Type: Application
    Filed: March 27, 2014
    Publication date: October 2, 2014
    Applicant: MITSUBISHI MATERIALS CORPORATION
    Inventor: Yoshinobu Nakada
  • Patent number: 8846544
    Abstract: A semiconductor device comprises a semiconductor substrate, a first electrode formed on a first main surface of the semiconductor substrate, and a second electrode formed on a second main surface of the semiconductor substrate. The semiconductor substrate includes a first region in which a density of oxygen-vacancy defects is greater than a density of vacancy cluster defects, and a second region in which the density of vacancy cluster defects is greater than the density of oxygen-vacancy defects.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: September 30, 2014
    Assignee: Toyota Jidosha Kabushiki Kaisha
    Inventors: Tadashi Misumi, Shinya Iwasaki, Takahide Sugiyama
  • Publication number: 20140287594
    Abstract: A cleaning method includes (a) providing a process chamber after forming an oxide film on a substrate in the process chamber formed by a reaction tube and a manifold supporting the reaction tube by performing a cycle a predetermined number of times, the cycle including supplying a source gas to the substrate through a first nozzle in the manifold extending upward to an inside of the reaction tube, and supplying an oxidizing gas to the substrate through a second nozzle in the manifold extending upward to the inside of the reaction tube; and (b) cleaning an inside of the process chamber. The step (b) includes a first cleaning process of supplying a hydrogen fluoride gas into the reaction tube through the second nozzle; and a second cleaning process of supplying a hydrogen fluoride gas onto an inner wall surface of the manifold through a third nozzle disposed in the manifold.
    Type: Application
    Filed: March 24, 2014
    Publication date: September 25, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Masato TERASAKI, Naonori AKAE, Hideki HORITA
  • Patent number: 8835909
    Abstract: Thin-film transistors are made using an organosilicate glass (OSG) as an insulator material. The organosilicate glasses may be SiO2-silicone hybrid materials deposited by plasma-enhanced chemical vapor deposition from siloxanes and oxygen. These hybrid materials may be employed as the gate dielectric, as a subbing layer, and/or as a back channel passivating layer. The transistors may be made in any conventional TFT geometry.
    Type: Grant
    Filed: July 30, 2009
    Date of Patent: September 16, 2014
    Assignee: The Trustees of Princeton University
    Inventors: Lin Han, Prashant Mandlik, Sigurd Wagner
  • Patent number: 8836001
    Abstract: A method for fabricating a semiconductor device includes forming at least one body having two sidewalls by vertically etching a semiconductor substrate, forming a protective layer having open parts that expose portions of the both sidewalls of the body, forming a buffer layer that fills the open parts, and forming a buried bit line in the body by siliciding the buffer layer and a portion of the body between the buffer layer.
    Type: Grant
    Filed: June 12, 2012
    Date of Patent: September 16, 2014
    Assignee: SK Hynix Inc.
    Inventors: Eun-Shil Park, Ju-Hyun Myung
  • Patent number: 8822349
    Abstract: A method of making a semiconductor structure is provided. The method includes forming a dielectric layer using a high density plasma oxidation process. The dielectric layer is on a storage layer and the thickness of the storage layer is reduced during the high density plasma oxidation process.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: September 2, 2014
    Assignee: Cypress Semiconductor Corporation
    Inventors: Jeong Soo Byun, Krishnaswamy Ramkumar
  • Publication number: 20140239461
    Abstract: A Si or Ge semi-conductor substrate includes an oxygen monolayer on a surface thereof. The oxygen monolayer can be fractional or complete. A Si4+ or Ge4+ oxidation state of the surface of the Si or Ge substrate, respectively, resulting from the presence of the oxygen monolayer represents less than 50%, preferably less than 40% and more preferably less than 30% of the sum of Si1+, Si2+, Si3+ and Si4+ oxidation states or the sum of Ge1+, Ge2+, Ge3+ and Ge4+ oxidation states, respectively, as measured by XPS.
    Type: Application
    Filed: February 20, 2014
    Publication date: August 28, 2014
    Applicant: IMEC
    Inventors: Annelies Delabie, Matty Caymax
  • Patent number: 8815708
    Abstract: A method for improving the quality of a SiC layer by effectively reducing or eliminating the carrier trapping centers in the as-grown SiC crystal. The method includes the steps of: (a) carrying out ion implantation of carbon atoms, silicon atoms, hydrogen atoms, or helium atoms into a shallow surface layer of the SiC crystal layer to introduce carbon interstitials into the surface layer, and (b) growing the SiC layer upward from the edge face of the surface layer into which the carbon interstitials have been introduced, and diffusing out the carbon interstitials that have been introduced into the surface layer from the surface layer into the grown layer and combining the carbon interstitials and point defects to make the electrically active point defects in the grown layer inactive.
    Type: Grant
    Filed: March 16, 2010
    Date of Patent: August 26, 2014
    Assignee: Central Research Institute of Electric Power Industry
    Inventors: Hidekazu Tsuchida, Liutauras Storasta
  • Patent number: 8815699
    Abstract: Generally, the present disclosure is directed to methods for forming reverse shallow trench isolation structures with super-steep retrograde wells for use with field effect transistor elements. One illustrative method disclosed herein includes performing a thermal oxidation process to form a layer of thermal oxide material on a semiconductor layer of a semiconductor substrate, and forming a plurality of openings in the layer of thermal oxide material to form a plurality of isolation regions from the layer of thermal oxide material, wherein each of the plurality of openings exposes a respective surface region of the semiconductor layer.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: August 26, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Tong Weihua, Krishnan Bharat, Lun Zhao, Kim Seung, Lee Yongmeng, Kim Sun
  • Patent number: 8809201
    Abstract: The present invention provides; a method for forming a metal oxide film which has both a surface irregularity and a predetermined pattern or either and has few unevenness of surface specific resistance, light transmittance and the like, and such the metal oxide film. The method for forming a metal oxide film having both a surface irregularity and a predetermined pattern or either on a substrate, wherein, the method comprises a first process in which a liquid material containing a metal salt is applied on the substrate to form a metal salt film, a second process in which a surface irregularity or a predetermined pattern is formed to the metal salt film, and a third process in which the metal salt film is converted to a metal oxide film by thermal oxidation treatment or plasma oxidation treatment.
    Type: Grant
    Filed: March 23, 2010
    Date of Patent: August 19, 2014
    Assignee: Lintec Corporation
    Inventors: Satoshi Naganawa, Takeshi Kondo
  • Patent number: 8809204
    Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: August 19, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
  • Publication number: 20140220787
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a specific element, oxygen, carbon, and nitrogen by performing a cycle a predetermined number of times. The cycle includes supplying a specific element-containing gas, supplying a carbon-containing gas, supplying an oxidizing gas, and supplying a nitriding gas. The act of supplying the nitriding gas is performed before the act of supplying the specific element-containing gas, and the act of supplying the carbon-containing gas and the act of supplying the oxidizing gas are not performed until the act of supplying the specific element-containing gas is performed.
    Type: Application
    Filed: April 11, 2014
    Publication date: August 7, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Ryota SASAJIMA, Yoshinobu NAKAMURA
  • Publication number: 20140213069
    Abstract: A substrate processing apparatus includes a process chamber in which a substrate is accommodated; a source gas supply system configured to supply a source gas onto the substrate; first and second reactive gas supply systems configured to supply a reactive gas onto the substrate via first and second interconnected reactive gas supply pipes, wherein a gas storage unit is installed at the second reactive gas supply pipe to store the reactive gas and the reactive gas is supplied onto the substrate via the gas storage unit; and a control unit configured to control the source gas supply system to supply the source gas onto the substrate and to control the first and second reactive gas supply systems to supply the reactive gas onto the substrate via the first and second reactive gas supply pipes.
    Type: Application
    Filed: January 23, 2014
    Publication date: July 31, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Yuji Takebayashi, Masakazu Shimada, Atsushi Morikawa
  • Patent number: 8791026
    Abstract: A method and an apparatus for treating a silicon substrate for effectively removing a silicon oxide film formed on a surface of a silicon film and improving surface uniformity of the silicon film. The method comprises providing a substrate including a silicon film; providing a first fluid, which is capable of etching a silicon oxide film, to a surface of the substrate in a first time band; providing a second fluid containing water to the surface of the substrate in a second time band, which is different from the first time band; and providing a third fluid, which is capable of etching the silicon oxide film, has different ingredients as compared to the first fluid, and has high etching ratio with respect to the silicon oxide film, to a surface of the substrate in a third time band, which is different from the first time band and the second time band.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: July 29, 2014
    Assignee: MMTech Co., Ltd.
    Inventors: Kil Soo An, Seung Il Chang
  • Patent number: 8790982
    Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
    Type: Grant
    Filed: July 19, 2013
    Date of Patent: July 29, 2014
    Assignee: Micron Technology, Inc.
    Inventors: Li Li, Pai-Hung Pan
  • Publication number: 20140199853
    Abstract: A method of forming a silicon oxide film includes forming a silicon film on a base, the base being a surface to be processed of an object to be processed, and forming a silicon oxide film on the base by oxidizing the silicon film. Between the forming a silicon film and the forming a silicon oxide film, exposing the object to be processed having the silicon film formed thereon to an atmosphere containing at least an oxidizing component is performed.
    Type: Application
    Filed: January 14, 2014
    Publication date: July 17, 2014
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hiroki MURAKAMI, Toshiyuki IKEUCHI, Jun SATO, Yuichiro MOROZUMI
  • Patent number: 8741784
    Abstract: A process for fabricating a semiconductor device is described. A silicon oxide layer is formed. A nitridation process including at least two steps is performed to nitridate the silicon oxide layer into a silicon oxynitride (SiON) layer. The nitridation process comprises a first nitridation step and a second nitridation step in sequence, wherein the first nitridation step and the second nitridation step are different in the setting of at least one parameter.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: June 3, 2014
    Assignee: United Microelectronics Corp.
    Inventors: Chien-Liang Lin, Te-Lin Sun, Ying-Wei Yen, Yu-Ren Wang
  • Patent number: 8728954
    Abstract: A method of manufacturing a semiconductor device includes forming a thin film containing a specific element, oxygen, carbon, and nitrogen by performing a cycle a predetermined number of times. The cycle includes supplying a specific element-containing gas, supplying a carbon-containing gas, supplying an oxidizing gas, and supplying a nitriding gas. The act of supplying the nitriding gas is performed before the act of supplying the specific element-containing gas, and the act of supplying the carbon-containing gas and the act of supplying the oxidizing gas are not performed until the act of supplying the specific element-containing gas is performed.
    Type: Grant
    Filed: August 9, 2013
    Date of Patent: May 20, 2014
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Ryota Sasajima, Yoshinobu Nakamura
  • Patent number: 8728951
    Abstract: A method of processing a substrate includes performing a first exposure that comprises generating a plasma containing reactive gas ions in a plasma chamber and generating a bias voltage between the substrate and the plasma chamber. The method also includes providing a plasma sheath modifier having an aperture disposed between the plasma and substrate and operable to direct the reactive gas ions toward the substrate, and establishing a pressure differential between the plasma chamber and substrate region while the reactive gas ions are directed onto the substrate.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 20, 2014
    Assignee: Varian Semiconductor Equipment Associates, Inc.
    Inventors: Ludovic Godet, Xianfeng Lu, Deepak A. Ramappa
  • Patent number: 8716156
    Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.
    Type: Grant
    Filed: February 1, 2013
    Date of Patent: May 6, 2014
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Bartlomiej Jan Pawlak, Steven Bentley, Ajey Jacob
  • Patent number: 8710682
    Abstract: The present invention provides polyimide polymer materials for passivating semiconductor wafers and methods for fabricating thereof. The present invention further provides a device that includes a semiconductor wafer and a passivating layer disposed on the surface of the wafer, wherein the passivating layer comprises such polyimide polymers.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: April 29, 2014
    Assignee: Designer Molecules Inc, Inc.
    Inventors: Stephen M Dershem, Farhad G Mizori, James T Huneke
  • Patent number: 8671878
    Abstract: An apparatus for forming spacers is provided. A plasma processing chamber is provided, comprising a chamber wall, a substrate support, a pressure regulator, an antenna, a bias electrode, a gas inlet, and a gas outlet. A gas source comprises an oxygen gas source and an anisotropic etch gas source. A controller comprises a processor and computer readable media. The computer readable media comprises computer readable code for placing a substrate of the plurality of substrates in a plasma etch chamber, computer readable code for providing a plasma oxidation treatment to form a silicon oxide coating over the spacer layer, computer readable code for sputtering silicon to form silicon oxide with the oxygen plasma, computer readable code for providing an anisotropic main etch, computer readable code for etching the spacer layer, computer readable code for removing the substrate from the plasma etch chamber after etching the spacer layer.
    Type: Grant
    Filed: September 27, 2012
    Date of Patent: March 18, 2014
    Assignee: Lam Research Corporation
    Inventors: Qinghua Zhong, Sung Cho, Gowri Kamarthy, Linda Braly
  • Patent number: 8662886
    Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for controlling oxide formation using pressure. The present invention, in one or more implementations, includes a pressure stabilization system to dynamically adjust scavenger pressure in a furnace during wafer fabrication in relation to a pressure formation range, value, or one or more pressure indicators in a wafer fabrication process.
    Type: Grant
    Filed: November 12, 2007
    Date of Patent: March 4, 2014
    Assignee: Micrel, Inc.
    Inventor: Miles Dudman
  • Publication number: 20140057455
    Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.
    Type: Application
    Filed: October 1, 2013
    Publication date: February 27, 2014
    Applicant: APPLIED MATERIALS, INC.
    Inventors: Yoshitaka YOKOTA, Norman L. TAM, Balasubramanian RAMACHANDRAN, Martin John RIPLEY
  • Publication number: 20140051261
    Abstract: Provided are: forming an oxycarbonitride film, an oxycarbide film or an oxide film on a substrate by alternately performing a specific number of times: forming a first layer containing the specific element, nitrogen and carbon, on the substrate, by alternately performing a specific number of times, supplying a first source containing the specific element and a halogen-group to the substrate in a processing chamber, and supplying a second source containing the specific element and an amino-group to the substrate in the processing chamber; and forming a second layer by oxidizing the first layer by supplying an oxygen-containing gas, and an oxygen-containing gas and a hydrogen-containing gas to the substrate in the processing chamber.
    Type: Application
    Filed: March 7, 2012
    Publication date: February 20, 2014
    Applicant: HITACHI KOKUSAI ELECTRIC INC.
    Inventors: Yosuke Ota, Yoshiro Hirose
  • Patent number: 8642486
    Abstract: A control unit heats a reaction pipe to a load temperature by controlling a temperature-raising heater 16, and then makes semiconductor wafers received in the reaction pipe. Next, the control unit heats the reaction pipe in which the semiconductor wafers are received to a film formation temperature by controlling the temperature-raising heater, and then forms thin films on the semiconductor wafers by supplying a film forming gas into the reaction pipe from a process gas introducing pipe. Also, the control unit sets the load temperature to a temperature higher than the film formation temperature.
    Type: Grant
    Filed: December 27, 2011
    Date of Patent: February 4, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Toshiyuki Ikeuchi, Pao-Hwa Chou, Kazuya Yamamoto, Kentarou Sera
  • Publication number: 20140024225
    Abstract: An insulating film having features such as a low dielectric constant, a low etching rate and a high insulating property is formed. An oxycarbonitride film is formed on a substrate by performing a cycle a predetermined number of times, the cycle including: (a) supplying a gas containing an element to the substrate; (b) supplying a carbon-containing gas to the substrate; (c) supplying a nitrogen-containing gas to the substrate; and (d) supplying an oxygen-containing gas to the substrate.
    Type: Application
    Filed: September 25, 2013
    Publication date: January 23, 2014
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro HIROSE, Yushin TAKASAWA, Tsukasa KAMAKURA, Yoshinobu NAKAMURA, Ryota SASAJIMA
  • Patent number: 8614124
    Abstract: Scaling a nonvolatile trapped-charge memory device and the article made thereby. In an embodiment, scaling includes multiple oxidation and nitridation operations to provide a tunneling layer with a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. In an embodiment, scaling includes forming a charge trapping layer with a non-homogenous oxynitride stoichiometry. In one embodiment the charge trapping layer includes a silicon-rich, oxygen-rich layer and a silicon-rich, oxygen-lean oxynitride layer on the silicon-rich, oxygen-rich layer. In an embodiment, the method for scaling includes a dilute wet oxidation to density a deposited blocking oxide and to oxidize a portion of the silicon-rich, oxygen-lean oxynitride layer.
    Type: Grant
    Filed: September 26, 2007
    Date of Patent: December 24, 2013
    Assignee: Cypress Semiconductor Corporation
    Inventors: Fredrick B. Jenne, Sagy Charel Levy
  • Patent number: 8609554
    Abstract: A semiconductor structure and a method for manufacturing the same are provided. The method comprises following steps. A first silicon-containing conductive material is formed on a substrate. A second silicon-containing conductive material is formed on the first silicon-containing conductive material. The first silicon-containing conductive material and the second silicon-containing conductive material have different dopant conditions. The first silicon-containing conductive material and the second silicon-containing conductive material are thermally oxidized for turning the first silicon-containing conductive material wholly into an insulating oxide structure, and the second silicon-containing conductive material into a silicon-containing conductive structure and an insulating oxide layer.
    Type: Grant
    Filed: January 19, 2011
    Date of Patent: December 17, 2013
    Assignee: Macronix International Co., Ltd.
    Inventors: Hang-Ting Lue, Yi-Hsuan Hsiao
  • Patent number: 8598049
    Abstract: A deposition method capable of forming an oxide film with a predetermined film thickness ratio using a deposition gas with which a small film thickness ratio is obtained and a deposition gas with which a large film thickness ratio is obtained. When forming an oxide film having a larger film thickness on the surface of a substrate than on the bottom surface of the hole so that the film thickness ratio of the oxide film formed on the surface of the substrate to the oxide film formed on the bottom surface of the hole becomes a predetermined ratio, plasma is generated from a gas mixture including tetraethoxysilane and oxygen to form an oxide film and then plasma is generated from a gas mixture including silane and nitrous oxide.
    Type: Grant
    Filed: November 25, 2010
    Date of Patent: December 3, 2013
    Assignee: SecureView LLC
    Inventors: Masayasu Hatashita, Akimitsu Oishi, Shoichi Murakami
  • Patent number: 8598706
    Abstract: A method for forming an interlayer dielectric film by a plasma CVD method, including turning off a radio frequency power and purging with an inert gas simultaneously.
    Type: Grant
    Filed: September 17, 2008
    Date of Patent: December 3, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hironori Yamamoto, Fuminori Ito, Yoshihiro Hayashi
  • Patent number: 8598018
    Abstract: The present invention provides a method of forming an electrode having reduced corrosion and water decomposition on a surface thereof. A conductive layer is deposited on a substrate. The conductive layer is partially oxidized by an oxygen plasma process to convert a portion thereof to an oxide layer thereby forming the electrode. The oxide layer is free of surface defects and the thickness of the oxide layer is from about 0.09 nm to about 10 nm and ranges therebetween, controllable with 0.2 nm precision.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: December 3, 2013
    Assignee: International Business Machines Corporation
    Inventors: Ali Afzali-Azdakani, Shafaat Ahmed, Hariklia Deligianni, Dario L. Goldfarb, Stefan Harrer, Hongbo Peng, Stanislav Polonsky, Stephen Rossnagel, Xiaoyan Shao, Gustavo A. Stolovitzky
  • Publication number: 20130316515
    Abstract: [Problem] To provide a method capable of forming an insulating film suffering less from both shrinkage and stress. [Means for solving] A method for forming a silicon dioxide film, comprising the steps of: coating a substrate with a polysilazane composition to form a coat, and then heating the formed coat in a hydrogen peroxide atmosphere at 50 to 200° C. This method enables to form isolation structures such as various insulating films.
    Type: Application
    Filed: February 16, 2012
    Publication date: November 28, 2013
    Applicant: AZ ELECTRONIC MATERIALS (LUXEMBOURG) S.a.r.L.
    Inventors: Tatsuro Nagahara, Masanobu Hayashi, Katsuchika Suzuki
  • Patent number: 8592325
    Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.
    Type: Grant
    Filed: January 11, 2010
    Date of Patent: November 26, 2013
    Assignee: International Business Machines Corporation
    Inventors: Joseph F. Shepard, Jr., Siddarth A. Krishnan, Rishikesh Krishnan, Michael P. Chudzik
  • Publication number: 20130309877
    Abstract: A silicon carbide semiconductor device (90), includes: 1) a silicon carbide substrate (1); 2) a gate electrode (7) made of polycrystalline silicon; and 3) an ONO insulating film (9) sandwiched between the silicon carbide substrate (1) and the gate electrode (7) to thereby form a gate structure, the ONO insulating film (9) including the followings formed sequentially from the silicon carbide substrate (1): a) a first oxide silicon film (O) (10), b) an SiN film (N) (11), and c) an SiN thermally-oxidized film (O) (12, 12a, 12b). Nitrogen is included in at least one of the following places: i) in the first oxide silicon film (O) (10) and in a vicinity of the silicon carbide substrate (1), and ii) in an interface between the silicon carbide substrate (1) and the first oxide silicon film (O) (10).
    Type: Application
    Filed: July 29, 2013
    Publication date: November 21, 2013
    Applicants: ROHM CO., LTD., NISSAN MOTOR CO., LTD.
    Inventors: Satoshi TANIMOTO, Noriaki KAWAMOTO, Takayuki KITOU, Mineo MIURA
  • Publication number: 20130309855
    Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.
    Type: Application
    Filed: July 19, 2013
    Publication date: November 21, 2013
    Inventors: Li Li, Pai-Hung Pan
  • Patent number: 8580698
    Abstract: A method for fabricating the gate dielectric layer comprises forming a high-k dielectric layer over a substrate; forming an oxygen-containing layer on the high-k dielectric layer by an atomic layer deposition process; and performing an inert plasma treatment on the oxygen-containing layer.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 12, 2013
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Yang Lee, Xiong-Fei Yu, Jian-Hao Chen, Cheng-Hao Hou, Da-Yuan Lee, Kuang-Yuan Hsu
  • Patent number: 8557716
    Abstract: A thin film can be formed on a substrate at a low temperature with a practicable film-forming rate. There is provided a semiconductor device manufacturing method for forming an oxide or nitride film on a substrate. The method comprises: exposing the substrate to a source gas; exposing the substrate to a modification gas comprising an oxidizing gas or a nitriding gas, wherein an atom has electronegativity different from that of another atom in molecules of the oxidizing gas or the nitriding gas; and exposing the substrate to a catalyst. The catalyst has acid dissociation constant pKa in a range from 5 to 7, but a pyridine is not used as the catalyst.
    Type: Grant
    Filed: February 17, 2010
    Date of Patent: October 15, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventor: Norikazu Mizuno
  • Patent number: 8546920
    Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.
    Type: Grant
    Filed: October 15, 2012
    Date of Patent: October 1, 2013
    Assignee: International Business Machines Corporation
    Inventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
  • Patent number: 8546272
    Abstract: An insulating film having features such as a low dielectric constant, a low etching rate and a high insulating property is formed.
    Type: Grant
    Filed: April 8, 2011
    Date of Patent: October 1, 2013
    Assignee: Hitachi Kokusai Electric Inc.
    Inventors: Yoshiro Hirose, Yushin Takasawa, Tsukasa Kamakura, Yoshinobu Nakamura, Ryota Sasajima
  • Patent number: 8547085
    Abstract: An arrangement for measuring process parameters within a processing chamber is provided. The arrangement includes a probe arrangement disposed in an opening of an upper electrode. Probe arrangement includes a probe head, which includes a head portion and a flange portion. The arrangement also includes an o-ring disposed between the upper electrode and the flange portion. The arrangement further includes a spacer made of an electrically insulative material positioned between the head portion and the opening of the upper electrode to prevent the probe arrangement from touching the upper electrode. The spacer includes a disk portion configured for supporting an underside of the flange portion. The spacer also includes a hollow cylindrical portion configured to encircle the head portion. The spacer forms a right-angled path between the o-ring and an opening to the processing chamber to prevent direct line-of-sight path between the o-ring and the opening to the processing chamber.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: October 1, 2013
    Assignee: Lam Research Corporation
    Inventors: Jean-Paul Booth, Douglas Keil
  • Patent number: 8536066
    Abstract: Methods of forming an oxide layer on silicon carbide include thermally growing an oxide layer on a layer of silicon carbide, and annealing the oxide layer in an environment containing NO at a temperature greater than 1175° C. The oxide layer may be annealed in NO in a silicon carbide tube that may be coated with silicon carbide. To form the oxide layer, a preliminary oxide layer may be thermally grown on a silicon carbide layer in dry O2, and the preliminary oxide layer may be re-oxidized in wet O2.
    Type: Grant
    Filed: May 10, 2010
    Date of Patent: September 17, 2013
    Assignee: Cree, Inc.
    Inventors: Mrinal K. Das, Brett Hull, Sumi Krishnaswami
  • Patent number: 8501636
    Abstract: A method for fabricating silicon dioxide layer is disclosed. The method includes the following steps. Firstly, a semiconductor substrate is provided. Next, the semiconductor substrate is cleaned with a solution containing hydrogen peroxide to form a chemical oxide layer on the semiconductor substrate. Then, the chemical oxide layer is heated in no oxygen atmosphere, such that the chemical oxide layer forms a compact layer. Then, the semiconductor substrate is heated in oxygen atmosphere to form a silicon dioxide layer between the semiconductor substrate and the compact layer.
    Type: Grant
    Filed: July 24, 2012
    Date of Patent: August 6, 2013
    Assignee: United Microelectronics Corp.
    Inventors: Shao-Wei Wang, Yu-Ren Wang, Chien-Liang Lin, Ying-Wei Yen, Kun-Yuan Lo, Chih-Wei Yang
  • Patent number: 8492289
    Abstract: A method of forming a barrier layer for metal interconnects of an integrated circuit device includes forming a first cap layer over a top surface of a conductive line of the integrated circuit device in a manner that facilitates a controllable dose of oxygen provided to the top surface of the conductive line, the conductive line comprising a metal formed over a seed layer that is an impurity alloy of the metal; and annealing the integrated circuit device so as to combine diffused impurity atoms of the seed layer with the controllable dose of oxygen, thereby forming an impurity oxide layer at an interface between the first cap layer and the top surface of the conductive line.
    Type: Grant
    Filed: September 15, 2010
    Date of Patent: July 23, 2013
    Assignee: International Business Machines Corporation
    Inventors: Daniel C. Edelstein, Takeshi Nogami, Hosadurga K. Shobha
  • Patent number: 8492290
    Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 23, 2013
    Assignees: International Business Machines Corporation, Globalfoundries Inc.
    Inventors: Michael P. Chudzik, Min Dai, Joseph F. Shepard, Jr., Shahab Siddiqui, Jinping Liu
  • Patent number: 8492292
    Abstract: Methods for processing substrates are provided herein. In some embodiments, a method for processing a substrate includes providing a substrate having an oxide layer disposed thereon, the oxide layer including one or more defects; and exposing the oxide layer to a plasma formed from a process gas comprising an oxygen-containing gas to repair the one or more defects. In some embodiments, the oxide layer may be formed on the substrate. In some embodiments, forming the oxide layer further comprises depositing the oxide layer atop the substrate. In some embodiments, forming the oxide layer further comprises thermally oxidizing the surface of the substrate to form the oxide layer. In some embodiments, a processing temperature is maintained at about 700 degrees Celsius or below during the thermal oxidation of the surface.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: July 23, 2013
    Assignee: Applied Materials, Inc.
    Inventors: Yoshitaka Yokota, Christopher S. Olsen, Agus Sofian Tjandra, Yonah Cho, Matthew S. Rogers