Abstract: A silicon semiconductor wafer is transported into a chamber, and preheating of the semiconductor wafer is started in a nitrogen atmosphere by irradiation with light from halogen lamps. When the temperature of the semiconductor wafer reaches a predetermined switching temperature in the course of the preheating, oxygen gas is supplied into the chamber to change the atmosphere within the chamber from the nitrogen atmosphere to an oxygen atmosphere. Thereafter, a front surface of the semiconductor wafer is heated for an extremely short time period by flash irradiation. Oxidation is suppressed when the temperature of the semiconductor wafer is relatively low below the switching temperature, and is caused after the temperature of the semiconductor wafer becomes relatively high. As a result, a dense, thin oxide film having good properties with fewer defects at an interface with a silicon base layer is formed on the front surface of the semiconductor wafer.

Abstract: Methods for forming a semiconductor structure including a silicon (Si) containing layer or a silicon germanium (SiGe) layer are provided. The methods include depositing a protective barrier (e.g., liner) layer over the semiconductor structure, forming a flowable dielectric layer over the liner layer, and exposing the flowable dielectric layer to high pressure steam. A cluster system includes a first deposition chamber configured to form a semiconductor structure, a second deposition chamber configured to perform a liner deposition process to form a liner layer, a third deposition chamber configured to form a flowable dielectric layer over the liner layer, an annealing chamber configured to expose the flowable oxide layer to high pressure steam.

Abstract: Embodiments described and discussed herein provide methods for depositing silicon nitride materials by vapor deposition, such as by flowable chemical vapor deposition (FCVD), as well as for utilizing new silicon-nitrogen precursors for such deposition processes. The silicon nitride materials are deposited on substrates for gap fill applications, such as filling trenches formed in the substrate surfaces. In one or more embodiments, the method for depositing a silicon nitride film includes introducing one or more silicon-nitrogen precursors and one or more plasma-activated co-reactants into a processing chamber, producing a plasma within the processing chamber, and reacting the silicon-nitrogen precursor and the plasma-activated co-reactant in the plasma to produce a flowable silicon nitride material on a substrate within the processing chamber. The method also includes treating the flowable silicon nitride material to produce a solid silicon nitride material on the substrate.

Abstract: Methods and systems relating to processes for treating a silicon nitride film on a workpiece including supporting the workpiece in a chamber, introducing an amine gas into the chamber and establishing a pressure of at least 5 atmospheres, and exposing the silicon nitride film on the workpiece to the amine gas while the pressure in the chamber is at least 5 atmospheres.

Abstract: Embodiments disclosed herein relate generally to forming a gate layer in high aspect ratio trenches using a cyclic deposition-etch process. In an embodiment, a method for semiconductor processing is provided. The method includes performing a first deposition process to form a conformal film over a bottom surface and along sidewall surfaces of a feature on a substrate. The method includes performing an etch process to remove a portion of the conformal film. The method includes repeating the first deposition process and the etch process to fill the feature with the conformal film. The method includes exposing the conformal film to ultraviolet light.

Abstract: A vapor deposition apparatus includes an exhaust regulator provided in an exhaust pipe to regulate exhaust of the reaction chamber and including: a hollow frustum upstream baffle having a larger first opening near a reaction chamber than a second opening near an exhaust device; and a hollow frustum downstream baffle provided near the exhaust device with respect to the upstream baffle and having a larger third opening near the reaction chamber than a fourth opening near the exhaust device. The upstream baffle and downstream baffle are designed so that B/A and C/A are 0.33 or less, at least one of B/A and C/A is 0.26 or less, and (B+C)/A is 0.59 or less, where an inner diameter of the exhaust pipe and diameters of the first and third openings are A, a diameter of the second opening is B and a diameter of the fourth opening is C.

Abstract: A manufacturing method of a semiconductor device includes generating hydrogen radicals by plasma excitation of hydrogen gas and exposing a surface of a substrate on which silicon and metal are exposed to a reducing atmosphere created with the hydrogen radicals, and generating hydrogen radicals and hydroxyl radicals by plasma excitation of a mixed gas of hydrogen gas and oxygen-containing gas and oxidizing the silicon exposed on the surface of the substrate by exposing the surface of the substrate to the hydrogen radicals and hydroxyl radicals to obtain the substrate on which the metal and oxidized silicon are formed.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an isolation trench between two fin structures on an integrated circuit substrate, forming a flowable film in the isolation trench using a flowable chemical vapor deposition process, and annealing the flowable film to form a silicon oxide dielectric layer in the isolation trench. The annealing is performed at a temperature of less than about 200° C. with a process gas including N2 and H2O2.

Abstract: A substrate processing apparatus is disclosed. The substrate processing apparatus includes a process chamber configured to accommodate a substrate; a gas supply unit configured to supply a process gas into the process chamber; a lid member configured to block an end portion opening of the process chamber; an end portion heating unit installed around a side wall of an end portion of the process chamber; and a thermal conductor installed on a surface of the lid member in an inner side of the process chamber, and configured to be heated by the end portion heating unit.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: Disclosed a method for manufacturing an oxide layer, applicable to a manufacture procedure of a field oxide layer of a CMOS transistor in the field of semiconductor manufacturing, the method includes: injecting a first gas satisfying a first predetermined condition into a processing furnace in which a first CMOS transistor semi-finished product formed with an N-well and a P-well is placed, and dry-oxidizing the first CMOS transistor semi-finished product into a second CMOS transistor semi-finished product; and injecting a second gas satisfying a second predetermined condition different from the first predetermined condition into the processing furnace, and wet-oxidizing the second CMOS transistor semi-finished product into a third CMOS transistor semi-finished product.

Abstract: A process of manufacturing the gate oxide layer, which uses the wet oxidation by deuterium to form gate oxide layer, wherein the nitriding treatment is applied to formed gate oxide layer by high temperature annealing process, the stable Si-D bonds is formed on surface of the gate oxide layer to reduce silicon dangling bonds, which reduce the defect of the gate oxide interface and lower the interface defect density of the gate oxide layer and the charge density effectively to avoid NBTI, is provided.

Abstract: A method of forming a conductive contact landing pad and a transistor includes forming first and second spaced-apart active regions in a semiconducting substrate, forming a layer of gate insulation material on the first and second active regions, and performing an etching process to remove the layer of gate insulation material formed on the second active region so as to thereby expose the second active region. The method further includes performing a common process operation to form a gate electrode structure above the layer of gate insulation material on the first active region for the transistor and the conductive contact landing pad that is conductively coupled to the second active region, and forming a contact to the conductive contact landing pad.

Abstract: Methods for improving selective oxidation of polysilicon against silicon nitride in a process chamber are provided herein. In some embodiments, a method of selectively oxidizing a substrate disposed within a process chamber includes exposing a substrate having an exposed polysilicon layer and an exposed silicon nitride layer to a hydrogen-containing gas; heating the substrate to a process temperature of at least about 850 degrees Celsius; adding an oxygen containing gas to the process chamber while maintaining the substrate at the process temperature to create a mixture of the hydrogen-containing gas and the oxygen-containing gas; and exposing the substrate to the mixture while at the process temperature to selectively form an oxide layer atop the polysilicon layer substantially without forming an oxide layer atop the silicon nitride layer.

Abstract: Oxygen is selectively removed from metal-containing materials in a partially-fabricated integrated circuit. In some embodiments, the partially-fabricated integrated circuit has exposed silicon and metal-containing materials, e.g., as part of a transistor. The silicon and metal-containing material are oxidized. Oxygen is subsequently removed from the metal-containing material by an anneal in an atmosphere containing a reducing agent. Advantageously, the silicon oxide formed by the silicon oxidation is maintained while oxygen is removed from the metal-containing material, thereby leaving a high quality metal-containing material along with silicon oxide.

Abstract: A silicon oxide film forming method includes performing a set one or more times, the set including: a standby process in which a workpiece is accommodated into and recovered from a boat; a load process in which the workpiece accommodated in the boat is loaded into a reaction chamber; a silicon oxide film formation process in which a silicon oxide film is formed on the workpiece accommodated within the reaction chamber; and an unload process in which the workpiece having the silicon oxide film is unloaded from the reaction chamber. In at least one of the unload process, the standby process and the load process, a gas containing water vapor is supplied into the reaction chamber while an interior of the reaction chamber is heated.

Abstract: One device herein includes first and second spaced-apart active regions, a transistor formed in and above the first active region, wherein the transistor has a gate electrode, a conductive contact landing pad that is coupled to the second active region, wherein the contact landing pad is made of the same conductive material as the gate electrode, and a contact that is coupled to the contact landing pad. One method herein includes forming first and second spaced-apart active regions, forming a layer of gate insulation material on the active regions, performing an etching process to remove the gate insulation material formed on the second active region, performing a common process operation to form a gate electrode structure above the gate insulation material on the first active region and the contact landing pad that is conductively coupled to the second active region and forming a contact to the contact landing pad.

Abstract: A dry etch method, apparatus, and system for etching a high-k material comprises sequentially contacting the high-k material with a vapor phase reducing agent, and a volatilizing etchant in a cyclical process. In some preferred embodiments, the reducing agent and/or volatilizing etchant is plasma activated. Control over etch rate and/or selectivity are improved by the pulsed process, where, in some embodiments, each step in the cyclical process has a self-limited extent of etching. Embodiments of the method are useful in the fabrication of integrated devices, as well as for cleaning process chambers.

Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen.

Abstract: In one embodiment, a method of manufacturing a semiconductor device includes sequentially forming a first insulator, a second insulator, and a sacrificial layer on a semiconductor substrate, and forming plural core materials from the sacrificial layer and the second insulator. The method further includes forming first and second interconnects on side surfaces of each core material to form plural first interconnects and plural second interconnects alternately, each first interconnect having a first side surface in contact with a core material and a second side surface positioned on an opposite side of the first side surface, and each second interconnect having a third side surface in contact with a core material and a fourth side surface positioned on an opposite side of the third side surface. The method further includes removing the sacrificial layer so that the second insulator remains, after the first and second interconnects are formed.

Abstract: Oxidation methods and resulting structures including providing an oxide layer on a substrate and then reoxidizing the oxide layer by vertical ion bombardment of the oxide layer in an atmosphere containing at least one oxidant. The oxide layer may be provided over diffusion regions, such as source and drain regions, in a substrate. The oxide layer may overlie the substrate and is proximate a gate structure on the substrate. The at least one oxidant may be oxygen, water, ozone, or hydrogen peroxide, or a mixture thereof. These oxidation methods provide a low-temperature oxidation process, less oxidation of the sidewalls of conductive layers in the gate structure, and less current leakage to the substrate from the gate structure.

Abstract: Techniques are provided for manufacturing a light-emitting device having high internal quantum efficiency, consuming less power, having high luminance, and having high reliability. The techniques include forming a conductive light-transmitting oxide layer comprising a conductive light-transmitting oxide material and silicon oxide, forming a barrier layer in which density of the silicon oxide is higher than that in the conductive light-transmitting oxide layer over the conductive light-transmitting oxide layer, forming an anode having the conductive light-transmitting oxide layer and the barrier layer, heating the anode under a vacuum atmosphere, forming an electroluminescent layer over the heated anode, and forming a cathode over the electroluminescent layer. According to the techniques, the barrier layer is formed between the electroluminescent layer and the conductive light-transmitting oxide layer.

Abstract: The present invention relates generally to semiconductor wafer fabrication and more particularly but not exclusively to advanced process control methodologies for controlling oxide formation using pressure. The present invention, in one or more implementations, includes a pressure stabilization system to dynamically adjust scavenger pressure in a furnace during wafer fabrication in relation to a pressure formation range, value, or one or more pressure indicators in a wafer fabrication process.

Abstract: A method for producing a SiGe stressor with high Ge concentration is provided. The method includes providing a semiconductor substrate with a source area, a drain area, and a channel in between; depositing the first SiGe film layer on the source area and/or the drain area; performing a low temperature thermal oxidation, e.g., a high water vapor pressure wet oxidation, to form an oxide layer at the top of the first SiGe layer and to form the second SiGe film layer with high Ge percentage at the bottom of the first SiGe film layer without Ge diffusion into the semiconductor substrate; performing a thermal diffusion to form the SiGe stressor from the second SiGe film layer, wherein the SiGe stressor provides uniaxial compressive strain on the channel; and removing the oxide layer. A Si cap layer can be deposited on the first SiGe film layer prior to performing oxidation.

Abstract: A method of creating insulating layers on different semiconductor materials includes providing a substrate having disposed thereon a first material and a second material, the second material having a chemical composition different from the first material; non-epitaxially depositing a continuous sacrificial layer of approximately constant thickness onto the first material and the second material, and then converting the sacrificial layer into a layer consisting essentially of SiO2 without oxidizing more than 10 angstroms into the second material. A structure includes a silicon nitride film disposed conformally on a silicon layer and a silicon germanium layer; a SiO2 layer is disposed on the silicon nitride film.

Abstract: An arrangement for measuring process parameters within a processing chamber is provided. The arrangement includes a probe arrangement disposed in an opening of an upper electrode. Probe arrangement includes a probe head, which includes a head portion and a flange portion. The arrangement also includes an o-ring disposed between the upper electrode and the flange portion. The arrangement further includes a spacer made of an electrically insulative material positioned between the head portion and the opening of the upper electrode to prevent the probe arrangement from touching the upper electrode. The spacer includes a disk portion configured for supporting an underside of the flange portion. The spacer also includes a hollow cylindrical portion configured to encircle the head portion. The spacer forms a right-angled path between the o-ring and an opening to the processing chamber to prevent direct line-of-sight path between the o-ring and the opening to the processing chamber.

Abstract: A method of depositing a film with a target conformality on a patterned substrate, includes: depositing a first film on a convex pattern and a bottom surface; and depositing a second film on the first film, thereby forming an integrated film having a target conformality, wherein one of the first and second films is a conformal film which is non-flowable when being deposited and has a conformality of about 80% to about 100%, and the other of the first and second films is a flowable film which is flowable when being deposited.

Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.

Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.

Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate oxidizing species containing oxygen, and oxidizing the element-containing layer by the oxidizing species; wherein the hydrogen-containing gas is supplied into the process vessel together with the source gas in step (a).

Abstract: With a recent shrinking semiconductor process, insulating layers formed between interconnect layers are becoming thin. To avoid parasitic capacitance between them, materials of a low dielectric constant have been used for an insulating layer in a multilevel interconnect. Low-k materials, however, have low strength compared with the conventional insulating layers. Porous low-k materials are structurally fragile. The invention therefore provides a manufacturing method of a semiconductor device having a multilevel interconnect layer including a low-k layer. According to the method, in a two-step cutting system dicing in which after formation of a groove in a semiconductor water with a tapered blade, the groove is divided with a straight blade thinner than the groove width, the multilevel interconnect layer portion is cut while being covered with a tapered face and then the wafer is separated with a thin blade which is not brought into contact with the multilevel interconnect layer portion.

Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.

Abstract: Provided is a method of manufacturing a semiconductor device.

Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.

Abstract: Methods of performing a wet oxidation process on a silicon containing dielectric material filling within trenches or vias defined within a substrate are provided. In one embodiment, a method of forming a dielectric material on a substrate includes forming a dielectric material on a substrate by a flowable CVD process, curing the dielectric material disposed on the substrate, performing a wet oxidation process on the dielectric material disposed on the substrate, and forming an oxidized dielectric material on the substrate.

Abstract: Methods of filling cavities or trenches. More specifically, methods of filling a cavity or trench in a semiconductor layer are provided. The methods include depositing a first dielectric layer into the trench by employing a conformal deposition process. Next, the first dielectric layer is etched to create a recess in the trench within the first dielectric layer. The recesses are then filled with a second dielectric layer by employing a high density plasma deposition process. The techniques may be particularly useful in filling cavities and trenches having narrow widths and/or high aspect ratios.

Abstract: Manufacturing of a charge trap type memory device can include forming a tunnel insulating layer on a substrate. A charge-trapping layer can be formed on the tunnel insulating layer. A blocking layer can be formed on the charge-trapping layer. Gate electrodes can be formed on the blocking layer and divided by a trench. A portion of the charge-trapping layer aligned with the trench may be converted into a charge-blocking pattern with a vertical side profile by an anisotropic oxidation process.

Abstract: The invention includes methods of forming semiconductor constructions in which a single etch is utilized to penetrate through a titanium-containing layer and partially into a silicon-containing layer beneath the titanium-containing layer. The etch can utilize CH2F2. The silicon-containing layer can contain an n-type doped region and a p-type doped region. In some methods, the silicon-containing layer can contain an n-type doped region laterally adjacent a p-type doped region, and the processing can be utilized to form a transistor gate containing n-type doped silicon simultaneously with the formation of a transistor gate containing p-type doped silicon.

Abstract: In a manufacturing method of a thin film transistor (1), the oxide film forming step is performed whereby: a process-target substrate (2) having a surface on which a gate oxide film (4) should be formed is immersed in an oxidizing solution containing an active oxidizing species; and a gate oxide film (4) is formed through direct oxidation of polycrystalline silicon (51) on the process-target substrate (2). With this step, a silicon dioxide film (42) is formed while growing a silicon dioxide film (41) on the process-target substrate 2. Accordingly, the interface between the polycrystalline silicon (51) and the gate oxide film (4) is kept clean. The gate oxide film (4) is uniformly formed with excellent quality in insulation tolerance and other properties. Therefore, the thin film transistor (1) contains a high quality oxide film with excellent insulation tolerance and other properties which can be formed at low temperature.

Abstract: Disclosed is a method of manufacturing a semiconductor device formed by laminating a capacitor including a bottom metal electrode, a capacitive insulating film, and an upper metal electrode. When the capacitive insulating film is formed by performing a first step of forming a first dielectric layer on the bottom metal electrode by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric; and a second step of forming a second dielectric layer on the first dielectric layer by a vapor phase film forming method using a precursor gas that contains constituent elements of a dielectric, a film forming temperature in the first step is set so as to be lower than a film forming temperature in the second step.

Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.

Abstract: One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.

Abstract: A semiconductor substrate having on its surface an electrode of a semiconductor device and a pattern unit is prepared. A copper plate is formed provided with a first principle surface having a bump and a second principle surface, opposite to the first principle surface, having a trench. By adjusting the position of the copper plate so that a pattern unit and the corresponding trench have a predetermined positional relation, the bump and the electrode are aligned, the first principle surface of the copper plate and a semiconductor substrate are pressure-bonded via an insulating layer, and the bump and the electrode become connected electrically while the bump penetrating the insulating layer. A predetermined rewiring pattern is formed on the side of the second principle surface.

Abstract: An oxide film formation method comprises steps of: generating a plasma from a gas mixture containing an inert gas and an oxidizing gas whose mixing ratio to the inert gas is higher than 0, and is 0.007 or lower; and forming an oxide film on a surface of a silicon substrate by using the plasma.

Abstract: Methods and apparatus are provided. An isolation region is formed by lining a trench formed in a substrate with a first dielectric layer by forming the first dielectric layer adjoining exposed substrate surfaces within the trench using a high-density plasma process, forming a layer of spin-on dielectric material on the first dielectric layer so as to fill a remaining portion of the trench, and densifying the layer of spin-on dielectric material.

Abstract: Methods of performing a wet oxidation process on a silicon containing dielectric material filling within trenches or vias defined within a substrate are provided. In one embodiment, a method of forming a dielectric material on a substrate includes forming a dielectric material on a substrate by a flowable CVD process, curing the dielectric material disposed on the substrate, performing a wet oxidation process on the dielectric material disposed on the substrate, and forming an oxidized dielectric material on the substrate.

Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.

Abstract: A semiconductor device having a silicon oxide/silicon nitride/silicon oxide (“ONO”) structure is formed by providing a first silicon oxide layer and a silicon nitride layer over a substrate having a memory region and a logic device region; patterning the first silicon oxide layer and the silicon nitride layer to define bottom oxide and silicon nitride portions of partially completed ONO stacks and to expose the substrate in the logic device regions; performing a rapid thermal annealing process in the presence of a radical oxidizing agent to form concurrently a second silicon oxide layer on the exposed surface of the silicon nitride layer and a gate oxide layer over the substrate; and depositing a conductive layer over the completed ONO stacks and the gate oxide. The invention is employed in manufacture of, for example, memory devices having and peripheral logic devices and memory cells including ONO structures.

Abstract: Methods of this invention relate to filling gaps on substrates with a solid dielectric material by forming a flowable film in the gap. The flowable film provides consistent, void-free gap fill. The film is then converted to a solid dielectric material. In this manner gaps on the substrate are filled with a solid dielectric material. According to various embodiments, the methods involve reacting a dielectric precursor with an oxidant to form the dielectric material. In certain embodiments, the dielectric precursor condenses and subsequently reacts with the oxidant to form dielectric material. In certain embodiments, vapor phase reactants react to form a condensed flowable film.

Abstract: There is provided a substrate processing apparatus equipped with a metallic component, with at least a part of its metallic surface exposed to an inside of a processing chamber and subjected to baking treatment at a pressure less than atmospheric pressure. As a result of this baking treatment, a film which does not react with various types of reactive gases, and which can block the out diffusion of metals, is formed on the surface of the above-mentioned metallic component.