Oxidation Patents (Class 438/770)
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Publication number: 20130178071Abstract: Disclosed is a method of forming a thermal oxide film on a silicon single crystal wafer, which includes throwing the silicon single wafer into a heat treatment furnace; elevating temperature of the heat treatment furnace up to a temperature T1 where a thermal oxide film is formed to form a thermal oxide film having a thickness d1; subsequently lowering the temperature of the heat treatment furnace down to a temperature lower than the temperature T1; and thereafter elevating the temperature of the heat treatment furnace up to a temperature T2 higher than the temperature T1 to additionally form a thermal oxide film having a thickness d2 thicker than the thickness d1. Thus, there is provided a thermal oxide film formation method to suppress occurrence of slip dislocation and/or crack of the silicon single wafer during formation of the thermal oxide film.Type: ApplicationFiled: October 6, 2011Publication date: July 11, 2013Applicant: SHIN-ETSU HANDOTAI CO., LTD.Inventors: Hiroyuki Takahashi, Kazuhiko Yoshida
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Patent number: 8470187Abstract: A method of depositing a film with a target conformality on a patterned substrate, includes: depositing a first film on a convex pattern and a bottom surface; and depositing a second film on the first film, thereby forming an integrated film having a target conformality, wherein one of the first and second films is a conformal film which is non-flowable when being deposited and has a conformality of about 80% to about 100%, and the other of the first and second films is a flowable film which is flowable when being deposited.Type: GrantFiled: November 5, 2010Date of Patent: June 25, 2013Assignee: ASM Japan K.K.Inventor: Jeongseok Ha
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Patent number: 8455293Abstract: A method for processing solar cells comprising: providing a vertical furnace to receive an array of mutually spaced circular semiconductor wafers for integrated circuit processing; composing a process chamber loading configuration for solar cell substrates, wherein a size of the solar cell substrates that extends along a first surface to be processed is smaller than a corresponding size of the circular semiconductor wafers, such that multiple arrays of mutually spaced solar cell substrates can be accommodated in the process chamber, loading the solar cell substrates into the process chamber; subjecting the solar cell substrates to a process in the process chamber.Type: GrantFiled: November 6, 2012Date of Patent: June 4, 2013Assignee: ASM International N.V.Inventors: Chris G. M. de Ridder, Klaas P. Boonstra, Adriaan Garssen, Frank Huussen
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Patent number: 8445352Abstract: A problem in the conventional technique is that metal contamination on a silicon carbide surface is not sufficiently removed in a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate. Accordingly, there is a high possibility that the initial characteristics of a manufactured silicon carbide semiconductor device are deteriorated and the yield rate is decreased. Further, it is conceivable that the metal contamination has an adverse affect even on the long-term reliability of a semiconductor device. In a manufacturing method of a semiconductor device using a monocrystalline silicon carbide substrate, there is applied a metal contamination removal process, on a silicon carbide surface, including a step of oxidizing the silicon carbide surface and a step of removing a film primarily including silicon dioxide formed on the silicon carbide surface by the step.Type: GrantFiled: November 11, 2008Date of Patent: May 21, 2013Assignee: Hitachi, Ltd.Inventors: Natsuki Yokoyama, Tomoyuki Someya
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Patent number: 8435906Abstract: Methods and apparatus for forming an oxide layer on a semiconductor substrate are disclosed. In one or more embodiments, plasma oxidation is used to form a conformal oxide layer by controlling the temperature of the semiconductor substrate at below about 100° C. Methods for controlling the temperature of the semiconductor substrate according to one or more embodiments include utilizing an electrostatic chuck and a coolant and gas convection.Type: GrantFiled: January 22, 2010Date of Patent: May 7, 2013Assignee: Applied Materials, Inc.Inventors: Agus S. Tjandra, Christopher S. Olsen, Johanes F. Swenberg, Yoshitaka Yokota
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Publication number: 20130109197Abstract: A method of forming a silicon oxide film includes forming a seed layer on a base, forming a silicon film on the seed layer, and forming the silicon oxide film on the base by oxidizing the silicon film and the seed layer.Type: ApplicationFiled: October 26, 2012Publication date: May 2, 2013Applicant: TOKYO ELECTRON LIMITEDInventor: TOKYO ELECTRON LIMITED
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Patent number: 8431494Abstract: A film formation method of forming a silicon oxide film on a surface of an object to be processed in a process chamber includes absorbing a seed gas comprising a silane-based gas on the surface of the object to be processed by supplying the seed gas into the process chamber, forming a silicon film having an impurity by supplying a silicon-containing gas as a material gas, and an addition gas including the impurity into the process chamber, and oxidizing the silicon film to convert the silicon film into the silicon oxide film. Accordingly, the silicon oxide film having the high density and the high stress is formed on the surface of the object to be processed.Type: GrantFiled: June 20, 2011Date of Patent: April 30, 2013Assignee: Tokyo Electron LimitedInventors: Hiroki Murakami, Kazuhide Hasebe, Kazuya Yamamoto, Toshihiko Takahashi, Daisuke Suzuki
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Patent number: 8420553Abstract: A manufacturing method of a semiconductor device, which includes the steps of forming a gate electrode layer over a substrate having an insulating surface, forming a gate insulating layer over the gate electrode layer, forming an oxide semiconductor layer over the gate insulating layer, forming a source electrode layer and a drain electrode layer over the oxide semiconductor layer, forming an insulating layer including oxygen over the oxide semiconductor layer, the source electrode layer, and the drain electrode layer, and after formation of an insulating layer including hydrogen over the insulating layer including oxygen, performing heat treatment so that hydrogen in the insulating layer including hydrogen is supplied to at least the oxide semiconductor layer.Type: GrantFiled: December 2, 2010Date of Patent: April 16, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8410002Abstract: An object is to provide a semiconductor device with a novel structure and favorable characteristics. A semiconductor device includes an oxide semiconductor layer, a source electrode and a drain electrode electrically connected to the oxide semiconductor layer, a gate insulating layer covering the oxide semiconductor layer, the source electrode, and the drain electrode, and a gate electrode over the gate insulating layer. The source electrode and the drain electrode include an oxide region formed by oxidizing a side surface thereof. Note that the oxide region of the source electrode and the drain electrode is preferably formed by plasma treatment with a high frequency power of 300 MHz to 300 GHz and a mixed gas of oxygen and argon.Type: GrantFiled: November 12, 2010Date of Patent: April 2, 2013Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventors: Shunpei Yamazaki, Jun Koyama
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Patent number: 8404601Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of: (a) introducing hydrogen and oxygen on a SiC substrate; and (b) subjecting the hydrogen and the oxygen to a combustion reaction on the SiC substrate to form a gate oxide film being a silicon oxide film on a surface of the SiC substrate by the combustion reaction.Type: GrantFiled: June 12, 2012Date of Patent: March 26, 2013Assignee: Mitsubishi Electric CorporationInventor: Kazuo Kobayashi
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Patent number: 8395902Abstract: An electronic apparatus includes an electronic component electrically connected to a substrate positioned beneath the electronic component. A member includes a plurality of decoupling capacitors having different voltages, and the decoupling capacitors are electrically connected to the electronic component. A plurality of voltage planes in the member are electrically connected to the decoupling capacitors. The decoupling capacitors, via the voltage planes in the member, provide different voltages to the voltage planes and thus the electronic component.Type: GrantFiled: May 21, 2008Date of Patent: March 12, 2013Assignee: International Business Machines CorporationInventor: John U. Knickerbocker
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Publication number: 20130059451Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate an atomic oxygen, and oxidizing the element-containing layer by the atomic oxygen.Type: ApplicationFiled: November 1, 2012Publication date: March 7, 2013Applicant: HITACHI KOKUSAI ELECTRIC, INC.Inventor: Hitachi Kokusai Electric, Inc.
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Patent number: 8389412Abstract: The invention relates to a finishing method for a silicon-on-insulator (SOI) substrate that includes an oxide layer buried between an active silicon layer and a support layer of silicon. The method includes applying the following steps in succession: a first rapid thermal annealing (RTA) of the SOI substrate; a sacrificial oxidation of the active silicon layer of the substrate conducted to remove a first oxide thickness; a second RTA of the substrate; and a second sacrificial oxidation of the active silicon layer conducted to remove a second oxide thickness that is thinner than the first oxide thickness.Type: GrantFiled: March 17, 2010Date of Patent: March 5, 2013Assignee: SoitecInventors: Walter Schwarzenbach, Sébastien Kerdiles, Patrick Reynaud, Ludovic Ecarnot, Eric Neyret
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Patent number: 8372761Abstract: A silicon oxide film is formed in a processing chamber of a plasma processing apparatus by performing oxidation process, by using plasma to a processing object having a patterned irregularity, wherein the plasma is generated while high-frequency power is supplied to a mount table under the conditions that the oxygen content in a process gas is not less than 0.5% and less than 10% and the process pressure is 1.3 to 665 Pa.Type: GrantFiled: March 28, 2008Date of Patent: February 12, 2013Assignee: Tokyo Electron LimitedInventors: Yoshiro Kabe, Takashi Kobayashi, Toshihiko Shiozawa, Junichi Kitagawa
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Publication number: 20130034941Abstract: Methods of forming a semiconductor structure include providing an insulation layer on a semiconductor layer and diffusing cesium ions into the insulation layer from a cesium ion source outside the insulation layer. A MOSFET including an insulation layer treated with cesium ions may exhibit increased inversion layer mobility.Type: ApplicationFiled: August 3, 2011Publication date: February 7, 2013Inventors: Sarit Dhar, Sei-Hyung Ryu, Anant Agarwal, John Robert Williams
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Patent number: 8367557Abstract: A method of manufacturing a semiconductor device, the method comprising: forming an oxide film on a substrate by alternately repeating: (a) forming an element-containing layer on the substrate by supplying a source gas containing an element into a process vessel accommodating the substrate; and (b) changing the element-containing layer to an oxide layer by supplying an oxygen-containing gas and a hydrogen-containing gas into the process vessel having an inside pressure lower than atmospheric pressure, reacting the oxygen-containing gas with the hydrogen-containing gas to generate oxidizing species containing oxygen, and oxidizing the element-containing layer by the oxidizing species; wherein the hydrogen-containing gas is supplied into the process vessel together with the source gas in step (a).Type: GrantFiled: October 28, 2009Date of Patent: February 5, 2013Assignee: Hitachi Kokosai Electric, Inc.Inventors: Naonori Akae, Yoshiro Hirose, Yushin Takasawa, Yosuke Ota
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Patent number: 8357619Abstract: A silicon-containing insulating film is formed on a target substrate by CVD, in a process field to be selectively supplied with a first process gas including di-iso-propylaminosilane gas and a second process gas including an oxidizing gas or nitriding gas. The film is formed by performing a plurality of times a cycle alternately including first and second steps. The first step performs supply of the first process gas, thereby forming an adsorption layer containing silicon on a surface of the target substrate. The second performs supply of the second process gas, thereby oxidizing or nitriding the adsorption layer on the surface of the target substrate. The second step includes an excitation period of supplying the second process gas to the process field while exciting the second process gas by an exciting mechanism.Type: GrantFiled: March 4, 2011Date of Patent: January 22, 2013Assignee: Tokyo Electron LimitedInventors: Kazuhide Hasebe, Shigeru Nakajima, Jun Ogawa
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Publication number: 20130017689Abstract: Novel silicon dioxide and silicon nitride deposition methods are generally disclosed. In one embodiment, the method includes depositing silicon on the surface of a substrate having a temperature of between about 65° C. and about 350° C. The heated substrate is exposed to a silicon source that is substantially free from an oxidizing agent. The silicon on the surface is then oxidized with an oxygen source that is substantially free from a silicon source. As a result of oxidizing the silicon, a silicon oxide layer forms on the surface of the substrate. Alternatively, or in additionally, a nitrogen source can be provided to produce silicon nitride on the surface of the substrate.Type: ApplicationFiled: May 7, 2007Publication date: January 17, 2013Inventors: Asif Khan, Vinod Adivarahan
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Patent number: 8349743Abstract: Disclosed is a method for fabricating a light emitting device. The method includes forming an oxide including gallium aluminum over a gallium oxide substrate, forming a nitride including gallium aluminum over the oxide including gallium aluminum and forming a light emitting structure over the nitride including gallium aluminum.Type: GrantFiled: January 12, 2012Date of Patent: January 8, 2013Assignee: LG Innotek Co., Ltd.Inventor: Yong Tae Moon
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Patent number: 8343879Abstract: A method for fabricating a semiconductor device includes forming an isolation layer which defines an active region in a substrate, forming recess patterns in the active region and the isolation layer, baking a surface of the recess pattern by conducting an annealing process and forming a gate dielectric layer over a surface of the recess pattern by conducting an oxidation process.Type: GrantFiled: June 29, 2010Date of Patent: January 1, 2013Assignee: Hynix Semiconductor Inc.Inventors: Se-Aug Jang, Eun-Jeong Kim, Eun-Ha Lee
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Publication number: 20120329230Abstract: A method of fabricating a silicon-containing oxide layer that includes providing a chemical oxide layer on a surface of a semiconductor substrate, removing the chemical oxide layer in an oxygen-free environment at a temperature of 1000° C. or greater to provide a bare surface of the semiconductor substrate, and introducing an oxygen-containing gas at a flow rate to the bare surface of the semiconductor substrate for a first time period at the temperature of 1000° C. The temperature is then reduced to room temperature during a second time period while maintaining the flow rate of the oxygen containing gas to provide a silicon-containing oxide layer having a thickness ranging from 0.5 ? to 10 ?.Type: ApplicationFiled: June 21, 2011Publication date: December 27, 2012Applicants: GLOBALFOUNDRIES INC., INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Michael P. Chudzik, Min Dai, Joseph F. Shepard, JR., Shahab Siddiqui, Jinping Liu
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Patent number: 8338312Abstract: A film formation method includes a film formation process for forming an SiO2 film on a surface of a target object inside a process container by use of an Si source gas and an oxidizing agent, and an oxidation purge process for performing oxidation on films deposited inside the process container while exhausting gas from inside the process container after unloading the target object from the process container, wherein the film formation process and the oxidation purge process are alternately repeated a plurality of times without, interposed therebetween, a process for removing the films deposited inside the process container.Type: GrantFiled: February 10, 2011Date of Patent: December 25, 2012Assignee: Tokyo Electron LimitedInventors: Jun Sato, Eiji Kikama, Masataka Toiya, Tetsuya Shibata
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Patent number: 8334215Abstract: A substrate can be appropriately oxidized, while oxidation of the substrate can be suppressed. The present invention includes a step of generating mixed plasma by causing a mixed gas of hydrogen (H2) gas and oxygen(O2) or oxygen/containing gas supplied to a processing chamber to form a plasma discharge, and processing the starting substrate by the mixed plasma; and a step of generating hydrogen plasma by causing hydrogen (H2) gas supplied to the processing chamber to form a plasma discharge, and processing the substrate by the hydrogen plasma.Type: GrantFiled: February 4, 2009Date of Patent: December 18, 2012Assignee: Hitachi Kokusai Electric Inc.Inventors: Tatsushi Ueda, Tadashi Terasaki, Unryu Ogawa, Akito Hirano
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Patent number: 8334222Abstract: A processing method of a semiconductor wafer is provided. The method comprising the steps of: removing at least part of oxide film from a surface of the semiconductor wafer; removing liquid from the surface; and providing at least partial oxide film on the surface by applying an oxidizing gas wherein a gas flow of the oxidizing gas and/or an ambient gas involved by the oxidizing gas is characterized by an unsaturated vapor pressure of the liquid such that the liquid on the surface vaporizes. The above-described steps are conducted in this order.Type: GrantFiled: May 1, 2009Date of Patent: December 18, 2012Assignee: Sumco Techxiv CorporationInventors: Isamu Gotou, Tomonori Kawasaki
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Patent number: 8329598Abstract: Methods of forming a top oxide around a charge storage material layer of a memory cell and methods of improving quality of a top oxide around a charge storage material layer of a memory cell are provided. The method can involve providing a charge storage layer on a semiconductor substrate, a nitride layer on the charge storage layer, and a first poly layer on the nitride layer, and converting at least a portion of the nitride layer to a top oxide. By converting at least a portion of a nitride layer to a top oxide layer, the quality of the resultant top oxide layer can be improved.Type: GrantFiled: June 6, 2011Date of Patent: December 11, 2012Assignee: Spansion LLCInventors: Chungho Lee, Kuo-Tung Chang, Hiroyuki Kinoshita, Huaqiang Wu, Fred Cheung
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Patent number: 8318608Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.Type: GrantFiled: August 25, 2008Date of Patent: November 27, 2012Assignee: Cypress Semiconductor CorporationInventors: Krishnaswamy Ramkumar, Sagy Levy, Jeong Byun
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Patent number: 8309440Abstract: Embodiments described herein provide methods for processing a substrate. One embodiment comprises positioning a substrate in a processing region of a processing chamber, exposing a surface of the substrate disposed in the processing chamber to an oxygen containing gas to form a first oxygen containing layer on the surface, removing at least a portion of the first oxygen containing layer to expose at least a portion of the surface of the substrate, and exposing the surface of the substrate to an oxygen containing gas to form a second oxygen containing layer on the surface.Type: GrantFiled: July 1, 2011Date of Patent: November 13, 2012Assignee: Applied Materials, Inc.Inventors: Errol Antonio C. Sanchez, Johanes Swenberg, David K. Carlson, Roisin L. Doherty
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Patent number: 8304352Abstract: According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.Type: GrantFiled: March 18, 2011Date of Patent: November 6, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Tanaka, Kazuhiro Matsuo, Yoshio Ozawa
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Patent number: 8298949Abstract: A method of forming spacers from a non-silicon oxide, silicon containing spacer layer with horizontal surfaces and sidewall surfaces over a substrate is provided. A plasma oxidation treatment is provided to form a silicon oxide coating over the spacer layer, wherein the silicon oxide coating provides a horizontal coating on the horizontal surfaces and sidewall coatings on the sidewall surfaces of the spacer layer. An anisotropic main etch that selectively etches horizontal surfaces of the spacer layer and silicon oxide coating with respect to sidewall surfaces of the spacer layer and the sidewall coatings of the silicon oxide coating is provided. The spacer layer is etched, wherein the sidewall coatings of the silicon oxide coating protect sidewall surfaces of the spacer layer.Type: GrantFiled: January 7, 2009Date of Patent: October 30, 2012Assignee: Lam Research CorporationInventors: Qinghua Zhong, Sung Cho, Gowri Kamarthy, Linda Braly
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Publication number: 20120270411Abstract: A manufacturing method of a gate dielectric layer is provided. An oxidation treatment is performed to form an oxide layer on a substrate. A nitridation treatment is performed to form a nitride layer on the oxide layer. An annealing treatment is performed in a mixing gas of N2 and O2, where the temperature of the annealing treatment is 900° C. to 950° C., the pressure of the annealing treatment is 5 Torr to 10 Torr, and the content ratio of the N2 to O2 is 0.5 to 0.8.Type: ApplicationFiled: April 25, 2011Publication date: October 25, 2012Applicant: NANYA TECHNOLOGY CORPORATIONInventors: Kuo-Hui Su, Yi-Nan Chen, Hsien-Wen Liu
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Patent number: 8293661Abstract: One embodiment of the present invention is to achieve high mobility in a device using an oxide semiconductor and provide a highly reliable display device. An oxide semiconductor layer including a crystal region in which c-axis is aligned in a direction substantially perpendicular to a surface is formed and an oxide insulating layer is formed over and in contact with the oxide semiconductor layer. Oxygen is supplied to the oxide semiconductor layer by third heat treatment. A nitride insulating layer containing hydrogen is formed over the oxide insulating layer and fourth heat treatment is performed, so that hydrogen is supplied at least to an interface between the oxide semiconductor layer and the oxide insulating layer.Type: GrantFiled: December 2, 2010Date of Patent: October 23, 2012Assignee: Semiconductor Energy Laboratory Co., Ltd.Inventor: Shunpei Yamazaki
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Patent number: 8288826Abstract: A semiconductor-on-insulator structure includes a buried dielectric layer interposed between a base semiconductor substrate and a surface semiconductor layer. The buried dielectric layer comprises an oxide material that includes a nitrogen gradient that peaks at the interface of the buried dielectric layer with at least one of the base semiconductor substrate and surface semiconductor layer. The interface of the buried dielectric layer with the at least one of the base semiconductor substrate and surface semiconductor layer is abrupt, providing a transition in less than about 5 atomic layer thickness, and having less than about 10 angstroms RMS interfacial roughness. A second dielectric layer comprising an oxide dielectric material absent nitrogen may be located interposed between the buried dielectric layer and the surface semiconductor layer.Type: GrantFiled: November 7, 2011Date of Patent: October 16, 2012Assignee: International Business Machines CorporationInventors: Anthony I. Chou, Toshiharu Furukawa, Wilfried Haensch, Zhibin Ren, Dinkar V. Singh, Jeffrey W. Sleight
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Patent number: 8288204Abstract: Methods for fabricating components with precise dimension control are described. One such method includes providing a workpiece including a top layer and a bottom layer of silicon separated by a layer of SiOx, where each of the three layers has about the same length and width, removing edge portions of the top layer, thereby exposing portions of the SiOx layer, etching the exposed portions of the SiOx layer and portions of the SiOx layer disposed between the top layer and bottom layer, thereby forming undercut sections between the top layer and bottom layer, growing a second layer of SiOx having a preselected thickness on the workpiece, depositing metal on the workpiece such that the metal deposited on the top layer is not continuous with the metal deposited on the bottom layer, and removing the bottom layer and a portion of the SiOx layer having a preselected thickness.Type: GrantFiled: August 30, 2011Date of Patent: October 16, 2012Assignee: Western Digital (Fremont), LLCInventors: Lei Wang, Zongrong Liu
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Patent number: 8283261Abstract: A method for fabricating a nonvolatile charge trap memory device is described. The method includes providing a substrate having a charge-trapping layer disposed Thereon. A portion of the charge-trapping layer is then oxidized to form a blocking dielectric layer above the charge-trapping layer by exposing the charge-trapping layer to a radical oxidation process.Type: GrantFiled: May 21, 2008Date of Patent: October 9, 2012Assignee: Cypress Semiconductor CorporationInventor: Krishnaswamy Ramkumar
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Patent number: 8278165Abstract: Methods for fabricating semiconductor devices are provided. The methods include providing a semiconductor substrate having pFET and nFET regions, each having active areas and shallow trench isolation. A hardmask layer is formed overlying the semiconductor substrate. A photoresist layer is provided over the hardmask layer. The phoresist layer is patterned. An exposed portion of the hardmask layer is removed from one of the pFET region and nFET region with the patterned photoresist acting as an etch mask to define a masked region and an unmasked region. An epitaxial silicon layer is formed on the active area in the unmasked region. A protective oxide layer is formed overlying the epitaxial silicon layer. The hardmask layer is removed from the masked region with the protective oxide layer protecting the epitaxial silicon layer during such removal step. The protective oxide layer is removed from the epitaxial silicon layer.Type: GrantFiled: October 12, 2009Date of Patent: October 2, 2012Assignee: GLOBALFOUNDRIES, Inc.Inventors: Rohit Pal, Janice Monzet
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Patent number: 8278175Abstract: Methods for fabricating FET device structures are disclosed. The methods include receiving a fin of a Si based material, and converting a region of the fin into an oxide element. The oxide element exerts pressure onto the fin where a Fin-FET device is fabricated. The exerted pressure induces compressive stress in the device channel of the Fin-FET device. The methods also include receiving a rectangular member of a Si based material and converting a region of the member into an oxide element. The methods further include patterning the member that N fins are formed in parallel, while being abutted by the oxide element, which exerts pressure onto the N fins. Fin-FET devices are fabricated in the compressed fins, which results in compressively stressed device channels. FET devices structures are also disclosed. An FET devices structure has a Fin-FET device with a fin of a Si based material. An oxide element is abutting the fin and exerts pressure onto the fin.Type: GrantFiled: June 10, 2010Date of Patent: October 2, 2012Assignee: International Business Machines CorporationInventors: Kangguo Cheng, Bruce B. Doris, Ali Khakifirooz, Pranita Kulkarni, Ghavam G. Shahidi
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Semiconductor device producing method, substrate producing method and substrate processing apparatus
Patent number: 8268731Abstract: Disclosed is a producing method of a semiconductor device, including: loading a substrate into a reaction tube; oxidizing the substrate under an atmospheric pressure by supplying a plurality of kinds of gases which react with each other and an inert gas into the reaction tube; and unloading, from the reaction tube, the substrate after the oxidizing, wherein in the oxidizing, a flow rate of the inert gas is varied in accordance with a variation of the atmospheric pressure to keep constant a partial pressure of an oxidizing gas or partial pressures of oxidizing gases in the reaction tube, and the flow rate of the inert gas is calculated based on a pre-calculated flow rate of a gas or pre-calculated flow rates of gases produced by reaction of the plurality of gases and a pre-calculated flow rate of a gas which is not consumed by the reaction and which remains or pre-calculated flow rates of gases which are not consumed by the reaction and which remain.Type: GrantFiled: March 30, 2006Date of Patent: September 18, 2012Assignee: Hitatchi Kokusai Electric Inc.Inventors: Naoto Nakamura, Iwao Nakamura, Ryota Sasajima -
Patent number: 8263501Abstract: A silicon dioxide film fabricating process includes the following steps. Firstly, a substrate is provided. A rapid thermal oxidation-in situ steam generation process is performed to form a silicon dioxide film on the substrate. An annealing process is performed to anneal the substrate in a first gas mixture at a temperature in the range of 1000° C. to 1100° C.Type: GrantFiled: December 15, 2010Date of Patent: September 11, 2012Assignee: United Microelectronics Corp.Inventors: Chien-Liang Lin, Yu-Ren Wang, Ying-Wei Yen
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Patent number: 8263451Abstract: A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.Type: GrantFiled: February 26, 2010Date of Patent: September 11, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chien-Chang Su, Tsz-Mei Kwok, Hsien-Hsin Lin, Hsueh-Chang Sung, Yi-Fang Pai, Kuan-Yu Chen
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Patent number: 8252701Abstract: Provided is a method of manufacturing a semiconductor device.Type: GrantFiled: November 18, 2010Date of Patent: August 28, 2012Assignee: Hitachi-Kokusai Electric Inc.Inventors: Ryota Sasajima, Yoshiro Hirose, Yosuke Ota, Naonori Akae, Kojiro Yokozawa
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Patent number: 8252700Abstract: In a method of heat treating a wafer obtained by slicing a silicon single crystal ingot manufactured by the Czochralski method, a rapid heating/cooling heat treatment is carried out by setting a holding time at an ultimate temperature of 1200° C. or more and a melting point of silicon or less to be equal to or longer than one second and to be equal to or shorter than 60 seconds in a mixed gas atmosphere containing oxygen having an oxygen partial pressure of 1.0% or more and 20% or less and argon, and an oxide film having a thickness of 9.1 nm or less or 24.3 nm or more is thus formed on a surface of the silicon wafer.Type: GrantFiled: January 21, 2010Date of Patent: August 28, 2012Assignee: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Kumiko Murayama, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima
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Patent number: 8242030Abstract: A method of electrically activating a structure having one or more graphene layers formed on a silicon carbide layer includes subjecting the structure to an oxidation process so as to form a silicon oxide layer disposed between the silicon carbide layer and a bottommost of the one or more graphene layers, thereby electrically activating the bottommost graphene layer.Type: GrantFiled: September 25, 2009Date of Patent: August 14, 2012Assignee: International Business Machines CorporationInventors: James B. Hannon, Fenton R. McFeely, Satoshi Oida, John J. Yurkas
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Patent number: 8236707Abstract: A method of manufacturing a semiconductor device according to the present invention includes the steps of: (a) introducing hydrogen and oxygen on a SiC substrate; and (b) subjecting the hydrogen and the oxygen to a combustion reaction on the SiC substrate to form a gate oxide film being a silicon oxide film on a surface of the SiC substrate by the combustion reaction.Type: GrantFiled: September 15, 2010Date of Patent: August 7, 2012Assignee: Mitsubishi Electric CorporationInventor: Kazuo Kobayashi
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Patent number: 8236706Abstract: Plasma assisted low temperature radical oxidation is described. The oxidation is selective to metals or metal oxides that may be present in addition to the silicon being oxidized. Selectivity is achieved by proper selection of process parameters, mainly the ratio of H2 to O2 gas. The process window may be enlarged by injecting H2O steam into the plasma, thereby enabling oxidation of silicon in the presence of TiN and W, at relatively low temperatures. Selective oxidation is improved by the use of an apparatus having remote plasma and flowing radicals onto the substrate, but blocking ions from reaching the substrate.Type: GrantFiled: December 12, 2008Date of Patent: August 7, 2012Assignee: Mattson Technology, Inc.Inventors: Bruce W. Peuse, Yaozhi Hu, Paul Janis Timans, Guangcai Xing, Wilfried Lerch, Sing-Pin Tay, Stephen E. Savas, Georg Roters, Zsolt Nenyei, Ashok Sinha
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Publication number: 20120196441Abstract: The present invention relates to a solution and a method for activating the oxidized surface of a substrate, in particular of a semiconducting substrate, for its subsequent coating by a metal layer deposited by the electroless method. According to the invention, this composition contains: A) an activator consisting of one or more palladium complexes; B) a bifunctional organic binder consisting one or more organosilane complexes; C) a solvent system consisting one or more solvents for solubilizing the said activator and the said binder.Type: ApplicationFiled: September 30, 2010Publication date: August 2, 2012Applicant: ALCHIMERInventors: Vincent Mevellec, Dominique Suhr
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Patent number: 8222163Abstract: A recess is usually formed on the sidewall of the trench due to the dry etch. The recess may influence the profile of an element formed in the trench. Therefore, a method of flattening a recess in a substrate is provided. The method includes: first, providing a substrate having a trench therein, wherein the trench has a sidewall comprising a recessed section and an unrecessed section. Then, a recessed section oxidation rate change step is performed to change an oxidation rate of the recessed section. Later, an oxidizing process is performed to the substrate so as to form a first oxide layer on the recessed section, and a second oxide layer on the unrecessed section, wherein the second oxide layer is thicker than the first oxide layer. Finally, the first oxide layer and the second oxide layer are removed to form a flattened sidewall of the trench.Type: GrantFiled: August 6, 2010Date of Patent: July 17, 2012Assignee: Nanya Technology Corp.Inventors: Chao-Wen Lay, Ching-Kai Lin
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Publication number: 20120168895Abstract: A device includes a substrate with a device region on which a transistor is formed. The device region includes active edge regions and an active center region which have different oxidation growth rates. A growth rate modifier (GRM) comprising dopants which modifies oxidation growth rate is employed to produce a gate oxide layer which has a uniform thickness. The GRM may enhance or retard the oxidation growth, depending on the type of dopants used. Fluorine dopants enhance oxidation growth rate while nitrogen dopants retard oxidation growth rate.Type: ApplicationFiled: December 29, 2010Publication date: July 5, 2012Applicant: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: Chunshan YIN, Palanivel BALASUBRAMANIAM, Jae Gon LEE, Elgin QUEK
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Publication number: 20120164844Abstract: A method for forming an oxide film on a carbon film includes the steps of forming a carbon film on an object to be processed; forming an object-to-be-oxidized layer on the carbon film; and forming an oxide film on the object-to-be-oxidized layer while oxidizing the object-to-be-oxidized layer.Type: ApplicationFiled: December 27, 2011Publication date: June 28, 2012Applicant: TOKYO ELECTRON LIMITEDInventors: Akinobu KAKIMOTO, Atsushi ENDO, Kazumi KUBO
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Publication number: 20120139088Abstract: A silicon wafer for preventing a void defect in a bulk region from becoming source of contamination and slip generation in a device process is provided. And a heat-treating method thereof for reducing crystal defects such as COP in a region near the wafer surface to be a device active region is provided. The silicon wafer has a surface region 1 which is a defect-free region and a bulk region 2 including void defect of a polyhedron whose basic shape is an octahedron in which a corner portion of the polyhedron is in the curved shape and an inner-wall oxide film the void defect is removed. The silicon wafer is provided by performing a heat-treating method in which gas to be supplied, inner pressure of spaces and a maximum achievable temperature are set to a predetermined value when subjecting the silicon wafer produced by a CZ method to RTP.Type: ApplicationFiled: May 28, 2010Publication date: June 7, 2012Applicant: Covalent Materials CorporationInventors: Takeshi Senda, Hiromichi Isogai, Eiji Toyoda, Koji Araki, Tatsuhiko Aoki, Haruo Sudo, Koji Izunome, Susumu Maeda, Kazuhiko Kashima, Hiroyuki Saito
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Patent number: 8168508Abstract: A method is provided. The method includes forming a plurality of nanowires on a top surface of a substrate and forming an oxide layer adjacent to a bottom surface of each of the plurality of nanowires, wherein the oxide layer is to isolate each of the plurality of nanowires from the substrate.Type: GrantFiled: December 30, 2008Date of Patent: May 1, 2012Assignee: Intel CorporationInventors: Benjamin Chu-Kung, Uday Shah, Ravi Pillarisetty, Been-Yih Jin, Marko Radosavljevic, Willy Rachmady