In Atmosphere Containing Water Vapor (i.e., Wet Oxidation) Patents (Class 438/773)
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Publication number: 20040063276Abstract: When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.Type: ApplicationFiled: August 20, 2003Publication date: April 1, 2004Inventors: Naoki Yamamoto, Hiroyuki Uchiyama, Norio Suzuki, Eisuke Nishitani, Shin?apos;ichiro Kimura, Kazuyuki Hozawa
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Publication number: 20040058557Abstract: A process for forming and/or modifying dielectric films on semiconductor substrates is disclosed. According to the present invention, a semiconductor wafer is exposed to a process gas containing a reactive component. The temperature to which the semiconductor wafer is heated and the partial pressure of the reactive component are selected so that, sometime during the process, diffusion of the reactive components occurs through the dielectric film to the film/semiconductor substrate interface. Further, diffusion also occurs of semiconductor atoms through the dielectric film to an exterior surface of the film. The process of the present invention has been found well suited to forming and/or modifying very thin dielectric films, such as films having a thickness of less than 8 nm.Type: ApplicationFiled: March 10, 2003Publication date: March 25, 2004Applicant: Mattson Technology, Inc.Inventors: Ignaz Eisele, Alexandra Ludsteck, Jorg Schulze, Zsolt Nenyei, Waltraud Dietl, Georg Roters
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Patent number: 6709990Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a silicon dioxide layer. This silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A second layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.Type: GrantFiled: October 9, 2002Date of Patent: March 23, 2004Assignee: Atmel CorporationInventors: Mark A. Good, Amit S. Kelkar
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Patent number: 6699796Abstract: A single chip pad oxide layer growth process is disclosed. First, a silicon chip is sent into a reaction chamber, which is filled with hydrogen and oxygen. A rapid thermal process is employed to increase the temperature inside the chamber to about 850° C. to 1100° C. to grow a SiO2 layer. The error on the final temperature after the rapid thermal process can be controlled to fluctuate within one to two degrees.Type: GrantFiled: June 14, 2002Date of Patent: March 2, 2004Assignee: Macronix International Co., Ltd.Inventor: Chin-Ta Su
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Publication number: 20040018708Abstract: In a method for manufacturing a semiconductor device having a laminated gate electrode, a phosphorus-doped polysilicon is formed on a gate oxide film. A high-melting metal or a compound of a high-melting metal and silicon is formed on the polysilicon. Phosphorus is doped into the polysilicon so that a concentration of the phosphorus in the polysilicon at an interface between the polysilicon and the gate oxide film is 2×1020 (1/cm3) or less. Then, thermal oxidation is carried out in a wet-hydrogen atmosphere containing water vapor.Type: ApplicationFiled: March 24, 2003Publication date: January 29, 2004Inventors: Kazuo Ogawa, Kiyonori Ohyu, Kensuke Okonogi, Toshihiro Imamura, Keiichi Watanabe, Hiroyuki Ohta
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Patent number: 6673725Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).Type: GrantFiled: April 30, 2001Date of Patent: January 6, 2004Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda
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Patent number: 6667247Abstract: This invention refers to a process for the production of an electrode for electrolytic capacitors made of a conductive substrate (7) onto which a porous layer of aluminum oxide is deposited on both sides in at least two-phase process by vacuum deposition of unstoichiometric aluminum oxide in a reactive atmosphere and a following surface oxidation process by a treatment under reactive plasma as well as a roll-to-roll system for such production and an electrode made by such process.Type: GrantFiled: September 28, 2001Date of Patent: December 23, 2003Assignee: Becromal S.p.A.Inventors: Giovanni Pietro Chiavarotti, Tarcisio Maria Cagnin
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Patent number: 6660613Abstract: A trench isolation in a semiconductor device, and a method for fabricating the same, includes: forming a trench having inner sidewalls for device isolation in a silicon substrate; forming an oxide layer on a surface of the silicon substrate that forms the inner sidewalls of the trench; supplying healing elements to the silicon substrate to remove dangling bonds; and filling the trench with a device isolation layer, thereby forming the trench isolation without dangling bonds causing electrical charge traps.Type: GrantFiled: March 22, 2002Date of Patent: December 9, 2003Assignee: Samsung Electronics Co., Ltd.Inventors: Chul-Sung Kim, Si-Young Choi, Jung-Woo Park, Jong-Ryol Ryu, Byeong-Chan Lee
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Publication number: 20030219921Abstract: A method and system for identifying and/or removing an oxide-induced dead zone in a VCSEL structure is disclosed herein. In general, a VCSEL structure can be formed having at least one oxide layer and an oxide-induced dead zone thereof. A thermal annealing operation can then be performed upon the VCSEL structure to remove the oxide-induced dead zone, thereby permitting oxide VCSEL structures thereof to be reliably and consistently fabricated. An oxidation operation may initially be performed upon the VCSEL structure to form the oxide layer and the associated oxide-induced dead zone. The thermal annealing operation is preferably performed upon the VCSEL after performing a wet oxidation operation upon the VCSEL structure.Type: ApplicationFiled: May 24, 2002Publication date: November 27, 2003Inventors: James R. Biard, James K. Guenter
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Patent number: 6649514Abstract: An EEPROM device having improved data retention and process for fabricating the device includes a two-step deposition process for the fabrication of an ILD layer overlying the high voltage elements of an EEPROM memory cell. The ILD layer is fabricated by first depositing an insulating layer on a high voltage device layer and thermally treating insulating layer. A second insulating layer is then deposited to overlie the first insulating layer. An EEPROM device in accordance with the invention includes a floating-gate transistor having a specified threshold voltage. A thermally-treated, boron-doped oxide layer overlies the floating-gate transistor and a second oxide layer overlies the thermally-treated, boron-doped oxide layer. The memory device exhibits data retention characteristics, such that upon subjecting the device to a baked temperature of at least about 250° C. for at least about 360 hours, the threshold voltage of the floating-gate transistor shifts by no more than about 100 mV.Type: GrantFiled: September 6, 2002Date of Patent: November 18, 2003Assignee: Lattice Semiconductor CorporationInventors: Chun Jiang, Sunil D. Mehta
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Patent number: 6645827Abstract: A method for forming isolation regions on a semiconductor substrate, includes partially covering the surface of the semiconductor substrate with oxidation inhabiting films, and heat-treating the portions of the semiconductor substrate which are exposed from the oxidation inhabiting films. The heat treatment consists of a wet-type heating step in a gaseous atmosphere containing oxygen and hydrogen, and a dry-type heating step in a atmosphere without hydrogen which is performed after the wet-type heating step.Type: GrantFiled: June 6, 2001Date of Patent: November 11, 2003Assignee: Oki Electric Industry Co., Ltd.Inventor: Toshiyuki Nakamura
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Publication number: 20030203646Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.Type: ApplicationFiled: April 2, 2003Publication date: October 30, 2003Inventors: Yoshikazu Tanabe, Toshiaki Nagahama, Nobuyoshi Natsuaki, Yasuhiko Nakatsuka
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Patent number: 6638899Abstract: A photoresist stripping solution which comprises (a) a salt of hydrofluoric acid with a base free from metal ions: (b) a water-soluble organic solvent; (c) a basic substance; and (d) water; and a method comprising etching a substrate using a photoresist pattern formed on the substrate as a mask, ashing the photoresist pattern, stripping the ashed photoresist pattern using the photoresist stripping solution as described above, and then rinsing the substrate with water. Thus, there are disclosed a photoresist stripping solution which is excellent not only in stripping away post-ashing residue (modified photoresist films) and post-etching residue (metal deposition) but also in protecting substrates from corrosion in the step of rinsing with water; and a method for stripping photoresists using the same.Type: GrantFiled: September 8, 2000Date of Patent: October 28, 2003Assignee: Tokyo Ohka Kogyo Co., Ltd.Inventors: Kazumasa Wakiya, Masakazu Kobayashi
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Patent number: 6638877Abstract: N2O is used as the oxidant for forming an ultra-thin oxide (14). The low oxidation efficiency of N2O compared to O2 allows the oxidation temperature to be raised to greater than 850° C. while maintaining the growth rate. A cold wall lamp heater rapid thermal process (RTP) tool limits reaction to the surface of the wafer (10). Hydrogen is preferably added to improve the electrical properties of the oxide (14).Type: GrantFiled: October 4, 2001Date of Patent: October 28, 2003Assignee: Texas Instruments IncorporatedInventor: Antonio L. P. Rotondaro
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Patent number: 6630411Abstract: A system, apparatus and/or method is provided for removing water vapor from a wafer processing chamber generated as a byproduct of wafer processing. A water vapor trap is used to collect the water vapor byproduct from the processing chamber interior. The water vapor trap has at least a portion thereof in communication with an interior of the processing chamber for collection of the water vapor and another portion thereof in communication with an exterior of the processing chamber. The portions are movable with respect to the interior and exterior of the processing chamber such that the portions may switch places. This allows the processing chamber to be in at least a substantially continuous mode of operation while still providing for the removal of water vapor byproduct via the water vapor trap. The “used” portion of the water vapor trap is regenerated while the “clean” portion is collecting water vapor.Type: GrantFiled: May 7, 2002Date of Patent: October 7, 2003Assignee: LSI Logic CorporationInventors: Robert D. Broyles, Michael J. Berman
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Publication number: 20030181063Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.Type: ApplicationFiled: March 18, 2003Publication date: September 25, 2003Inventor: Don Carl Powell
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Process for growing a dielectric layer on a silicon-containing surface using a mixture of N2O and O3
Patent number: 6607946Abstract: This invention is embodied in an improved process for growing high-quality silicon dioxide layers on silicon by subjecting it to a gaseous mixture of nitrous oxide (N2O) and ozone (O3). The presence of O3 in the oxidizing ambiance greatly enhances the oxidation rate compared to an ambiance in which N2O is the only oxidizing agent. In addition to enhancing the oxidation rate of silicon, it is hypothesized that the presence of O3 interferes with the growth of a thin silicon oxynitride layer near the interface of the silicon dioxide layer and the unreacted silicon surface which makes oxidation in the presence of N2O alone virtually self-limiting. The presence of N2O in the oxidizing ambiance does not impair oxide reliability, as is the case when silicon is oxidized with N2O in the presence of a strong, fluorine-containing oxidizing agent such as NF3 or SF6.Type: GrantFiled: April 13, 1998Date of Patent: August 19, 2003Assignee: Micron Technology, Inc.Inventors: Gurtej Singh Sandhu, Randhir PS Thakur -
Patent number: 6602808Abstract: In a gas-phase treating process of a semiconductor wafer using hydrogen, there is provided a technique for safely eliminating the hydrogen in an exhaust gas discharged from a gas-phase treating apparatus. The profile at the end portions of the side walls of gate electrodes of a poly-metal structure is improved by forming the gate electrodes over a semiconductor wafer IA having a gate oxide film and then by supplying the semiconductor wafer 1A with a hydrogen gas containing a low concentration of water, as generated from hydrogen and oxygen by catalytic action, to oxidize the principal face of the semiconductor wafer 1A selectively. After this, the hydrogen in the exhaust gas, as discharged from an oxidizing furnace, is completely converted into water by causing it to react with oxygen by a catalytic method.Type: GrantFiled: December 13, 2001Date of Patent: August 5, 2003Assignees: Hitachi, Ltd., Hitachi Tokyo Electronics Co., Ltd.Inventors: Yoshikazu Tanabe, Toshiaki Nagahama, Nobuyoshi Natsuaki, Yasuhiko Nakatsuka
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Patent number: 6602799Abstract: A method of forming a highly uniform ultra-thin insulating gate oxide layer on a silicon wafer is presented where an oxide layer non-uniformity introduced at a processing temperature is compensated during a cooling step during which oxygen is added to give additional oxide layer growth thereby producing a substantially uniform oxide layer.Type: GrantFiled: September 17, 2001Date of Patent: August 5, 2003Assignee: Taiwan Semiconductor Manufacturing Co., LtdInventors: Chi-Chun Chen, Wen Chang, Michael Chang, Shih-Chang Chen
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Publication number: 20030143864Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: ApplicationFiled: January 31, 2003Publication date: July 31, 2003Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6599845Abstract: An oxidation method of oxidizing surfaces of workpieces heated at a predetermined temperature in a vacuum atmosphere in a processing vessel produces active hydroxyl and active oxygen species. The active hydroxyl and active oxygen species oxidize the surfaces of the workpieces in a processing vessel. Both the intrafilm thickness uniformity and the characteristics of the oxide film can be improved, maintaining oxidation rate on a relatively high level.Type: GrantFiled: May 1, 2001Date of Patent: July 29, 2003Assignee: Tokyo Electron LimitedInventors: Shoichi Sato, Kazuhide Hasebe, Kota Umezawa
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Patent number: 6596650Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: August 28, 2001Date of Patent: July 22, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6596653Abstract: A method of forming a silicon oxide layer over a substrate disposed in a high density plasma substrate processing chamber. The silicon oxide layer is formed by flowing a process gas including a silicon-containing source, an oxygen-containing source, an inert gas and a hydrogen-containing source into the substrate processing chamber and forming a high density plasma (i.e., a plasma having an ion density of at least 1×1011 ions/cm3) from the process gas to deposit said silicon oxide layer over said substrate. In one embodiment, the hydrogen-containing source in the process gas is selected from the group of H2, H2O, NH3, CH4 and C2H6.Type: GrantFiled: May 11, 2001Date of Patent: July 22, 2003Assignee: Applied Materials, Inc.Inventors: Zhengquan Tan, Dongqing Li, Walter Zygmunt, Tetsuya Ishikawa
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Publication number: 20030124793Abstract: A semiconductor device includes a trench isolating elements, a memory cell transistor and a peripheral circuit Vcc transistor having a thermal oxide film of a first thickness, and a peripheral circuit Vpp transistor including a thermal oxide film and a thermal oxide film formed before trench formation, having a second thickness greater than the first thickness.Type: ApplicationFiled: June 18, 2002Publication date: July 3, 2003Applicant: Mitsubishi Denki Kabushiki KaishaInventor: Naoki Tsuji
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Patent number: 6573178Abstract: A method for manufacturing a semiconductor device, includes forming a film on a substrate to be processed in a reaction furnace at a first temperature, unloading the substrate from the reaction furnace, and lowering a temperature in the reaction furnace to a second temperature which is lower than the first temperature, conducting a gas purge, using only an inert gas, in the reaction furnace after the substrate has been unloaded from the reaction furnace.Type: GrantFiled: April 21, 2000Date of Patent: June 3, 2003Assignee: Kokusai Electric Co., Ltd.Inventor: Iwao Nakamura
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Patent number: 6569780Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: August 28, 2001Date of Patent: May 27, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6566199Abstract: An object of the present invention is to provide a film-forming method, a film-forming system, etc. capable of achieving adequate thickness repeatability and uniformity and sufficiently large film-forming rates in film formation of a thin film on a substrate to be treated and also capable of simplifying a system configuration. A thermal treatment system 1 according to the present invention is a system for forming a thin film of SiO2 on an Si wafer W and is provided with a reactant gas exhaust system 15 for reducing the pressure around the Si wafer W, a reactant gas supply system 14 for supplying hydrogen gas Gh and oxygen gas Go so as to mix them, onto the Si wafer W, and a chamber 2 having a lamp group 9G for heating the Si wafer W, and a wafer support member 3.Type: GrantFiled: January 18, 2001Date of Patent: May 20, 2003Assignee: Applied Materials, Inc.Inventors: Nobuo Tokai, Yuji Maeda, Masayuki Hashimoto
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Patent number: 6562684Abstract: The invention encompasses a method of forming a dielectric material. A nitrogen-comprising layer is formed on at least some of the surface of a rugged polysilicon substrate to form a first portion of a dielectric material. After the nitrogen-comprising layer is formed, at least some of the substrate is subjected to dry oxidation with one or both of NO and N2O to form a second portion of the dielectric material. The invention also encompasses a method of forming a capacitor. A layer of rugged silicon is formed over a substrate, and a nitrogen-comprising layer is formed on the layer of rugged silicon. Some of the rugged silicon is exposed through the nitrogen-comprising layer. After the nitrogen-comprising layer is formed, at least some of the exposed rugged silicon is subjected to dry oxidation conditions with one or both of NO and N2O. Subsequently, a conductive material layer is formed over the nitrogen-comprising layer. Additionally, the invention encompasses a capacitor structure.Type: GrantFiled: August 30, 2000Date of Patent: May 13, 2003Assignee: Micron Technology, Inc.Inventors: Behnam Moradi, Er-Xuan Ping, Lingyi A. Zheng, John Packard
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Patent number: 6541393Abstract: A semiconductor device is fabricated by a method comprising the steps of: selectively introducing a halogen element or argon into a device region 14 of a silicon substrate 10; and wet oxidizing the silicon substrate 10 in an ambient atmosphere which an H2O partial pressure is less than 1 atm to thereby form a silicon oxide film 22 in the device region 14 of the silicon substrate 10, and a silicon oxide film 24 thinner than the silicon oxide film 22 in a device region 16 of the silicon substrate 10. Whereby the silicon oxide film in a device region 14 with the halogen element or argon introduced can be selectively formed thick. The silicon oxide films are formed by the wet oxidation, whereby the gate insulation films can be more reliable than those formed by the dry oxidation.Type: GrantFiled: February 9, 2001Date of Patent: April 1, 2003Assignee: Fujitsu LimitedInventors: Taro Sugizaki, Toshiro Nakanishi, Kyoichi Suguro, Atsushi Murakoshi
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Patent number: 6537926Abstract: A two-step progressive thermal oxidation process is provided to improve the thickness uniformity of a thin oxide layer in semiconductor wafer fabrication. A semiconductor wafer, e.g., of silicon, with a surface subject to formation of an oxide layer thereon but which is substantially oxide layer-free, is loaded, e.g., at room temperature, into an oxidation furnace maintained at a low loading temperature, e.g., of 400-600° C., and the wafer temperature is adjusted to a low oxidizing temperature, e.g., of 400-600° C., all while the wafer is under an inert, e.g., nitrogen, atmosphere. The wafer is then subjected to initial oxidation, e.g., in dry oxygen, at the low oxidizing temperature to form a uniform initial thickness oxide, e.g., silicon dioxide, layer, e.g., of up to 10 angstroms, on the surface, after which the furnace temperature is increased to a high oxidizing temperature, e.g., of 700-1200° C., while the wafer is under an inert atmosphere. The wafer is next subjected to final oxidation, e.Type: GrantFiled: August 14, 2000Date of Patent: March 25, 2003Assignee: Infineon Technologies, AGInventors: Martin Schrems, Helmut Horst Tews
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Patent number: 6528403Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: December 13, 2001Date of Patent: March 4, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6528431Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: January 3, 2001Date of Patent: March 4, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6518201Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: January 31, 2000Date of Patent: February 11, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6518202Abstract: A method for fabricating a semiconductor integrated circuit device of the invention comprises feeding oxidation species containing a low concentration of water, which is generated from hydrogen and oxygen by the catalytic action, to the main surface of or in the vicinity of a semiconductor wafer, and forming a thin oxide film serving as a gate insulating film of an MOS transistor and having a thickness of 5 nm or below on the main surface of the semiconductor wafer at an oxide film-growing rate sufficient to ensure fidelity in formation of an oxide film and uniformity in thickness of the oxide film.Type: GrantFiled: January 3, 2001Date of Patent: February 11, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Satoshi Sakai, Nobuyoshi Natsuaki
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Patent number: 6514879Abstract: A configuration of various chemical compound generators coupled to a furnace provides the environment for formation of extremely thin oxides of silicon on a wafer. Dichloroethylene is reacted with oxygen in a first heated reaction chamber and reaction products therefrom are diluted with a gas such as nitrogen and then introduced into a vertically oriented furnace maintained at an elevated temperature and having rotating wafers therein. Hydrogen and oxygen are catalytically reacted to form steam in a second heated reaction chamber, the steam is diluted with a gas such as nitrogen and introduced into the vertical diffusion furnace. In a further aspect of the present invention, MOSFETs having gate dielectric layers of extremely thin oxides of silicon are formed.Type: GrantFiled: December 17, 1999Date of Patent: February 4, 2003Assignee: Intel CorporationInventors: Reza Arghavani, Robert Chau, Ron Dalesky
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Publication number: 20030022523Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.Type: ApplicationFiled: September 6, 2002Publication date: January 30, 2003Applicant: FUJITSU LIMITEDInventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
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Patent number: 6503819Abstract: With a view to preventing the oxidation of a metal film at the time of light oxidation treatment after gate patterning and at the same time to making it possible to control the reproducibility of oxide film formation and homogeneity of oxide film thickness at gate side-wall end portions, in a gate processing step using a poly-metal, a gate electrode is formed by patterning a gate electrode material which has been deposited over a semiconductor wafer 1A having a gate oxide film formed thereon and has a poly-metal structure and then, the principal surface of the semiconductor wafer 1A heated to a predetermined temperature or vicinity thereof is supplied with a hydrogen gas which contains water at a low concentration, the water having been formed from hydrogen and oxygen by a catalytic action, to selectively oxidize the principal surface of the semiconductor wafer 1A, whereby the profile of the side-wall end portions of the gate electrode is improved.Type: GrantFiled: January 31, 2001Date of Patent: January 7, 2003Assignee: Hitachi, Ltd.Inventors: Yoshikazu Tanabe, Isamu Asano, Makoto Yoshida, Naoki Yamamoto, Masayoshi Saito, Nobuyoshi Natsuaki
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Patent number: 6495475Abstract: A method for fabricating a silicon dioxide/silicon nitride/silicon dioxide (ONO) stacked composite having a thin silicon nitride layer for providing a high capacitance interpoly dielectric structure. In the formation of the ONO composite, a bottom silicon dioxide layer is formed on a substrate such as polysilicon. A silicon nitride layer is formed on the silicon dioxide-layer and is thinned by oxidation. The oxidation of the silicon nitride film consumes some of the silicon nitride by a reaction that produces a temporary silicon dioxide layer. The temporary silicon dioxide layer is removed with a hydrofluoric acid dilution. The silicon nitride layer is again thinned by re-oxidization as a top silicon dioxide layer is formed on the silicon nitride layer. A layer of polysilicon is deposited over the silicon nitride, forming an interpoly dielectric.Type: GrantFiled: March 28, 2001Date of Patent: December 17, 2002Assignee: Atmel CorporationInventors: Mark A. Good, Amit S. Kelkar
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Publication number: 20020187651Abstract: A technique for controlling the oxidation of silicon is achieved by applying low temperature ammonia prior to the oxidation. The result is that the subsequent oxidation of the silicon is at a slower oxidation rate and higher nitrogen content. The higher nitrogen content is particularly beneficial for a gate dielectric because it acts as somewhat of a boron barrier and provides additional resistance to unwanted oxidation. The result is transistors with improved gate dielectric thickness uniformity across a wafer for a tighter threshold voltage distribution, reduced shift in threshold voltage, and improved time to breakdown.Type: ApplicationFiled: June 11, 2001Publication date: December 12, 2002Inventors: Kimberly G. Reid, Hsing-Huang Tseng, Julie C.H. Chang, John R. Alvis
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Publication number: 20020182888Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.Type: ApplicationFiled: July 19, 2002Publication date: December 5, 2002Applicant: International Business Machines CorporationInventors: Douglas A. Buchanan, Evgeni P. Gousev, Carol J. Heenan, Wade J. Hodge, Steven M. Shank, Patrick R. Varekamp
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Patent number: 6475927Abstract: In the formation of semiconductor devices, a processing method is provided, including steps for forming an oxide layer. The embodied methods involve a series of oxidation steps, with optional interposed cleanings, as well as an optional conditioning step after oxidation. In a preferred embodiment, these steps are clustered and transportation between the clustered process chambers takes place in a controlled environment such as nitrogen or a vacuum. In some embodiments, the method provides an oxide layer to be used as part of the device, such as a tunnel oxide for a flash-EEPROM, or as a general gate oxide. Alternatively, the steps can be used to sculpt through oxidation various levels of a substrate, thereby allowing for embedded memory architecture. Cleaning between oxidation steps offers the advantage of providing a more defect-free oxide layer or providing access to a more defect-free level of substrate.Type: GrantFiled: February 2, 1998Date of Patent: November 5, 2002Assignee: Micron Technology, Inc.Inventor: Randhir P. Thakur
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Publication number: 20020160623Abstract: In this disclosure, we present processes of growing SiO2 films over silicon at temperatures as low as room temperature and at pressures as high as 1 atmosphere. The lower temperature oxidation was made possible by creation of oxygen atoms and radicals by adding noble gas(es) along with oxidizing gas(es) and applying RF power to create plasma. It was also possible to fabricate silicon nitride films by flowing nitrogen containing gas(es) with noble gas(es) and applying RF power to create plasma at pressures as high as one atmosphere. In addition, the above processes could also be carried out using microwave power instead of RF power to create plasma.Type: ApplicationFiled: August 27, 2001Publication date: October 31, 2002Inventor: Ramesh H. Kakkad
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Publication number: 20020155728Abstract: Semiconductor chip assemblies incorporating flexible, sheet-like elements having terminals thereon overlying the front or rear face of the chip to provide a compact unit. The terminals on the sheet-like element are movable with respect to the chip, so as to compensate for thermal expansion. A resilient element such as a compliant layer interposed between the chip and terminals permits independent movement of the individual terminals toward the chip driving engagement with a test probe assembly so as to permit reliable engagement despite tolerances.Type: ApplicationFiled: June 5, 2002Publication date: October 24, 2002Applicant: Tessera, Inc.Inventors: Igor Y. Khandros, Thomas H. DiStefano
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Patent number: 6468926Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.Type: GrantFiled: June 29, 1999Date of Patent: October 22, 2002Assignee: Fujitsu LimitedInventors: Kiyoshi Irino, Ken-ichi Hikazutani, Tatsuya Kawamura, Taro Sugizaki, Satoshi Ohkubo, Toshiro Nakanishi, Kanetake Takasaki
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Patent number: 6461948Abstract: A method of doping silicon that involves placing a silicon wafer in spaced relationship to a solid phosphorus dopant source at a first temperature for a time sufficient to deposit a phosphorus-containing layer on the surface of the wafer and subsequently oxidizing the doped silicon wafer with wet oxygen or pyrogenic steam at a second temperature lower than the first temperature. The silicon wafer is maintained in spaced relationship to the solid phosphorus dopant source during the oxidizing step. The temperatures are selected such that the solid phosphorus dopant source evolves P2O5 at the first temperature and the second temperature is sufficiently lower than the first temperature to decrease evolution of P2O5 from the solid phosphorus dopant source during the oxidizing step.Type: GrantFiled: March 29, 2000Date of Patent: October 8, 2002Assignee: Techneglas, Inc.Inventors: James E. Rapp, Russell B. Rogenski
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Patent number: 6458715Abstract: A target semiconductor device can be obtained stably by reforming an insulating film and a semiconductor. In a process of manufacturing a semiconductor device, at least one of the semiconductor and the insulating film is reformed after an annealing process for annealing the semiconductor at a temperature ranging from 20 to 400° C. in the atmosphere containing a gas of water (H2O) with a partial pressure from 1 Torr to a saturated vapor pressure for an annealing time ranging from 15 seconds to 20 hours.Type: GrantFiled: February 8, 2001Date of Patent: October 1, 2002Assignee: Sony CorporationInventors: Naoki Sano, Masaki Hara, Mitsunobu Sekiya, Toshiyuki Sameshima
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Publication number: 20020132493Abstract: Using deuterium oxygen during stream oxidation forms an oxidizing vapor. Since deuterium is chemically similar to hydrogen, the oxidation process takes place normally and the silicon-silicon oxide interface is concurrently saturated with deuterium. Saturating the interface with deuterium reduces the interface trap density thereby reducing channel hot carrier degradation.Type: ApplicationFiled: July 16, 2001Publication date: September 19, 2002Inventors: Victor Watt, Beth Walden, Brian K. Kirkpatrick, Edmund G. Russell
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Publication number: 20020127872Abstract: An apparatus and method of forming an oxynitride insulating layer on a substrate performed by putting the substrate at a first temperature within the main chamber of a furnace, exposing the substrate to a nitrogen containing gas at a second temperature which is higher than the first temperature, and growing the oxynitride layer on the substrate within the main chamber in the presence of post-combusted gases. The higher temperature nitrogen containing gases are combusted in a chamber outside the main chamber. The higher temperature is in the range of 800 to 1200° C., and preferably 950° C. In a second embodiment, distributed N2O gas injectors within the main chamber deliver the nitrogen containing gas. The nitrogen containing gas is pre-heated outside the chamber. The nitrogen containing gas is then delivered to a gas manifold that splits the gas flow and directs the gas to a number of gas injectors, preferably two to four injectors within the main process tube.Type: ApplicationFiled: June 22, 2001Publication date: September 12, 2002Applicant: International Business Machines CorporationInventors: Douglas A. Buchanan, Evgeni P. Gousev, Carol J. Heenan, Wade J. Hodge, Steven M. Shank, Patrick R. Varekamp
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Publication number: 20020123238Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.Type: ApplicationFiled: April 18, 2002Publication date: September 5, 2002Inventor: Don Carl Powell
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Patent number: 6440382Abstract: Disclosed is a process of treating semiconductor substrates, including the production of pure water, a method of producing the pure water for semiconductor fabrication, and a water-producing apparatus. Ammonia is catalytically oxidized in a catalytic conversion reactor to form pure water. The water is then supplied to a semiconductor fabrication process. The water-producing apparatus comprises a housing surrounding a catalytic material for adsorbing ammonia, an ammonia and oxidant source, each in communication with the housing, and an outlet for reaction products. The outlet is connected to a semiconductor processing apparatus. According to preferred embodiments of the invention, the apparatus can be a catalytic tube reactor, a fixed bed reactor or a fluidized bed reactor.Type: GrantFiled: August 31, 1999Date of Patent: August 27, 2002Assignee: Micron Technology, Inc.Inventor: Don Carl Powell