Nitridation Patents (Class 438/775)
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Patent number: 5972783Abstract: An element isolator is formed in a silicon substrate. A gate oxide film and a gate electrode are formed overlying the silicon substrate. Subsequently, a four-step large-tilted-angle ion implant is performed in which ions of nitrogen are implanted at an angle of tilt of 25 degrees, to form an oxynitride layer at each edge of the gate oxide film and to form a nitrogen diffusion layer in the silicon substrate. This is followed by formation of a lightly-doped source/drain region by means of impurity doping. A sidewall is formed on each side surface of the gate electrode, which is followed by formation of a heavily-doped source/drain region by impurity doping. The present invention provides an improved semiconductor device having high-performance, highly-reliable MOS field effect transistors and a method for fabricating the same.Type: GrantFiled: February 6, 1997Date of Patent: October 26, 1999Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masatoshi Arai, Mizuki Segawa, Toshiki Yabu
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Patent number: 5970382Abstract: A process for forming coatings and films from a gaseous reactant onto a semiconductor device is disclosed. The process includes preheating a gas to a temperature so that the gas will immediately react with the semiconductor wafer. After being preheated, the gas is contacted with the wafer under controlled conditions in order to form a uniform film. For instance, in one embodiment, a gas containing dinitrogen oxide is preheated until the dinitrogen oxide disassociates into nitric oxide. The nitric oxide is then contacted with the wafer to form an oxide coating. In an alternative embodiment, gaseous hydrogen and oxygen are preheated to a temperature sufficient to form steam, which subsequently chemically reacts with the wafer.Type: GrantFiled: January 26, 1998Date of Patent: October 19, 1999Assignee: AG AssociatesInventor: Nitin B. Shah
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Patent number: 5966606Abstract: A side-wall film of a gate electrode is fabricated as a two-layer structure including an underlying thin silicon nitride film and a relatively thick silicon oxide film. The silicon nitride film covers and protects the edge of the gate oxide film against formation of a gate bird's beak at the edge of the gate oxide film. The side-wall contacts with the silicon substrate substantially at the thick silicon oxide film of the side-wall, which prevents formation of a carrier trap area adjacent to the channel area. The bottom of the side-wall may be a nitride-doped silicon oxide instead.Type: GrantFiled: May 14, 1997Date of Patent: October 12, 1999Assignee: NEC CorporationInventor: Atsuki Ono
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Patent number: 5966624Abstract: A structure for semiconductors having a crystalline layer includes a first silicon-containing dielectric film formed on a semiconductor substrate. A crystalline layer is formed on the first dielectric film by hydrogen annealing the surface of the first dielectric layer to form a layer of silicon atoms. The silicon atoms are reacted with a gas containing nitrogen or annealed in the presence of an inert gas to form either a crystalline layer of silicon nitride or a crystalline layer of silicon, respectively. A second dielectric film can be formed on the crystalline layer. In particularly useful embodiments, the crystalline layer of silicon or silicon nitride is three to twenty monolayers. The silicon nitride structure described herein forms an improved dielectric structure reducing the thickness of dielectric layer and improving resistance to electrical breakdown. The silicon structure described herein forms a semiconductor layer on a dielectric layer.Type: GrantFiled: July 29, 1997Date of Patent: October 12, 1999Assignee: Siemens AktiengesellschaftInventor: Hua Shen
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Patent number: 5960289Abstract: A method for forming a dual gate oxide (DGO) structure begins by forming a first oxide layer (106) within active areas (110) and (112). A protection layer (108a) is then formed over the layer (106). A mask (114) is used to allow removal of the layers (106 and 108a) from the active area (110). A thermal oxidation process is then used to form a thin second oxide layer (118) within an active area (110). Conductive gate electrodes (120a and 120b) are then formed wherein the first oxide layer (106) and the protection layer (108c) are incorporated into the gate dielectric layer of an MOS transistor (122a). The transistor (122b) has a thinner gate oxide layer that excludes the protection layer (108c).Type: GrantFiled: June 22, 1998Date of Patent: September 28, 1999Assignee: Motorola, Inc.Inventors: Paul G. Y. Tsui, Hsing-Huang Tseng, Navakanta Bhat, Ping Chen
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Patent number: 5943602Abstract: A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.Type: GrantFiled: May 1, 1998Date of Patent: August 24, 1999Assignee: Micron Technology, Inc.Inventor: Randhir P. S. Thakur
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Patent number: 5926730Abstract: Methods and apparatus for forming word line stacks comprise forming a thin nitride layer coupled between a bottom silicon layer and a conductor layer. In a further embodiment, a diffusion barrier layer is coupled between the thin nitride layer and the bottom silicon layer. The thin nitride layer is formed by annealing a silicon oxide film in a nitrogen-containing ambient.Type: GrantFiled: February 19, 1997Date of Patent: July 20, 1999Assignee: Micron Technology, Inc.Inventors: Yongjun Hu, Randhir P. S. Thakur, Scott DeBoer
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Patent number: 5913149Abstract: A method is provided for forming silicon nitride stacks. A semiconductor substrate is cleaned to remove any native oxide, and an insulative material is disposed thereon. A plurality of films are deposited superjacent the insulative material, and each of the plurality of films converted into a dielectric to form a multi-layered stack. A fill layer is formed superjacent the multi-layered stack to seal any pinholes. The fill layer is formed by at least one of low temperature chemical vapor deposition (CVD) of oxide, low temperature deposition of nitride, low temperature re-oxidation of ozone, the low temperature is at least 20.degree. C.Type: GrantFiled: September 14, 1994Date of Patent: June 15, 1999Assignee: Micron Technology, Inc.Inventors: Randhir P. S. Thakur, Gurtej Singh Sandhu
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Patent number: 5904523Abstract: A process for forming a silicon oxynitride layer in an N.sub.2 atmosphere is disclosed. The silicon oxynitride layer is formed by heating a silicon substrate in an N.sub.2 atmosphere for a period of time that is sufficient to form a nitrided layer with a nitrogen content of at least about 5.times.10.sup.13 atoms/cm.sup.2 therein. Afterward, the substrate is further oxidized in an oxygen containing atmosphere for a period of time sufficient to form a silicon oxynitride layer on the substrate with a thickness of at least about 1 nm and a nitrogen content of at least about 5.times.10.sup.13 atoms/cm.sup.2 on the wafer.Type: GrantFiled: October 3, 1997Date of Patent: May 18, 1999Assignee: Lucent Technologies Inc.Inventors: Leonard Cecil Feldman, Martin Laurence Green, Thomas Werner Sorsch
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Patent number: 5891798Abstract: A method for forming an insulator with a high dielectric constant on silicon is disclosed. This method overcomes one limitation of increasing the dielectric constant of a gate dielectric by using a high dielectric constant material, such as a paraelectric material, instead of silicon dioxide. First, nitrogen is implanted into the silicon through a sacrificial oxide layer. After annealing the substrate and stripping the sacrificial oxide, a dielectric layer is formed from a material with a high dielectric constant, such as a paraelectric material. Although the paraelectric material provides a source of oxygen for oxidation of silicon in subsequent high temperature process steps, no oxidation takes place due to the presence of the nitrogen in the silicon. Therefore, there is no undesired decrease in the overall capacitance of the dielectric system.Type: GrantFiled: December 20, 1996Date of Patent: April 6, 1999Assignee: Intel CorporationInventors: Brian Doyle, Jack Lee
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Patent number: 5891809Abstract: A method of forming a thin, robust nitrided oxide layer. The process results in a manufacturable, uniform, low-defect density, reliable nitrided oxide that may be used as a gate dielectric, as a portion of a spacer, or as a portion of a trench isolation. First, a substrate is oxidized in a chlorinated dry oxidation followed by a low temperature pyrogenic steam oxidation. Next, a low temperature ammonia anneal is performed, followed by a high temperature anneal in an inert ambient.Type: GrantFiled: September 29, 1995Date of Patent: April 6, 1999Assignee: Intel CorporationInventors: Robert S. K. Chau, Lawrence N. Brigham, Chia-Hong Jan, Chan-Hong Chern, Binny P. Arcot
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Patent number: 5891789Abstract: A method for fabricating an isolation layer in a semiconductor device, includes the steps of forming a pad oxide layer on a substrate and sequentially forming a first thin nitride layer, a polysilicon layer and a second nitride layer on the pad oxide layer; selectively and sequentially dry-etching the second nitride layer, polysilicon layer, first nitride layer and pad oxide layer to expose a portion of the substrate corresponding to a field region and to form an active region pattern; growing an oxide layer on the exposed portion of the substrate in the field region; carrying out nitridation onto the polysilicon layer to form a nitride layer on the side of the active region pattern; and performing field oxidation to form a field oxide layer in the field region.Type: GrantFiled: March 5, 1997Date of Patent: April 6, 1999Assignee: LG Semicon Co., Ltd.Inventor: Sang-Don Lee
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Patent number: 5882978Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.Type: GrantFiled: April 22, 1997Date of Patent: March 16, 1999Assignee: Micron Technology, Inc.Inventors: Anand Srinivasan, Sujit Sharan, Gurtej S. Sandhu
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Patent number: 5838056Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH.sub.3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800.degree. C. to 1200.degree. C. and the partial pressures of H.sub.2 O and O.sub.2 are set at 1.times.10.sup.-4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained.Type: GrantFiled: December 30, 1996Date of Patent: November 17, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Yoshio Kasai, Takashi Suzuki, Takanori Tsuda, Yuuichi Mikata, Hiroshi Akahori, Akihito Yamamoto
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Patent number: 5827769Abstract: A method of fabricating a field effect transistor with increased resistance to hot carrier damage is disclosed. An oxide is grown on the gate electrode. This oxide is strengthened by nitridation and anneal. After a lightly doped drain implant, a second side oxide and a conformal nitride layer are deposited. Then, the conformal nitride is anisotropically etched to form spacers for masking a high dose drain implant. An NMOS transitor fabricated with this process has been found to be forty percent less susceptible to hot carrier damage than a conventional lightly doped drain process. Also, this process has proven to be more manufacturable than one in which the side oxide is nitrided and re-oxidized.Type: GrantFiled: November 20, 1996Date of Patent: October 27, 1998Assignee: Intel CorporationInventors: Payman Aminzadeh, Reza Arghavani, Peter Moon
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Patent number: 5821172Abstract: A semiconductor manufacturing process in which a single crystal silicon semiconductor substrate is immersed in an oxidation chamber maintained at a first temperature preferably between 400.degree. and 700.degree. C. for a first duration. During the first duration, the oxidation chamber comprises a first ambient gas of N.sub.2 or Argon. Thereafter, the ambient temperature within the oxidation chamber is ramped to a second temperature in the range of approximately 600.degree. to 1100.degree. C. NH.sub.3 is then introduced into the oxidation chamber simultaneously with either NO or N.sub.2 O to form an oxynitride layer. Thereafter, a conductive gate structure is formed on the oxynitride layer and a source/drain impurity distribution is introduced into a pair of source/drain regions laterally displaced on either side of the channel region of the semiconductor substrate. The channel region is aligned with the conductive gate.Type: GrantFiled: January 6, 1997Date of Patent: October 13, 1998Assignee: Advanced Micro Devices, Inc.Inventors: Mark C. Gilmer, Mark I. Gardner
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Patent number: 5821153Abstract: The present invention provides a method of manufacturing a high nitrogen (N) content oxynitride layer 34A 34B over field oxide regions. The oxynitride layer 34A 34B prevents subsequent etches from forming recesses in the field oxide regions 30 and planarizes the surface. The method begins by forming a field oxide region 30 an isolation area in the substrate 22. A high N content oxynitride protection layer 34A 34B (an etch barrier) is then formed surrounding (over and under) the field oxide layer 30. The high N content oxynitride protection layer 34A 34B is formed by heating (e.g., annealing) the substrate in a gas environment comprising ammonia. The high N content oxynitride layer is preferably formed by rapidly thermally annealing the substrate at temperature between about 825.degree. and 875 .degree. C. in an ammonia containing environment with a partial pressure of between about 0.5 and 1.2 kg/cm.sup.2 .Type: GrantFiled: December 9, 1996Date of Patent: October 13, 1998Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chaochieh Tsai, Chin-Hsiung Ho
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Patent number: 5780346Abstract: A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.Type: GrantFiled: December 31, 1996Date of Patent: July 14, 1998Assignee: Intel CorporationInventors: Reza Arghavani, Robert S. Chau, Simon Yang, John Graham
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Patent number: 5780364Abstract: A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.Type: GrantFiled: November 27, 1996Date of Patent: July 14, 1998Assignee: Micron Technology, Inc.Inventor: Randhir P. S. Thakur
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Patent number: 5763300Abstract: A microelectronic capacitor is formed by nitrating the surface of a conducting electrode on a microelectronic substrate. The nitrated surface of the conductive electrode is then oxidized. The nitrating and oxidizing steps collectively form a film of silicon oxynitride on the conductive electrode. A tantalum pentoxide film is then formed on the oxidized and nitrated surface of the conductive electrode. The tantalum pentoxide film may then be thermally treated in the presence of oxygen gas. High performance microelectronic capacitors are thereby provided.Type: GrantFiled: September 10, 1996Date of Patent: June 9, 1998Assignee: Samsung Electronics Co., Ltd.Inventors: In-sung Park, Kyung-hoon Kim
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Patent number: 5731235Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, the silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.Type: GrantFiled: October 30, 1996Date of Patent: March 24, 1998Assignee: Micron Technology, Inc.Inventors: Anand Srinivasan, Sujit Sharan, Gurtej S. Sandhu
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Patent number: 5726091Abstract: A new method of local oxidation using an oxynitrided pad oxide layer to suppress the growth of a bird's beak is described. An oxide layer is provided over the surface of a semiconductor substrate. The oxide layer is annealed in a nitrogen atmosphere whereby the oxide layer is nitrided. The nitrided oxide layer is then reoxidized. A silicon nitride layer is deposited overlying the oxide layer. Portions of the silicon nitride and oxide layers not covered by a mask pattern are etched through to provide an opening exposing the portion of the semiconductor substrate that will form the field oxidation. The silicon substrate within the opening is oxidized wherein the semiconductor substrate is transformed to silicon dioxide wherein the nitrided oxide layer suppresses the formation of the bird's beak whereby the field oxidation is formed with a small bird's beak. The remaining oxide and silicon nitride layers are removed completing the field oxidation of the integrated circuit.Type: GrantFiled: August 29, 1996Date of Patent: March 10, 1998Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chao-Chieh Tsai, Shun-Liang Hsu
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Patent number: 5726087Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of one of either nitrogen or fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features.Type: GrantFiled: June 9, 1994Date of Patent: March 10, 1998Assignee: Motorola, Inc.Inventors: Hsing-Huang Tseng, Philip J. Tobin
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Patent number: 5719086Abstract: A method for isolating the elements of semiconductor devices, in which bird's beak can be restrained by accumulating nitrogen atoms between a pad oxide film and a silicon substrate and the etch depth of a silicon substrate can be controlled by use of wet etch to remove the oxide which is grown on the silicon substrate at a low temperature after formation of nitride spacer, thereby reproducing good profiles of the field oxide film.Type: GrantFiled: November 1, 1996Date of Patent: February 17, 1998Assignee: Hyundai Electronics Industries Co., Ltd.Inventors: Young Bog Kim, Sung Ku Kwon, Byung Jin Cho, Jong Choul Kim
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Patent number: 5712208Abstract: A semiconductor dielectric (10) is formed by providing a base layer (12) having a surface. A thin interface layer (13) is formed at the surface of the base layer (12). The thin interface layer has a substantial concentration of both nitrogen and fluorine. A thermal oxide layer (14) is formed overlying the interface layer (13). A deposited dielectric layer (16) is formed overlying the thermal oxide layer (14). The deposited dielectric layer (16) is optionally densified by a thermal heat cycle. The deposited dielectric layer (16) has micropores that are misaligned to micropores in the thermal oxide layer (14) to provide enhanced features which the nitrogen/fluorine interface further improves the dielectric's features.Type: GrantFiled: May 25, 1995Date of Patent: January 27, 1998Assignee: Motorola, Inc.Inventors: Hsing-Huang Tseng, Philip J. Tobin, Keith E. Witek