Abstract: Disclosed is a method of manufacturing a semiconductor device, including the step of supplying an oxidizing gas and a nitriding gas onto one main surface of a semiconductor substrate while heating the substrate so as to oxynitride the surface region of the substrate, wherein the supplying step is performed such that the gaseous phase above the main surface of the substrate forms a first region having a substantially uniform temperature in a direction perpendicular to the main surface of the substrate and a second region interposed between the first region and the substrate and having a temperature gradient in a direction perpendicular to the main surface of the substrate such that the temperature is elevated toward the substrate, and the distance from the main surface of the substrate to the interface between the first and second regions is set at 9.5 cm or less.

Abstract: A method of forming a metal silicide comprising contact over a substrate includes forming an opening in an insulative material to a substrate region with which electrical connection is desired. The opening has insulative sidewalls. The insulative sidewalls within the opening are coated with an electrically conductive material. The coating less than completely fills the opening. An example process is to deposit an elemental metal or metal alloy layer, and then nitridize it. Preferably, the substrate region comprises silicon which reacts with the metal layer during deposition to form a silicide of the metal(s). A preferred deposition comprised forming a plasma from source gases comprising TiCl4 and H2. A metal silicide layer is then substantially chemical vapor deposited on the conductive coating and over the substrate region relative to any exposed insulative material to fill remaining volume of the opening with the metal silicide.

Abstract: A method of fabricating a dielectric layer is provided. A first oxide layer is formed on a polysilicon layer. A silicon-rich nitride layer is formed on a first oxide layer. A silicon-poor nitride layer is formed on the silicon-rich nitride layer. An oxidation step is performed on the silicon-poor nitride layer. A second oxide layer is formed on the silicon-poor nitride layer. The dielectric layer comprising a multiple nitride layer structure is formed.

Abstract: A semiconductor device structure with differential field oxide thicknesses. A single field oxidation step produces a nitrided field oxide region (322) that is thinner than a non-nitrided field oxide region (324). The bird's beak (326) of the nitrided field oxide (322) encroaches less into the active cell region than the bird's beak (328) of the thicker non-nitrided field oxide (324). The differential field oxide thicknesses allow isolation of multi-voltage integrated circuit devices, such as flash memory devices, while increasing available active cell area for a given design rule.

Abstract: Techniques for fabricating integrated circuits having devices with gate oxides having different thicknesses and a high nitrogen content include forming the gate oxides at pressures at least as high as 2.0 atmospheres in an ambient of a nitrogen-containing gas. In one implementation, a substrate includes a first region for forming a first device having a gate oxide of a first thickness and a second region for forming a second device having a gate oxide of a second different thickness. A first oxynitride layer is formed on the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres. A portion of the first oxynitride layer is removed to expose a surface of the substrate on the second region. Subsequently, a second oxynitride is formed over the first and second regions in an ambient comprising a nitrogen-containing gas at a pressure in a range of about 10 to about 15 atmospheres to form the first and second gate oxides.

Abstract: A method of fabricating gate oxides of different thicknesses has been achieved. Active area isolations are provided in a silicon substrate to define low voltage sections and high voltage sections in the silicon substrate. A sacrificial oxide layer is formed overlying the silicon substrate. A silicon nitride layer is deposited overlying the sacrificial oxide layer. A masking oxide layer is deposited overlying the silicon nitride layer. The masking oxide layer is patterned to form a hard mask overlying the low voltage sections. The silicon nitride layer is etched through where exposed by the hard mask thereby exposing the sacrificial oxide layer overlying the high voltage section. The exposed sacrificial oxide layer and the hard mask are etched away. A thick gate oxide layer is grown overlying the silicon substrate in the high voltage section. The silicon nitride layer is etched away. The sacrificial oxide layer overlying the low voltage section is etched away.

Abstract: Methods and apparatus for fabricating stacked capacitor structures, which include barrier layers, are disclosed. According to one aspect of the present invention, a method for reducing outdiffusion within an integrated circuit includes forming a gate oxide layer over a substrate, and further forming a silicon plug over a portion of the gate oxide layer. A silicon dioxide layer is then formed over the gate oxide layer, and is arranged around the silicon plug. A first barrier film is formed over the silicon plug, and a dielectric layer is formed over the silicon dioxide layer. In one embodiment, forming the first barrier film includes forming a first oxide layer over the silicon plug, nitridizing the first oxide layer, and etching the nitridized first oxide layer.

Abstract: A method is disclosed to form a plurality of oxides of different thicknesses with one step oxidation. In a first embodiment, a substrate is provided having a high-voltage cell area and a peripheral low-voltage logic area separated by a trench isolation region. The substrate is first nitrided. Then the nitride layer over the high-voltage area is removed, and the substrate is wet cleaned with HF solution. The substrate surface is next oxidized to form a tunnel oxide of desired thickness over the high-voltage. In a second embodiment, a sacrificial oxide is used over the substrate for patterning the high voltage cell area and the low-voltage logic area. The sacrificial oxide is removed from the low-voltage area and the substrate is nitrided after cleaning with a solution not containing HF, thus forming a nitride layer over the low-voltage area. Then, the sacrificial oxide is removed from the high-voltage area with an HF dip, and tunnel oxide of desired thickness is formed over the same area.

Abstract: A method for growing nitride semiconductor crystals according to the present invention includes the steps of: a) forming a first metal single crystal layer on a substrate; b) forming a metal nitride single crystal layer by nitrifying the first metal single crystal layer; and c) epitaxially growing a first nitride semiconductor layer on the metal nitride single crystal layer.

Abstract: Disclosed are multilevel interconnects for integrated circuit devices, especially copper/dual damascene devices, and methods of fabrication. Methylated-oxide type hardmasks are formed over polymeric interlayer dielectric materials. Preferably the hardmasks are materials having a dielectric constant of less than 3 and more preferably 2.7 or less. Advantageously, both the hardmask and the interlayer dielectric can be spincoated.

Abstract: A method for forming a gate conductor cap in a transistor comprises the steps of: a) forming a polysilicon gate conductor; b) doping the polysilicon gate; c) doping diffusion areas; and d) capping the gate conductor by a nitridation method chosen from among selective nitride deposition and selective surface nitridation. The resulting transistor may comprise a capped gate conductor and borderless diffusion contacts, wherein the capping occurred by a nitridation method chosen from among selective nitride deposition and selective surface nitridation and wherein a portion of the gate conductor is masked during the nitridation method to leave open a contact area for a local interconnect or a gate contact.

Abstract: A silicon wafer is heated from an initial pre-heating temperature (T0) up to a first annealing temperature (T1) by a rapid heating up step using an IR lamp. A first annealing is executed at the first annealing temperature (T1). Successively, while the silicon wafer is maintained at a second annealing temperature (T2) lower than the first annealing temperature (T1), a second annealing step is executed by a resistive heating furnace. A thermal oxidation can be executed as the second annealing step. To do so, an equipment for manufacturing a semiconductor device in the present invention is provided with: a heating device having an IR lamp and a resistive heater; an annealing tube having on a surface thereof a plurality of concave portions in such a way that each bottom approaches a central line; a resistive heater wrapped around this annealing tube; and an IR lamp movably inserted into and pulled out from the concave portion from the external.

Abstract: A method for fabricating a semiconductor device having asymmetric source-drain extension regions includes the formation of a conformal layer of spacer forming material over a gate electrode. Nitrogen atoms are directionally introduced into the sidewall spacer material to form nitrogenated regions within the sidewall spacer material. The gate electrode casts a shadow over a portion of the sidewall spacer material adjacent to an edge of the gate electrode that is opposite from the direction of introduction of the nitrogen atoms. The shadow region of the sidewall spacer material remains free of nitrogen atoms. The shadow region of the sidewall spacer material is converted into a sidewall spacer by isotropically etching away the nitrogenated regions, while not substantially etching the shadow region. The asymmetrically formed sidewall spacer can then be used to mask a portion of the substrate adjacent to the drain edge of the gate electrode.

Abstract: A semiconductor processing method of forming field isolation oxide relative to a silicon substrate includes, i) rapid thermal nitridizing an exposed silicon substrate surface to form a base silicon nitride layer on the silicon substrate; ii) providing a silicon nitride masking layer over the nitride base layer, the base and masking silicon nitride layers comprising a composite of said layers of a combined thickness effective to restrict appreciable oxidation of silicon substrate thereunder when the substrate is exposed to LOCOS conditions; and iii) exposing the substrate to oxidizing conditions effective to form field isolation oxide on substrate areas not masked by the base and masking silicon nitride layers composite.

Abstract: A dielectric interlayer is formed over a semiconductor substrate comprising at least one active region. The exposed upper surface of the dielectric interlayer is treated with nitrogen to form a nitrided barrier layer thereon. At least one hydrogen-containing dielectric layer is formed over the dielectric interlayer having the nitrided barrier layer thereon. The nitrided barrier layer serves as a barrier to diffusion of hydrogen from the at least one hydrogen-containing dielectric layer into the dielectric interlayer, thereby preventing a decrease in hot carrier injection reliability.

Abstract: The invention provides a method for fabricating ultra-shallow, low resistance junctions. In the preferred embodiment, a nitrogen containing screen oxide layer is formed on an undoped area of a substrate by poly re-oxidation using rapid thermal processing in a nitrogen containing atmosphere. Impurity ions are implanted into the substrate, in the undoped area, through the nitrogen containing screen oxide layer to form lightly doped source and drain regions. A post-implant anneal is performed on the lightly doped source and drain regions using a rapid thermal anneal in a nitrogen containing atmosphere. The nitrogen containing screen oxide layer: prevents surface dopant loss during post implant anneal; prevents gate oxide degradation during ion implantation and screen oxide stripping; and acts as a diffusion barrier, reducing oxygen enhanced diffusion. Alternatively, the poly re-oxidation can be performed in an O2 atmosphere followed by a rapid thermal anneal in a nitrogen containing atmosphere.

Abstract: A semiconductor wafer having an impurity diffusion layer formed in an inner surface of a trench is cleaned. The semiconductor wafer is inserted into a furnace, and NH3 gas is introduced into the furnace in the low-pressure condition to create an atmosphere in which the temperature is set at 800° C. to 1200° C. and the partial pressures of H2O and O2 are set at 1×10−4 Torr or less. A natural oxide film formed on the inner surface of the trench is removed, and substantially at the same time, a thermal nitride film is formed on the impurity diffusion layer. Then, a CVD silicon nitride film is formed on the thermal nitride film without exposing the thermal nitride film to the outside air in the same furnace. Next, a silicon oxide film is formed on the CVD nitride film. As a result, a composite insulative film formed of the thermal nitride film, CVD silicon nitride film and silicon oxide film is obtained. Then, an electrode for the composite insulative film is formed in the trench.

Abstract: This invention relates to the fabrication of integrated circuit devices and more particularly to an improved, graded, silicon oxynitride process step, in order to form an unconventional dielectric layer, having an adjustable effective dielectric constant, for the purpose of fabricating capacitors for both DRAM and Logic technologies. During the special CVD process for the oxynitride layer, its composition is varied such that three distinct regions are created in the direction of film growth. The dielectric property of the lower region is close to silicon oxide, the dielectric property of the upper region is close to silicon oxynitride and the dielectric property of the intermediate transition zone is between that of silicon oxide and oxynitride.

Abstract: A method of forming the gate structure of a MOS device forms a gate structure over a semiconductor substrate and then treats the sidewalls of the gate structure with nitrous oxide plasma so that the silicon and tungsten atoms within the gate structure can react with activated nitrogen in the plasma to form chemical bonds. Hence, a protective layer is formed on the gate sidewalls, thereby increasing thermal stability of the tungsten suicide layer and the polysilicon layer within the gate structure. Thereafter, an oxide material is formed over the protective layer using a rapid thermal oxidation. Next, spacers are formed over the sidewall oxide layer. Finally, subsequent operations necessary for forming a complete MOS device are performed.

Abstract: A capacitor in a semiconductor device is constituted by a lower electrode having a laminated layer including an adhesive layer formed on an insulating film, a barrier layer formed so as to cover the upper surface of the insulating layer, a nitride side formed so as to cover the side face of the adhesive layer, and an electrode layer formed so as to cover the upper surface of the barrier layer, a capacitor insulating film formed so as to cover the upper surface and side surface of the lower electrode, and an upper electrode formed so as to cover the surface of the capacitor insulating film.

Abstract: The present invention relates to the formation of an ILD layer while preventing or reducing oxidation of the upper surface of a metallic interconnect. Avoidance of oxidation of the upper surface of a metallic interconnect is achieved according to the present invention by passivating the exposed upper surface of the metallic interconnect prior to formation of the ILD. In order to avoid the oxidation of an upper surface of an interconnect during the formation of an ILD layer, an in situ passivation of the upper surface of the interconnect is formed immediately prior to or simultaneously with the formation of the ILD.

Abstract: In one aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen, the exposing not increasing a thickness of the silicon nitride layer by more than about 10 Angstroms. In another aspect, the invention includes a method of densifying a silicon nitride layer comprising: after forming the silicon nitride layer, exposing the silicon nitride layer to atomic nitrogen in the substantial absence of a silicon-containing gas.

Abstract: A method for depositing silicon nitride on a semiconductor wafer uses plasma enhanced chemical vapor deposition at very low temperatures. The temperature in a silicon nitride deposition chamber is set to be about 170.degree. C. or less. Silane gas (SiH.sub.4) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 300 sccm (standard cubic cm per minute) to about 500 sccm. Nitrogen gas (N.sub.2) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 500 sccm to about 2000 sccm. Ammonia gas (NH.sub.3) flows into the silicon nitride deposition chamber with a flow rate in a range of from about 1.0 slm to about 2.2 slm. A high frequency RF signal is applied on a showerhead within the deposition chamber. A low frequency RF signal is applied on a heating block for holding the semiconductor wafer.

Abstract: An embodiment of the instant invention is a method of forming a dielectric layer, the method comprising the steps of: providing a semiconductor substrate (substrate 12), the substrate having a surface; forming an oxygen-containing layer (layer 14) on the semiconductor substrate; and subjecting the oxygen-containing layer to a nitrogen containing plasma (plasma 16) so that the nitrogen is either incorporated into the oxygen-containing layer (see regions 18, 19, and 20) or forms a nitride layer at the surface of the substrate (region 22). Using this embodiment of the instant invention, the dielectric layer can be substantially free of hydrogen. Preferably, the oxygen-containing layer is an SiO.sub.2 layer or it is comprised of oxygen and nitrogen (preferably an oxynitride layer). The plasma is, preferably, a high-density plasma. Preferably, a source of nitrogen is introduced to the plasma to form the nitrogen containing plasma. The source of nitrogen is preferably comprised of a material consisting of: N.sub.

Abstract: The present invention is a method of fabricating void-free and volcano-free tungsten plugs. A silicon film was formed over contact hole surfaces for restricting the reflow of a dielectric layer. A titanium film is formed over the silicon layer. By performing a thermal process to the silicon layer and the titanium layer in a nitride-containing environment, the etching damage to the substrate can be recovered and a silicon silicide and a titanium nitride can be formed. The contact resistance of plugs can be significantly reduced, when compared with known technology. The undesired formation of voids and volcano can be eliminated. The method can be employed to fabricate defect-free advanced ULSI devices.

Abstract: A method for use in forming a memory cell dielectric includes providing a substrate surface of a memory cell including a silicon based electrode surface. Silicon is predeposited on the electrode surface followed by the deposition of a silicon nitride layer. An incubation time for the start of silicon nitride nucleation at the electrode surface is decreased relative to the incubation time for the start of silicon nitride nucleation when silicon nitride is deposited without predeposition of silicon on the electrode surface. Further, the substrate surface may include one or more component surfaces and when at least a monolayer of silicon is predeposited thereon silicon nitride nucleation at the substrate surface is performed at a substantially equivalent rate independent of the different component surfaces.

Abstract: A doped oxide and an undoped oxide are formed on a substrate. Then, the substrate is annealed to re-flow the doped oxide layer. The doped oxide is then etched back. Next, a contact hole is created by etching. An amorphous silicon layer is formed on the surface of the doped oxide layer and along the surface of the contact hole. Next, high temperature is used to recover the etching damage and simultaneously transform or convert the amorphous silicon into a polysilicon layer. A titanium layer and a titanium nitride are respectively formed onto the polysilicon layer. Next, rapid thermal process (RTP) is introduced to form a titanium silicide beneath the titanium nitride layer. A tungsten layer is formed on the titanium nitride layer and refilled into the contact hole. The tungsten layer is then etched back to form a tungsten plug with void-free in the contact hole. A conductive layer is formed on the titanium nitride layer.

Abstract: A first embodiment of the present invention introduces a method to cure mobile ion contamination in a semiconductor device during semiconductor processing by the steps of: forming active field effect transistors in a starting substrate; forming a first insulating layer over the field effect transistor and the field oxide; forming a second insulating layer over the first insulating layer; and performing an annealing step in a nitrogen containing gas ambient prior to exposing the insulating layer to mobile ion impurities. A second embodiment teaches a method to cure mobile ion contamination during semiconductor processing by annealing an insulating layer in a nitrogen containing gas ambient prior to exposing said insulating layer to mobile ion impurities.

Abstract: A method of fabricating metallization. A metal nitride layer is formed on the exposed surface of the metal layer. The metal nitride layer is used as a barrier layer to prevent short circuit, which is produced by metal diffusing into the inter-metal dielectrics. Therefore, the reliability of devices can be improved.

Abstract: A metal interconnection is formed on a dielectric layer. A pre-treatment is then performed to remove organic materials on the surface of the metal layer. The pre-treatment is done by plasma bombardment using NH.sub.3 and NO.sub.2 as the reaction gases. A thin oxide layer is subsequently deposited on the metal layer and on the dielectric layer. The oxide layer serves a buffer layer to eliminate the stress between the metal layer and subsequent silicon nitride layer. A silicon nitride layer is then formed on the thin oxide layer to act as a passivation layer.

Abstract: A method of fabricating a dielectric layer which is application to be used in a capacitor. A first conductive layer is provided. A nitridation step is performed on the first conductive layer, so that a nitride layer is formed on a surface of the first conductive layer. A dielectric layer with a high dielectric constant is formed, followed by a thermal treatment and an oxygen plasma treatment to terminate dangling bonds of the dielectric layer. Consequently, oxygen is distributed on a surface of the dielectric layer and bonded with dangling bonds of the dielectric layer distributed on the surface.

Abstract: The method of the present invention is a method to fabricate a MOS device without boron penetration. After growing a gate oxide layer, a thin stacked-amorphous-silicon layer (SAS) is deposited over the oxide layer. Subsequently, a lightly nitrogen ion is implanted into the stacked-amorphous silicon layer. The stacked-amorphous silicon layer is patterned to define a gate structure. Then, a light doped ion implantation is performed to dope ions through the gate oxide layer into the substrate to form lightly doped source and drain regions. A dielectric layer is formed over the gate structure and the gate oxide layer, and the dielectric layer is etched to form sidewall spacers. Next, a second ion implantation is performed to dope ions into the substrate to form source and drain. Finally, a thermal annealing is performed on the stacked-amorphous silicon gate and the substrate.

Abstract: The present invention relates generally to removing an undesirable second oxide, while minimally affecting a desirable first oxide, on an integrated circuit. The integrated circuit may be part of a larger system.The second oxide is first converted to another material, such as oxynitride. The other material has differing characteristics, such as etching properties, so that it can then be removed, without substantially diminishing the first oxide.The conversion may be accomplished by heating. Heating may be accomplished by rapid thermal or furnace processing. Subsequently, the other material is removed from the integrated circuit, for example by hot phosphoric etching, so that the desirable first oxide is not substantially affected.

Abstract: In accordance with an aspect of the invention, a semiconductor processing method of forming field effect transistors includes forming a first gate dielectric layer over a first area configured for forming p-type field effect transistors and a second area configured for forming n-type field effect transistors, both areas on a semiconductor substrate. The first gate dielectric layer is silicon dioxide having a nitrogen concentration of 0.1% molar to 10.0% molar within the first gate dielectric layer, the nitrogen atoms being higher in concentration within the first gate dielectric layer at one elevational location as compared to another elevational location. The first gate dielectric layer is removed from over the second area while leaving the first gate dielectric layer over the first area, and a second gate dielectric layer is formed over the second area. The second gate dielectric layer is a silicon dioxide material substantially void of nitrogen atoms.

Abstract: A method of making a semiconductor device includes a semiconductor substrate in which a semiconductor element is formed, an interlayer insulating film formed on the semiconductor substrate, an insulating barrier layer, formed on the interlayer insulating film by plasma nitriding, for preventing diffusion of a metal constituting a wiring layer, a conductive barrier layer, formed on the insulating barrier layer, for preventing diffusion of the metal, and a wiring layer formed of the metal on the conductive barrier layer. A bottom portion of the wiring layer is protected by the conductive barrier layer and the insulating barrier layer. Therefore, the diffusion of the metal constituting the wiring layer can be surely prevented.

Abstract: Provided are methods for fabricating hardened composite thin layer gate dielectrics. According to preferred embodiments of the present invention, composite gate dielectrics may be produced as bilayers having oyxnitride portions with nitrogen contents above 10 atomic percent, while avoiding the drawbacks of prior art nitridization methods. In one aspect of the present invention, a hardened composite thin layer gate dielectric may be formed by deposition of a very thin silicon layer on a very thin oxide layer on a silicon substrate, followed by low energy plasma nitridization and subsequent oxidation of the thin silicon layer. In another aspect of the invention, low energy plasma nitridization of a thin oxide layer formed on a silicon substrate may be followed by deposition of a very thin silicon layer and subsequent oxidation, or additional low energy plasma nitridization and then oxidation, of the thin silicon layer.

Abstract: Dual gate oxide layer thicknesses are achieved by depositing a thin blocking layer on active regions of a semiconductor substrate, such as silicon nitride, oxynitride, or oxide. Selected active regions are nitridated through a patterned photoresist mask formed thereon. The blocking layer protects the substrate from the photoresist mask and enables nitriding, as by ion implantation, plasma exposure, or rapid thermal annealing.

Abstract: A method of forming silicon nitride includes, a) forming a first layer comprising silicon nitride over a substrate; b) forming a second layer comprising silicon on the first layer; and c) nitridizing silicon of the second layer into silicon nitride to form a silicon nitride comprising layer, said silicon nitride comprising layer comprising silicon nitride of the first and second layers. Further, a method of forming a capacitor dielectric layer of silicon nitride includes, a) forming a first capacitor plate layer; b) forming a first silicon nitride layer over the first capacitor plate layer; c) forming a silicon layer on the silicon nitride layer; d) nitridizing the silicon layer into a second silicon nitride layer; and e) forming a second capacitor plate layer over the second silicon nitride layer.

Abstract: A integrated circuit transistor that has a high nitrogen concentration in the channel region and a method of making same are provided. A sacrificial oxide layer integrated with a nitrogen bearing species is grown on the substrate. A portion of the nitrogen bearing species diffuses into the substrate to form a nitrogen doped region. Nitrogen is implanted through the first oxide layer to increase the peak concentration of nitrogen in the nitrogen doped region. The sacrificial oxide layer is removed and a very thin gate oxide layer is formed. A gate, a source, and a drain are formed. The result is an integrated circuit transistor with a very thin gate oxide layer and a high peak concentration of nitrogen substantially at the Si--SiO.sub.2 interface.

Abstract: Copper or copper alloy interconnection patterns are formed with improved barrier layer protection against copper diffusion. A damascene opening is formed in a dielectric layer and a barrier layer is deposited lining the damascene opening and on the dielectric layer. Embodiments include forming a nitride barrier layer with a plasma generated in a chamber containing a shutter which prevents sputtered atoms from impinging on the dielectric layer. The shutter is then opened to allow a metal layer, e.g., Al, Mg or an alloy thereof, to be sputter deposited on the nitride layer in the chamber. Copper or a copper alloy is then deposited to fill the opening, as by electroplating or electroless plating.

Abstract: A method of manufacturing a semiconductor device comprises the step of applying a nitridation treatment to a semiconductor substrate in the presence of a network terminal element so as to form a nitride film containing the network terminal element on the semiconductor substrate.

Abstract: In forming a storage node with sidewalls on interlayer dielectric layer of a semiconductor device, the interlayer dielectric layer having an uppermost silicon oxide film, a silicon nitride film is formed as a protective film on the storage node of poly-silicon formed on the interlayer dielectric layer, and thereafter a poly-silicon layer is deposited and then subjected to an anisotropic etching to partially remove the polysilicon layer to remain, as the side walls, portions of the poly-silicon layer on side surfaces of the storage node, with protecting the storage node by the protective film from the etching and without etching the uppermost silicon oxide film. Alternatively, the uppermost silicon oxide film is subjected to a nitrogen plasma treatment before forming the storage node, and a silicon oxide film can be used as the protective film. The storage node with the side walls can be used as a lower electrode of a stack type capacitor in the semiconductor device after removing the protective film.

Abstract: A CMOS integrated circuit having a PMOS and NMOS device with different gate dielectric layers. According to the present invention, an NMOS transistor is formed on a p-type conductivity region of a semiconductor substrate. The NMOS transistor has first gate dielectric layer formed on the p-type conductivity region. A PMOS transistor is formed on a n-type conductivity region of the semiconductor substrate. The PMOS transistor has a second gate dielectric layer wherein the second gate dielectric layer has a different composition than the first gate dielectric layer.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) silicon-oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium silicon-oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium silicon-oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide. However, the zirconium silicon-oxynitride gate dielectric may also be designed to have the advantages of silicon dioxide, e.g. high breakdown, low interface state density, and high stability.

Abstract: A field effect semiconductor device comprising a high permittivity zirconium (or hafnium) oxynitride gate dielectric and a method of forming the same are disclosed herein. The device comprises a silicon substrate 20 having a semiconducting channel region 24 formed therein. A zirconium oxynitride gate dielectric layer 36 is formed over this substrate, followed by a conductive gate 38. Zirconium oxynitride gate dielectric layer 36 has a dielectric constant is significantly higher than the dielectric constant of silicon dioxide.

Abstract: A method for adjusting the amount of doped nitride ions in a dielectric layer so that the nitride ions form bonds with silicon to increase the quality of an oxide layer. The method comprises the step of providing a silicon substrate. Next, a rapid thermal oxidation or furnace oxidation method is used to form an oxide layer over the silicon substrate. Gaseous mixtures having different ratios of nitrogen monoxide, nitrous oxide or ammonia to oxygen are concocted and then allowed to react at different reacting temperatures for controlling the nitride concentration level in the oxide layer. The nitride-doped oxide layer not only can stop the penetration of boron ions, but can also provide a stabilizing effect on the oxide layer/silicon substrate interface without degradation of electrical property, thereby improving the quality of a transistor.

Abstract: A semiconductor device fabrication process in which an oxynitride layer and a polysilicon layer are formed in the same reaction chamber is provided. In accordance with one embodiment of the invention, a semiconductor device is formed by forming, in a reaction chamber, an oxynitride layer on a surface of a substrate and forming, in the same reaction chamber, a polysilicon layer over the oxynitride layer. The oxynitride layer may be used to form a gate oxide and the polysilicon layer used to form a gate electrode.

Abstract: The invention comprises a method of forming a semiconductor device is provided where a first gate insulator layer 26 is formed on an outer surface of semiconductor substrate 24. A mask body 28 is formed to cover portions of the insulator layer 26. The exposed portions of the layer 26 are subjected to a nitridation process to form a nitride layer 30. A second oxidation process forms a thick gate oxide layer 32. The nitride layer 30 inhibits the growth of oxide resulting in a single integrated device having gate insulator layers having two different thicknesses such that high voltage and low voltage transistors can be formed on the same integrated circuit.

Abstract: A method for fabricating a semiconductor device with a multi-level insulator formed on a semiconductor substrate is provided, which enables restraint of impurity atoms doped into a material contacted with the insulator from diffusing into the insulator and substrate. A first dielectric film formed on the substrate is made of an oxide of a semiconductor constituting the substrate by thermal treatment of the substrate in an oxygen atmosphere. The second dielectric film is disposed at the interface of the substrate and first dielectric and is made of a nitride or oxynitride of the semiconductor constituting the substrate by thermal treatment of the substrate and first dielectric in a nitride atmosphere. The insulator preferably contains only the first and second dielectric films to have a two-level structure. The insulator may further contain a third dielectric film formed over the multi-level structure, thereby having a three-level insulator structure.

Abstract: A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.