Abstract: The formation of a barrier layer over a high k dielectric layer and deposition of a conducting layer over the barrier layer prevents intermigration between the species of the high k dielectric layer and the conducting layer and prevents oxygen scavenging of the high k dielectric layer. One example of a capacitor stack device provided includes a high k dielectric layer of Ta2O5, a barrier layer of TaON or TiON formed at least in part by a remote plasma process, and a top electrode of TiN. The processes may be conducted at about 300 to 700° C. and are thus useful for low thermal budget applications. Also provided are MIM capacitor constructions and methods in which an insulator layer is formed by remote plasma oxidation of a bottom electrode.

Abstract: A method for using CVD oxynitride and BTBAS nitride during the sidewall formation process in MOS transistor fabrication processes. A silicon oxynitride layer (110) and a silicon nitride layer (120) are used to form sidewalls for MOS transistors. The silicon nitride layer (120) is formed using BTBAS processes.

Abstract: The present invention relates to a semiconductor device manufacturing method for forming an interlayer insulating film having a low dielectric constant by coating a copper wiring. The low dielectric constant insulating film is formed by reaction of a plasma of a film-forming gas containing an oxygen-containing gas of N2O, H2O, or CO2, ammonia (NH3), and at least one of an alkyl compound having a siloxane bond and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3).

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract: An apparatus and method for processing a microelectronic substrate comprises a main chamber and a movable boundary. The main chamber comprises a main chamber wall enclosing a main chamber interior. The movable boundary is disposed within the main chamber interior, and is movable between a first position and a second position. At the first position, the movable boundary at least partially defines a sub-chamber in which a substrate can be processed. The sub-chamber is fluidly isolated from the main chamber interior, and provides an environment suitable for a high-pressure processing of the substrate such as cleaning or surface preparation. The sub-chamber can be maintained at a high pressure while the main chamber is maintained at either a low pressure, an atmospheric pressure, or at a vacuum. The apparatus can be directly coupled to an external substrate handling and/or fabrication module, such that the main chamber interior provides a buffer between the sub-chamber and the external module.

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: The present invention relates to a process for vapor depositing a low dielectric insulating film, and more particularly to a process for vapor deposition of low dielectric insulating film that can significantly improve a vapor deposition speed while maintaining properties of the low dielectric insulating film, thereby solving parasitic capacitance problems to realize a high aperture ratio structure, and can reduce a process time by using silane gas when vapor depositing an insulating film by a CVD or PECVD method to form a protection film for a semiconductor device.

Abstract: A structure to enable damascene copper semiconductor fabrication is disclosed. There is a silicon nitride film for providing a diffusion barrier for Cu as well as an etch stop for the duel damascene process. Directly above the silicon nitride film is a silicon oxynitride film. The silicon oxynitride film is graded, to form a gradual change in composition of nitrogen and oxygen within the film. Directly above the silicon oxynitride film is silicon oxide. The silicon oxide serves as an insulator for metal lines. Preferably, the film stack of silicon nitride, silicon oxynitride and silicon oxide is all formed in sequence, within the same plasma-processing chamber, by modifying the composition of film-forming gases for forming each film.

Abstract: A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

Abstract: An integrated circuit and manufacturing method therefor is provided having a semiconductor substrate with a semiconductor device. A dielectric layer formed over the semiconductor substrate has an opening provided therein. The dielectric layer is of non-barrier dielectric material capable of being changed into a barrier dielectric material. The dielectric layer around the opening is changed into the barrier dielectric material and the conductor core material is deposited to fill the opening. The conductor core is processed to form a channel for the integrated circuit.

Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate.

Abstract: A method of forming an interlayer insulation film on a semiconductor substrate using plasma CVD includes introducing a source gas into a reaction chamber, applying radio-frequency power after the source gas is brought in, introducing an oxidizing gas with or without an additive gas into the reaction chamber after the completion of supplying the source gas and applying the radio-frequency power, and applying the radio-frequency power again. The concentration of the oxidizing gas may be 0.3% or higher and a processing time period by the oxidizing gas may be three seconds or longer.

Abstract: A lower electrode of a capacitor which has uneven surface formed by using HSG-Si (hemispherical grained silicon) and which is used, for example, in a semiconductor device such as DRAM device. Such lower electrode is fabricated as follows. An insulating film is formed on a semiconductor substrate, and a silicon film is formed on the insulating film. Then, the silicon film is selectively patterned to pattern it. The semiconductor substrate is heated to remove moisture in the insulating film. An oxide film on the surface of the silicon film is then removed. Thereafter, silicon nuclei are formed on the surface of the silicon film by heating the semiconductor substrate in atmosphere containing silicon compound gas. The silicon nuclei are then grown and thereby a lower electrode is formed which has hemispherical grains on the surface thereof.

Abstract: A interconnection structure of the damascene type is produced on a surface of a microelectronic device that includes at least one dielectric material layer for housing at least one interconnection and at least one interface layer on the dielectric material layer. The interface layer may include at least one SiCH layer and at least one SiOCH layer.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: The invention includes a method for treating a plurality of discrete semiconductor substrates. The discrete semiconductor substrates are placed within a reactor chamber. While the substrates are within the chamber, they are simultaneously exposed to one or more of H, F and Cl to remove native oxide. After removing the native oxide, the substrates are simultaneously exposed to a first reactive material to form a first mass across at least some exposed surfaces of the substrates. The first reactive material is removed from the reaction chamber, and subsequently the substrates are exposed to a second reactive material to convert the first mass to a second mass. The invention also includes apparatuses which can be utilized for simultaneous ALD treatment of a plurality of discrete semiconductor substrates.

Abstract: A method of using dichloroethene and ammonia to provide chlorine and nitrogen during the growth of an in-situ hardened gate dielectric. The method provides a gaseous source of gettering agent and a gaseous source of dielectric strengthening agent that are compatible with each other and can be used during the formation of in-situ hardened dielectric or the strengthening of an already formed dielectric.

Abstract: A method for reducing oxidation encroachment of stacked gate layer is provided by forming a silicon oxynitride layer on the sidewall surface of the stacked gate layer. A tilted ion implantation step is performed to implant nitrogen ions into the sidewall surface of the stacked gate layer to rich nitrogen containing in the sidewall surface of the stacked gate layer. An oxygen-annealing step is subsequently performed to form a silicon oxynitride layer on the sidewall surface of the stacked gate layer. The silicon oxynitride layer can prevent the polysilicon layer in the stacked gate layer being continuously encroached from the oxygen.

Abstract: Planarization of the top surfaces of layers that are more than about a micron thick is beset with problems not encountered in thinner layers. These problems have been overcome by means of a process that, initially allows the formation of ‘horns’ in the surface that is to be planarized. Said horns are then selectively etched away while other parts of the surface are protected, following which CMP is initiated and the surface gets planarized. A total of four embodiments are disclosed.

Abstract: A process is disclosed for forming an integrated circuit structure characterized by formation of a combined dielectric layer and antireflective coating layer. The process comprises forming a layer of dielectric material over an integrated circuit structure, and treating the surface of the layer of dielectric material to form an antireflective coating (ARC) surface therein. When a layer of photoresist is then formed over the ARC surface, and the layer of photoresist is exposed to a pattern of radiation, the ARC surface improves the accuracy of the replication, in the photoresist layer, of the pattern of radiation. Preferably, the surface of the dielectric layer is treated with a plasma comprising ions of elements and/or compounds to form the ARC surface.

Abstract: Methods are provided herein for treating substrate surfaces in preparation for subsequent nucleation-sensitive depositions (e.g., polysilicon or poly-SiGe) and adsorption-driven deposition (e.g. atomic layer deposition or ALD). Prior to depositing, the surface is treated with non-depositing plasma products. The treated surface more readily nucleates polysilicon and poly-SiGe (such as for a gate electrode), or more readily adsorbs ALD reactants (such as for a gate dielectric). The surface treatment provides surface moieties more readily susceptible to a subsequent deposition reaction, or more readily susceptible to further surface treatment prior to deposition. By changing the surface termination of the substrate with a low temperature radical treatment, subsequent deposition is advantageously facilitated without depositing a layer of any appreciable thickness and without significantly affecting the bulk properties of the underlying material.

Abstract: A method for utilizing a rough insulator to enhance metal-insulator-semiconductor reliability is provided. The method includes steps of: (a) providing a semiconductor substrate; (b) prebaking the semiconductor substrate under a relatively high vacuum to form a rough surface on the semiconductor substrate; and (c) growing an insulator on the semiconductor substrate to form a rough insulator and increase the metal-insulator-semiconductor reliability when the insulator is applied.

Abstract: One aspect of the invention relates to forming a high-k dielectric layer comprising a Group IVB metal compound, especially HfO2, HfSixOy or HfSixOyNz. According to the invention, these compounds are formed by molecular layer deposition. According to another aspect of the invention, molecular layer deposition is used to add silicon oxynitride to the dielectric. The silicon oxynitride provides a barrier to diffusion of dopants from the gate to the channel region.

Abstract: There is disclosed a method of manufacturing a semiconductor device, wherein a thin film containing a metal and capable of bonding with oxygen is deposited on a silicon substrate, a metal oxide film is formed on the thin film, and the thin film is oxidized by heat treatment to form a gate insulating film comprising the oxidized thin film and the metal oxide film.

Abstract: A method for providing a dielectric film having a low dielectric constant. The deposited film is particularly useful as an intermetal or premetal dielectric layer in an integrated circuit. The low dielectric constant film is a carbon-doped silicon oxide layer deposited from a thermal, as opposed to plasma, CVD process. The layer is deposited from a process gas of ozone and an organosilane precursor having at least one silicon-carbon (Si—C) bond. During the deposition process the wafer is heated to a temperature less than 250° C. and preferably to a temperature between 100-200° C. Enhancements to the process include adding Boron and/or Phosphorus dopants, two step deposition, and capping the post cured layer.

Abstract: A method for scaling down thickness of ONO film with remote plasma nitridation, the method includes the acts of forming a substrate; form a first oxide layer on the substrate; nitrogenizing the oxide layer under the ONO film to form a nitridation layer; forming a nitride layer on the nitridation layer; and forming a second oxide layer on the nitride layer.

Abstract: A shallow junction EEPROM device and process for fabricating the device includes the formation of a control-gate region and a tunnel region in a semiconductor substrate in which the control-gate region has a substantially higher total doping concentration than the tunnel region. To compensate for rate enhanced oxidation of the silicon surface overlying the control-gate region, nitrogen is selectively introduced into the control-gate region, such that the resulting dielectric layer thickness overlying the control-gate region is substantially the same as that overlying the tunnel region. The relatively high doping concentration of the control-gate region enables fabrication of an EEPROM device having high capacitance coupling, shallow junctions, and a relatively small capacitor area.

Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.

Abstract: A method of forming a low dielectric constant film. The low dielectric constant film is formed by passing gaseous silane into a reaction chamber and performing a plasma chemical vapor deposition to form a carbon-rich layer. Micro-particles deposited on the dielectric film are purged by ammonia. By adjusting the flow rate of ammonia, and the pressure and plasma density inside the reaction chamber, several ammonium plasma conditions are produced in sequence to clear the particles on the dielectric film.

Abstract: A method of forming an oxide film with resistance to erosion caused by a stripper during removal of a photoresist layer. First, a substrate is provided with a polysilicon gate layer. Then, using LPCVD, an LP-oxide film is formed on the substrate to cover the polysilicon gate layer. Then, using annealing treatment with a gas containing a nitrogen element, a surface layer with an oxynitride composition is formed on the oxide film.

Abstract: A method and apparatus for directing a process gas through a processing apparatus, such as a vapor deposition chamber. The apparatus comprises a pumping plate for a processing chamber having an annular body member wherein said body member has a first portion and a second defining a circumferential edge and a central opening. The first portion comprises a sidewall of the circumferential edge having a plurality of circumferentially spaced through holes and the second portion has comprises a lateral portion that protrudes from the circumferential edge, such that, in a processing chamber, the first portion defines a first gas flow region comprising the central opening and a second gas flow region comprising the lateral portion of the second portion.

Abstract: Provided with a method for forming conductive lines in a semiconductor device including the steps of: (a) forming a first conductive line on a substrate; (b) forming a first insulating layer on the substrate as well as on the first conductive line; (c) etching the first insulating layer on the first conductive line to form a first opening; (d) forming a second insulating layer on the first insulating layer to be in contact with the upper part of the first opening, thereby sealing the first opening; (e) etching the first and second insulating layers corresponding to the first conductive line to form a second opening and at the same time extend the first opening so as to expose the first conductive line; and (f) forming a second conductive line within the first and second openings so as to be connected with the first conductive line, thereby preventing halation caused by irregular reflection during exposure on the second photo resist because the second insulating layer has a less difference in thickness, and su

Abstract: Degradation of fluorine-doped silica glass low-k inter-layer dielectrics during fabrication is significantly reduced and resolution of submicron features is improved by the formation of dual nature capping/ARC layers on inter-layer dielectric films. The capping/ARC layer is formed in-situ on a fluorine-doped silica glass inter-layer dielectric. The in-situ formation of the capping/ARC layer provides a strongly adhered capping/ARC layer, formed with fewer processing steps than conventional capping and ARC layers.

Abstract: In fabricating a semiconductor device, a hydrogen-containing first insulating film is formed over a semiconductor layer, a gate insulating film and a gate electrode, and a first heat-treatment in a hydrogen atmosphere is performed. A second insulating film can be formed on the first insulating film, and a second heat-treatment in a hydrogen atmosphere performed. A hydrogen-containing third insulating film can be formed on the second insulating film, and a third heat-treatment in an atmosphere containing hydrogen or nitrogen performed. By these methods, damages to a semiconductor layer caused by hydrogenation can be avoided.

Abstract: A method of manufacturing a semiconductor device in which a thin film is formed on a semiconductor substrate using a reaction gas described in the present invention as active species is disclosed, where a film formation process is subdivided into multiple stages and a film is formed by varying the gas pressure or the gas flow speed of the active species within a reaction chamber for each stage.

Abstract: A method for preventing electron secondary injection in a pocket implantation process performed on a nitride read only memory (NROM). The NROM has an oxide-nitride-oxide (ONO) layer formed on a silicon substrate. A plurality of bit line masks, arranged in a column, is formed on the surface of the ONO layer. A plurality of N type bit lines is formed in a region of the substrate not covered by the bit line masks. The method starts by performing a pocket implantation process of Indium ions with low energy, high dosage and using an angle nearly parallel to the ONO layer, so as to prevent electron secondary injection. Also, a plurality of P-type ultra-shallow junctions is formed in the region of the substrate not covered by the bit line masks.

Abstract: The present invention discloses a method for forming a layer of nitrogen and silicon containing material on a substrate by first providing a heated substrate and then flowing a gas which has silicon and nitrogen atoms but no carbon atoms in the same molecule over said heated substrate at a pressure of not higher than 500 Torr, such that a layer of nitrogen and silicon containing material is formed on the surface. The present invention is further directed to a composite structure that includes a substrate and a layer of material containing nitrogen and silicon but not carbon overlying the substrate for stopping chemical species from reaching the substrate. The present invention is further directed to a structure that includes a semiconducting substrate, a gate insulator on the substrate, a nitrogen-rich layer on top of the gate insulator, and a gate electrode on the nitrogen-rich layer, wherein the nitrogen-rich layer blocks diffusion of contaminating species from the gate electrode to the gate insulator.

Abstract: A capacitor and a capacitor dielectric material are fabricated by adjusting the amount of an ionic conductive species, such as hydrogen, contained in the capacitor dielectric material to obtain predetermined electrical or functional characteristics. Forming the capacitor dielectric material from silicon, nitrogen and hydrogen allows a stoichiometric ratio control of silicon to nitrogen to limit the amount of hydrogen. Forming the capacitor by dielectric material plasma enhanced chemical vapor deposition (PECVD) allows hydrogen bonds to be broken by ionic bombardment, so that stoichiometric control is achieved by controlling the power of the PECVD. Applying a predetermined number of thermal cycles of temperature elevation and temperature reduction also breaks the hydrogen bonds to control the amount of the hydrogen in the formed capacitor dielectric material.

Abstract: A first wiring layer is formed on an insulating film. The first wiring layer is formed by sequentially laminating a barrier layer, an Al alloy layer, and an antireflection layer. The antireflection layer is formed by sequentially laminating a Ti layer, a TiN layer, and a TiON layer. After an interlayer insulating film is formed on the first wiring layer, a contact hole is formed through the interlayer insulating film and a tight adhesion layer is formed on an inner surface of the contact hole. The tight adhesion layer is formed by sequentially laminating a Ti layer, a TiN layer, a TiON layer, and a TiN layer. A W plug is embedded in the contact hole through CVD using WF6. Thereafter, an Al alloy layer and an antireflection layer are sequentially deposited and patterned to form a second wiring layer.

Abstract: A gate insulation film includes nitrogen, oxygen and silicon as constituent elements thereof. The nitrogen concentration profile of the gate insulation film in the thickness direction has a maximum concentration in the vicinity of the top surface of the gate insulation film and substantially zero concentration in the vicinity of the silicon substrate. The specified nitrogen profile is obtained by a steep rising slope and a relatively steep falling slope of the temperature profile with time in the step of nitriding a silicon oxide film to form a silicon oxynitride film.

Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.

Abstract: A method of forming a silicon carbide layer for use in integrated circuits is provided. The silicon carbide layer is formed by reacting a gas mixture comprising a silicon source, a carbon source, and a nitrogen source in the presence of an electric field. The as-deposited silicon carbide layer incorporates nitrogen therein from the nitrogen source.

Abstract: A process used to retard out diffusion of P type dopants from P type LDD regions, resulting in unwanted LDD series resistance increases, has been developed. The process features the formation of a nitrogen containing layer, placed between the P type LDD region and overlying silicon oxide regions, retarding the diffusion of boron from the LDD regions to the overlying silicon oxide regions, during subsequent high temperature anneals. The nitrogen containing layer, such as a thin silicon nitride layer, or a silicon oxynitride layer, formed during or after reoxidation of a P type polysilicon gate structure, is also formed in a region that also retards the out diffusion of P type dopants from the P type polysilicon gate structure.

Abstract: The novel method allows monitoring of nitrogen processes by making use of the fact that the incorporation of nitrogen near the surface in silicon, or in a thin silicon nitride layer on the silicon surface, inhibits the diffusion of oxygen during the subsequent thermal oxidation. Accordingly, the oxidation rate of the thermal oxidation is reduced and the growth of the oxide layer on the silicon surface is inhibited. The thickness of the oxide layer is thus used as a measure for the nitrogen content, i.e., for the quality of the nitrogen process.

Abstract: The present invention relates to a method of forming an insulating film in a semiconductor device by which the composition and the doping concentration of oxide are controlled using an atomic layer deposition method. In case of silicon oxide, a thermal oxidization process and a deposition process are sequentially performed to form an oxide film having a good interface characteristic and the deposition speed. On the other hand, in case of depositing an oxide film, an oxynitride film and a metal oxide film, the pulse construction and the supply time of a source and radical are adjusted to form an optimum oxide film having a good interface characteristic.

Abstract: A relatively thin gate insulator of a digital switching transistor is formed from a layer of silicon oxynitride which was initially formed by implanting nitrogen atoms in a silicon substrate and oxidizing the nitrogen and silicon. It has been discovered that an outer layer of silicon dioxide is formed as a part of the silicon oxynitride layer. Removing this outer layer of silicon dioxide from the silicon oxynitride layer leaves a thin remaining layer of substantially-only silicon oxynitride as the gate insulator. Thinner gate insulators of approximately 15-21 angstroms, for example, can be formed from a grown thickness of 60 angstroms, for example. Gate insulators for digital and analog transistors may be formed simultaneously with a greater differential in thickness been possible by using conventional nitrogen implantation techniques.

Abstract: A method of forming an integrated circuit using a fluoro-organosilicate layer is disclosed. The fluoro-organosilicate layer is formed by applying an electric field to a gas mixture comprising a fluoro-organosilane compound and an oxidizing gas. The fluoro-organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the fluoro-organosilicate layer is used as a hardmask. In another integrated circuit fabrication process, the fluoro-organosilicate layer is incorporated into a damascene structure.