Abstract: A process for producing a nitrided oxide layer on a silicon semiconductor substrate includes introducing a multiplicity of wafers into an atmospheric batch furnace, carrying out an oxidation step at a first predetermined temperature, carrying out a nitriding step at a second predetermined temperature, and carrying out a reoxidation step at a third predetermined temperature. The wafers are then cooled and removed from the atmospheric batch furnace.

Abstract: Dual-Damascene processes for difficult to etch low k dielectric such as carbon-doped oxide. First deposition of dielectric is made to thickness of vias only, then etched. Second depositions of dielectric is made to thickness of conductor and then etched.

Abstract: A method for forming an ultra thin gate dielectric for an integrated circuit device is disclosed. In an exemplary embodiment of the invention, the method includes forming an initial nitride layer upon a substrate by rapidly heating the substrate in the presence of an ammonia (NH3) gas, and then re-oxidizing the initial nitride layer by rapidly heating the initial nitride layer in the presence of a nitric oxide (NO) gas, thereby forming an oxynitride layer. The oxynitride layer has a nitrogen concentration therein of at about 1.0×1015 atoms/cm2 to about 6.0×1015 atoms/cm2, and has a thickness which may be controlled within a sub 10 Å range.

Abstract: An improved gate structure for a MOSFET device exhibits a reduced level of 1/f noise or “flicker noise”, while maintaining the control of boron penetration into the substrate of the MOSFET device. The gate structure for the MOSFET device includes a gate electrode and a gate oxide layer wherein nitrogen is selectively implanted into the gate oxide/device substrate interface prior to oxidation of the gate oxide layer. The nitrogen is selectively implanted so that the nitrogen is implanted into thin gate oxide regions and masked from thick gate oxide regions so that the benefits of controlling the boron penetration are realized while the 1/f noise is reduced due to the selective implantation of the nitrogen.

Abstract: A method of forming a semiconductor device by forming a first interlayer insulation film on a substrate, forming a second, organic interlayer insulation film on the first interlayer insulation film, forming a first etching stopper film on the second interlayer insulation film, and forming a second, different etching stopper film on the first etching stopper film. A first opening is formed in the second etching stopper film so as to expose the first etching stopper film, a second opening is formed in a part of the first etching stopper film exposed by the first opening, and a third opening is formed in the second interlayer insulation film in correspondence to the second opening by applying an etching process while using the first etching stopper film as a mask. An interconnection groove is then formed in the second interlayer insulation film in correspondence to the first opening by applying an etching process while using the second etching stopper film as a mask.

Abstract: A method of making a semiconductor device including a metal gate electrode on a semiconductor substrate with a silicon oxynitride spacer formed on a surface of the metal gate electrode, wherein an interface of the silicon oxynitride spacer and the metal gate electrode is substantially free of metal silicide. The process includes steps of forming a metal gate electrode on a semiconductor substrate; forming by PECVD on a surface of the metal gate electrode a silicon oxynitride spacer, wherein the silicon oxynitride spacer is formed under initially silicon-starved conditions in which a first quantity of at least one silicon-containing material is provided to a PECVD apparatus which is reduced relative to an amount of at least one other reactant, as a result of which substantially no silicide is formed.

Abstract: A method for protecting selected first surfaces on a semiconductor substrate during application of a second oxide layer to said substrate comprising applying an oxidation barrier layer as a mask over said selected first surfaces, prior to patterning said semiconductor substrate with a resist mask and applying said second oxide layer.

Abstract: An oxynitride material is used to form shallow trench isolation regions in an integrated circuit structure. The oxynitride may be used for both the trench liner and trench fill material. The oxynitride liner is formed by nitriding an initially formed oxide trench liner. The oxynitride trench fill material is formed by directly depositing a high density plasma (HDP) oxide mixture of SiH4 and O2 and adding a controlled amount of NH3 to the plasma mixture. The resultant oxynitride structure is much more resistant to trench fill erosion by wet etch, for example, yet results in minimal stress to the surrounding silicon. To further reduce stress, the nitrogen concentration may be varied by varying the proportion of O2 to NH3 in the plasma mixture so that the nitrogen concentration is maximum at the top of the fill material.

Abstract: A technique for controlling the oxidation of silicon is achieved by applying low temperature ammonia prior to the oxidation. The result is that the subsequent oxidation of the silicon is at a slower oxidation rate and higher nitrogen content. The higher nitrogen content is particularly beneficial for a gate dielectric because it acts as somewhat of a boron barrier and provides additional resistance to unwanted oxidation. The result is transistors with improved gate dielectric thickness uniformity across a wafer for a tighter threshold voltage distribution, reduced shift in threshold voltage, and improved time to breakdown.

Abstract: There is provided a wafer transfer method, by which, when a wafer is loaded into a system, heat shock applied to the wafer can be relieved, the frequency of occurrence of crystal dislocation such as slip can be decreased, and productivity can be improved due to saving of energy and time required for heating and cooling of the system, and there is also provided a wafer support member used for this method. In this method, a step for transferring wafers so as to replace a wafer, which finishes its thin film growth process, with a following wafer, which is to be subjected to its thin film growth process, is carried out under the temperature being higher than the room temperature, while the wafer 1 is transferred integrally with a wafer support member 2 used for the thin film growth process.

Abstract: A semiconductor device manufacturing method including a step of forming, by thermal chemical vapor deposition, silicon nitride films on a plurality of substrates vertically stacked in a vertical reaction tube having an inner wall. Bis tertiary butyl amino silane and NH3 flows into the vertical reaction tube and flows vertically from one end of the plurality of substrates to an opposing end of the plurality of substrates without flowing into the vertical reaction tube through the inner wall at a height between the one end and the opposing end of the plurality of substrates. The silicon nitride films are formed on the plurality of substrates in a state in which a distance “a” between adjacent substrates of the plurality of substrates and a distance “b” between edges of the plurality of substrates and the inner wall of the vertical reaction tube are maintained substantially equal to each other.

Abstract: Reactive ion etch (RIE) selectivity during etching of a feature nearby embedded structure is improved by using a silicon oxynitride layer formed with carbonization throughout layer.

Abstract: A nickel silicide layer is formed on a semiconductor device having a crystalline silicon source/drain region doped with arsenic. Arsenic is doped into the crystalline silicon, by implantation, for example, so that the concentration of arsenic is slightly below the surface of the silicon. Annealing restores the crystalline structure of the silicon after implantation of the arsenic. Amorphous silicon is selectively deposited over the source/drain regions and over the top of the gate electrode. Nickel is deposited over the entire semiconductor device and a second anneal reacts the nickel with the amorphous silicon. The second anneal is timed so that the nickel reacts with the amorphous silicon, and does not substantially react with the silicon source/drain regions containing arsenic. Preventing the nickel from substantially reacting with the silicon source/drain regions containing arsenic provides a smooth interface between the resulting nickel silicide and the silicon source/drain regions doped with arsenic.

Abstract: A method for producing fluorinated hydrogenated silicon oxycarbide (H:F:SiOC) and amorphous fluorinated hydrogenated silicon carbide (H:F:SiC) films having low dielectric permittivity. The method comprises reacting a silicon containing compound with a fluorocarbon or fluorohydrocarbon compound having an unsaturated carbon bonded to F or H. The resulting films are useful in the formation of semiconductor devices.

Abstract: The present invention fabricates an oxide-nitride-oxide (ONO) layer of an NROM. A first oxide layer is formed on the surface of the substrate of a semiconductor wafer. Then two CVD processes are performed to respectively form a first nitride layer and a second nitride layer on the surface of the first oxide layer, and the boundary between the second nitride layer and the first nitride layer is so forming an interface. Thereafter, a second oxide layer is formed on the surface of the second nitride layer completing the process of manufacturing the ONO layer. The second nitride layer and the first nitride layer are used as a floating gate of the NROM, and the interface is used as a deep charge trapping center to improve the charge trapping efficiency, and furthermore, to improve the endurance and reliability of the NROM.

Abstract: Disclosed is a method for producing a circuit structure having an insulator layer comprising a porous silicon oxide thin film, which comprises (1) forming a preliminary insulator layer comprising a silicon oxide-organic polymer composite thin film formed on a substrate, which silicon oxide-organic polymer composite thin film comprises a silicon oxide having an organic polymer dispersed therein, (2) forming, in the preliminary insulator layer, a groove which defines a pattern for a circuit, (3) forming, in the groove, a metal layer which functions as a circuit, and (4) removing the organic polymer from the preliminary insulator layer to render the preliminary insulator layer porous, thereby converting the preliminary insulator layer to an insulator layer comprising a porous silicon oxide thin film. By the method of the present invention, the capacitance between mutually adjacent circuit lines (line-to-line capacitance) in the circuit structure can be lowered.

Abstract: The present invention provides a method improving the adhesion between inter metal dielectric (IMD) layers by performing a HF dip etch to treat the surface of an oxide, silicon nitride or Silicon oxynitride insulating layer before an overlying low-K layer is formed. The present invention provides a method of fabricating a low-K IMD layer 20 over an oxide, Silicon oxynitride (SiON), or nitride IMD layer 14 with improved adhesion. First, a 1st inter metal dielectric (IMD) layer 14 is formed over a substrate. Next, the invention's novel HF dip etch is performed on the 1st IMD layer 14 to form a treated surface 16. Next, a 2nd BMD layer composed of a low-K material is formed over the rough surface 16 of the 1st IMD layer 14. The treated surface 16 improves the adhesion between a 1st IMD layer oxide (oxide, SiN or SiON) and a low k layer. Subsequent photoresist strip steps do not cause the 1st IMI layer 14 and the 2nd IMD layer 20 (low-K dielectric) to peel.

Abstract: A manufacture method for a semiconductor device includes the steps of: (a) transporting a silicon wafer into a reaction chamber having first and second gas introducing inlet ports; (b) introducing an oxidizing atmosphere via the first gas introducing inlet port and raising the temperature of the silicon wafer to an oxidation temperature; (c) introducing a wet oxidizing atmosphere to form a thermal oxide film on the surface of the silicon wafer; (d) purging gas in the reaction chamber by using inert gas to lower a residual water concentration to about 1000 ppm or lower; and (e) introducing an NO or N2O containing atmosphere into the reaction chamber via the second gas introducing inlet port while the silicon wafer is maintained above 700° C. and above the oxidation temperature, to introduce nitrogen into the thermal oxide film and form an oxynitride film. A thin oxynitride film can be manufactured with good mass productivity.

Abstract: A method of manufacturing a semiconductor device includes: providing a semiconductor with a dielectric layer formed thereon; forming an opening in said dielectric layer, said opening defined by walls of said dielectric layer and exposes a portion of said semiconductor, forming a conductive layer in said opening; removing said conductive layer to said dielectric layer; and forming a barrier layer over said conductive layer and said dielectric layer, said barrier layer made of a compound of silicon nitride with a third material compounded therein wherein said third material is modulated in amount through said layer of silicon nitride.

Abstract: An ultra high-speed semiconductor device has a high-K dielectric gate insulator layer, wherein spread of impurities to a Si substrate from a gate electrode through the high-K dielectric gate insulator layer, and spread of oxygen and metallic elements from the high-K dielectric gate insulator layer to the Si substrate or the gate electrode are suppressed by arranging the high-K dielectric film sandwiched by nitrogen atomic layers on the Si substrate that is covered by an oxygen atomic layer.

Abstract: A N2O in-situ steam generation (N2O-ISSG) process for forming an ultra-thin nitrided oxide layer is provided. The N2O-ISSG process includes placing a silicon substrate in a process chamber, and then introducing a gas mixture comprising N2O and H2 into the process chamber at a pressure lower than 10 torr. Thereafter, heating the surface of the silicon substrate to a predetermined temperature about 800˜1100° C. to cause growth of a nitrided silicon dioxide layer on the heated surface of the silicon substrate. The nitrided silicon dioxide layer has nitrogen with a content about 1˜5 atomic %.

Abstract: A method for depositing a high-k dielectric coating onto a substrate, such as a semiconductor wafer, is provided. In one embodiment, the process is directed to forming a nitride layer on a substrate. In an alternative embodiment, the present invention is directed to forming a metal oxide or silicate on a semiconductor wafer. When forming a metal oxide or silicate, a passivation layer is first deposited onto the substrate.

Abstract: A method for forming an interlayer dielectric film includes the step of forming the interlayer dielectric film out of an organic/inorganic hybrid film by plasma-polymerizing a source material, including an organosilicon compound, at a relatively high pressure within an environment containing nitrogen gas as a dilute gas.

Abstract: A phase shifting mask (PSM) for manufacturing a semiconductor device and a method of fabricating the same includes a transparent substrate, a main pattern formed on the transparent substrate and comprising a first phase shifting layer having a first optical transmittance greater than 0, and at least one assistant pattern formed on the transparent substrate proximal to the main pattern for phase-shifting by the same degree as the main pattern and having a second optical transmittance, which is less than the first optical transmittance.

Abstract: The oxynitride or oxide layer formed on a semiconductor substrate is pre-treated with UV-excited gas (such as chlorine or nitrogen) to improve the layer surface condition and increase the density of nucleation sites for subsequent silicon nitride deposition. The pre-treatment is shown to reduce the root mean square surface roughness of thinner silicon nitride films (with physical thicknesses below 36 Å, or even below 20 Å that are deposited on the oxynitride layer by chemical vapor deposition (CVD).

Abstract: There is provided an array of fluoro-substituted silsesquioxane thin film precursors having a structure wherein fluoro groups are bonded to the silicon atoms of a silsesquioxane cage. In a first aspect, the present invention provides a composition comprising a vaporized material having the formula [F—SiO1.5]x[H—SiO1.5]y, wherein x+y=n, n is an integer between 2 and 30, x is an integer between 1 and n and y is a whole number between 0 and n. Also provided are films made from these precursors and objects comprising these films.

Abstract: A method for fabricating a non-FLASH integrated circuit that minimizes Vmin shift. A protective overcoat (134) is deposited to protect and encapsulate the top metal interconnect layer (118). The protective overcoat (134) is patterned and etched to form bondpad windows either before or after depositing the final metal interconnect layer (136). A sinter that is normally performed after forming the bondpad windows is either omitted or the temperature of the sinter is kept at or below 350° C.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Oxide base film on a substrate, and then annealing the substrate in ammonia. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

Abstract: A method of fabricating a semiconductor device having a low dielectric constant is disclosed. According to the method, a silicon oxycarbide layer is formed, treated with plasma, and patterned. The silicon oxycarbide layer is formed by a coating method or a CVD method such as a PECVD method. Treating the silicon oxycarbide layer with plasma is performed by supplying at least one gas selected from a group of He, H2, N2O, NH3, N2, O2 and Ar. It is desirable that plasma be applied at the silicon oxycarbide layer in a PECVD device by an in situ method after forming the silicon oxycarbide layer. In a case in which a capping layer is further stacked and patterned, it is desirable to treat with H2-plasma. Even in a case in which an interlayer insulation is formed of the silicon oxycarbide layer and a coating layer of an organic polymer group for a dual damascene process, it is desirable to perform the plasma treatment before forming the coating layer.

Abstract: A method and system for providing a semiconductor device is disclosed. The method and system include depositing an antireflective coating (ARC) layer having antireflective properties. The method and system also include depositing a capping layer on the ARC layer. The capping layer reduces a susceptibility of the ARC layer to removal while allowing the ARC layer to substantially retain the antireflective properties.

Abstract: A method for fabricating and patterning semiconductor devices with a resolution down to 0.12 &mgr;m on a substrate structure. The method begins by providing a substrate structure comprising various layers of oxide and/or nitride formed over either monocrystalline silicon or polycrystalline silicon. A silicon oxynitride layer is formed on the substrate structure. Key characteristics of the oxynitride layer include: a refractive index of between about 1.85 and 2.35 at a wavelength of 248 nm, an extinction coefficient of between 0.45 and 0.75 at a wavelength of 248 nm, and a thickness of between about 130 Angstroms and 850 Angstroms. A photoresist layer is formed over the silicon oxynitride layer and exposed at a wavelength of between about 245 nm and 250 nm; whereby during exposure at a wavelength of between 245 nm 250 nm, the silicon oxynitride layer provides a phase-cancel effect.

Abstract: A semiconductor device is disclosed including a transistor that may have desired characteristics due to a silicon nitride film that may prevent carbon from diffusing to a silicon substrate. The semiconductor device (60) may include a device structure having an insulating film formed from gas containing carbon. A silicon nitride film may be formed between the insulating film and a transistor formation region in the silicon substrate for preventing carbon from diffusing to the silicon substrate.

Abstract: Silicon oxynitride layers are deposited by plasma enhanced chemical vapor deposition with significantly reduced defects, such as nodules, employing a ramp down step at the end of the deposition cycle. Embodiments include depositing a SION ARC at a first power, discontinuing the flow of SiH4 and ramping down to a second power while continuing the flow of N2O and N2, and ramping down to a third power while continuing the flow of N20 and N2 before pumping down. The resulting relatively defect free silicon oxynitride layers can be advantageously employed as an ARC, particularly when patterning contact holes in manufacturing flash memory devices.

Abstract: A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH4), silicon tetrafluoride (SiF4), oxygen (O2) and argon (Ar) are used as the reactant gases. SiH4, SiF4, and O2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH4 with the SiF4 tends to mitigate the destructive effects of SiF4 throughout most of the deposition. By removing the SiH4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.

Abstract: A stacked insulating film having an organic insulating film, and a carbon-containing silicon oxide film formed on the organic insulating film is disclosed. The carbon-containing silicon oxide film has a carbon content of 8 atom % to 25 atom %.

Abstract: A method is used by a semiconductor processing tool. The method comprises forming a first layer above a substrate layer, and forming an inorganic bottom antireflective coating layer above the first layer by introducing at least two gases at a preselected ratio into the semiconductor processing tools. A signal indicating that the semiconductor processing tool has been serviced is received, and the ratio of the gases is varied in response to receiving the signal to control optical parameters of the bottom antireflective coating layer to enhance subsequent photolithographic processes.

Abstract: A method of fabricating a PE-SiON film includes forming a PE-SiON film by turning on a high frequency radio frequency (HF RF) power in the chamber after a plurality of reaction gases SiH4, N2, NH3, N2O have simultaneously flown into a chamber without proceeding a bypass process of SiH4.

Abstract: Implemented is a method of manufacturing a contact structure having a combination of formation of a buried wiring and that of a low dielectric constant interlayer insulating film in which a connecting hole to be formed in a low dielectric constant interlayer insulating film does not turn into an abnormal shape. A fourth interlayer insulating film 11 is formed on an upper surface of a third interlayer insulating film 10. Next, patterning for a wiring trench and a connecting hole is carried out into the fourth interlayer insulating film 11 and the third interlayer insulating film 10, respectively. Then, a pattern of the connecting hole is first formed in a third low dielectric constant interlayer insulating film 9. Thereafter, a second interlayer insulating film 8 exposed in the pattern is removed and a pattern of the wiring trench is formed in the third interlayer insulating film 10.

Abstract: A method for fabricating a semiconductor device including a silicon substrate includes forming a thin Nitrogen Oxide base film on a substrate, and then annealing the substrate in ammonia. An ultra-thin nitride film is deposited on the base film. The semiconductor device is then oxidized in Nitrogen Oxide. FET gates are then conventionally formed over the gate insulator. The resultant gate insulator is electrically insulative without degrading performance with respect to a conventional gate oxide insulator.

Abstract: The present invention provides a method of forming a semiconductor structure (10) comprising a substrate (12) having a patterned Oxide-Nitride-Oxide (ONO) insulating layer (22) provided over a portion of the substrate (12). The invention employs an Oxide-Nitride-Silicon structure (38, 40, 42) as the basis for the ONO layer, which has the advantage that the upper silicon sub-layer (42) of the structure is resistant to damage during the photoresist stripping step of a patterning process and is then available for re-oxidizing into an oxide layer forming the upper sub-layer of the required ONO structure.

Abstract: A semiconductor package and a manufacturing method prevent electrical shorts that otherwise result from bonding wires contacting the edge of a semiconductor chip. An insulating region at the edge of a semiconductor chip prevents the shorts. One method for forming the insulating region leaves a polyimide layer on the scribe area of a wafer and cuts through the polyimide layer. To avoid chipping, the cutting uses a fine grit blade and a slow cutting rate. An alternative process removes the polyimide from the scribe area and forms the insulating region on the edge of the semiconductor chip. A potting method can deposit the insulating region on a semiconductor chip after cutting a wafer and after attaching a separated chip to a substrate. Alternatively, plotting or printing can apply insulating material on the wafer. A cutting process then cuts through the insulating material and the wafer and leaves insulating regions on each separated chip.

Abstract: A method is provided for forming a material with a low dielectric constant, suitable for electrical isolation in integrated circuits. The material and method of manufacture has particular use as an interlevel dielectric between metal lines in integrated circuits. In a disclosed embodiment, methylsilane is reacted with hydrogen peroxide to deposit a silicon hydroxide layer incorporating carbon. The layer is then treated by exposure to a plasma containing oxygen, and annealing the layer at a temperature of higher than about 450° C. or higher.

Abstract: An anti-reflection layer and method of manufacture. A silicon substrate has a conductive layer formed thereon. Plasma-enhanced chemical vapor deposition is performed to form a graded silicon oxynitride layer over the conductive layer. During silicon oxynitride deposition, concentration of one of the reactive gases nitrous oxide is gradually reduced so that the graded silicon oxynitride layer is oxygen-rich near bottom but nitrogen-rich near the top.

Abstract: A semiconductor device includes a substrate, a gate oxide film formed on the substrate, a gate electrode provided on the gate oxide film, first and second diffusion regions formed in the substrate at both lateral sides of the gate electrode. The gate electrode includes a first region located immediately underneath the gate electrode and a second region adjacent to the first region, wherein the first and second regions contain N atoms with respective concentrations such that the second region contains N with a higher concentration as compared with the first region.

Abstract: A method for forming a dielectric layer upon a silicon layer. There is first provided a substrate employed within a microelectronics fabrication. There is then formed over the substrate a silicon layer. There is then formed through use of a first thermal annealing method employing a nitrogen containing annealing atmosphere in absence of an oxidizing material or a reducing material silicon nitride containing layer upon a partially consumed silicon layer derived from the silicon layer. There is then oxidized through use of a second thermal annealing method employing an oxidizing material containing atmosphere the silicon nitride containing layer to form an oxidized silicon nitride containing layer upon a further consumed silicon layer derived from the partially consumed silicon layer. The method is particularly useful in forming a gate dielectric layer with enhanced hot carrier resistance properties and enhanced dopant diffusion barrier properties within a field effect transistor (FET).

Abstract: A deposition process for silicon oxycarbide films suitable for use as anti-reflection coatings is described. The, process is based on plasma enhanced CVD of silane mixed with methyl-silane, trimethyl-silane, or tetramethyl-silane (together with a carrier gas). Provided the relative gas flow rates are maintained within the ranges specified, films having excellent ARL properties are obtained, with photoresist patterns formed on said films being free of overhangs and footings.

Abstract: This semiconductor device manufacturing method comprises the steps of: forming a thick gate oxide film (thick oxide film) in a first region of a substrate, forming a thin gate oxide film (thin oxide layer) in a second region, and then, applying oxynitridation to these gate oxide films; forming gate electrodes to 1d on these gate oxide films; and implanting an ion that contains nitrogen or nitrogen atoms into at least one part of an interface between the hick gate oxide film (thick oxide film) and the substrate before or after the step of forming the gate electrodes, thereby forming a highly oxy-nitrided region. In this manner, in a semiconductor device in which there coexist a MISFET having a thin gate insulation film and a MISFET having a thick gate insulation film, hot carrier reliability of the MISFET having the thick gate insulation film is improved.

Abstract: A method of manufacturing a capacitor for semiconductor memory devices is disclosed. According to the present invention, a lower electrode is formed on the semiconductor substrate. A Ta2O5 layer with a tantalum-based carbon-free precursor is formed on the lower electrode. And, an upper electrode is formed on the Ta2O5 layer.

Abstract: A method of nitriding the gate oxide layer of a semiconductor device includes the chemical growth on a silicon substrate of a native silicon oxide layer ≦1 nm thick; treating said substrate coated with the native silicon oxide layer with gas NO at a temperature ≦700° C. and a pressure level ≦104 Pa to obtain a nitrided native silicon oxide layer; and the growth of the gate oxide layer. The method is applicable to PMOS devices. Further modifications and alternative embodiments of various aspects of the invention will be apparent to those skilled in the art in view of this description. Accordingly, this description is to be construed as illustrative only and is for the purpose of teaching those skilled in the art the general manner of carrying out the invention. It is to be understood that the forms of the invention shown and described herein are to be taken as the presently preferred embodiments.