Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
  • Publication number: 20030092284
    Abstract: A method and apparatus for preventing plasma induced damage resulting from high density plasma deposition processes. In the present embodiment, Un-doped Silica Glass(USG) is deposited so as to form a USG liner. In the present embodiment, the USG liner directly overlies a conductive interconnect structure that couples to semiconductor devices that are susceptible to plasma-induced damage during high density plasma deposition processes. A silicon-rich oxide is deposited in-situ immediately following the deposition of the USG liner so as to form a silicon-rich oxide liner that directly overlies the USG liner. The silicon-rich oxide liner protects the interconnect structure during the subsequent high density plasma deposition process, preventing damage resulting from plasma charge to the interconnect structure.
    Type: Application
    Filed: November 13, 2001
    Publication date: May 15, 2003
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURED LIMITED
    Inventors: Liu Huang, John Suodijono
  • Publication number: 20030089681
    Abstract: A method for controlling the voltage distribution of the standing wave impressed upon the coil of an inductively coupled plasma generator includes the steps of impressing a radio frequency voltage across the coil to establish a standing wave thereacross. A voltage profile is selected for the standing wave so as to control the location and amount of capacitive coupling. A circuit parameter is controlled to achieve the selected voltage profile. Proper selection of the voltage profile enhances process capabilities, decreases the time between cleans, minimizes component wear, and minimizes cleaning time. An apparatus for carrying out the disclosed method is also disclosed.
    Type: Application
    Filed: December 20, 2002
    Publication date: May 15, 2003
    Inventors: Guy Blalock, Kevin G. Donohoe
  • Patent number: 6562731
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Grant
    Filed: January 2, 2001
    Date of Patent: May 13, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur
  • Patent number: 6562734
    Abstract: A method of filling gaps on a semiconductor wafer with a dielectric material employs a plasma enhanced chemical vapor deposition (PECVD) process with a temperature in the range of 500 to 700° C. As a result of the deposition process, gaps resulting from e.g. shallow trench isolation or premetal dielectric techniques are filled homogeneously without any voids. The deposition may be improved by applying two radio frequency signals with different frequencies.
    Type: Grant
    Filed: September 17, 2001
    Date of Patent: May 13, 2003
    Assignee: Semiconductor 300 GmbH & Co. KG
    Inventor: Markus Kirchhoff
  • Patent number: 6559026
    Abstract: A trench-fill material is deposited to fill a trench in a substrate disposed in a process chamber. An inert gas is introduced into the process chamber and a plasma is formed to heat the substrate to a preset temperature, which is typically the temperature at which deposition of the trench-fill material is to take place. The plasma is terminated upon reaching the preset temperature for the substrate. A process gas is then flowed into the process chamber without plasma excitation until the process gas flow and distribution achieve a generally steady state in the process chamber. A plasma is then formed to deposit the trench-fill material on the surface of the substrate and fill the trench. By establishing generally steady state conditions in the chamber prior to deposition, transient effects are reduced and more uniform deposition of the trench-fill material is obtained.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: May 6, 2003
    Assignee: Applied Materials, Inc
    Inventors: Kent Rossman, Zhuang Li, Young Lee
  • Publication number: 20030082923
    Abstract: An apparatus for radical oxidation of a silicon wafer contained therein includes a vacuum chamber having a heated chuck therein for holding the silicon wafer, and for maintaining the temperature of the silicon wafer at a temperature of between about 400° C. to 500° C.; an oxidation gas source for providing an oxygen-containing gas to oxidize the silicon wafer in the vacuum chamber; an oxygen dissociation mechanism for dissociating the oxygen-containing gas into a dissociation product containing oxygen in a O(1D) state; and a mechanism for moving the dissociation product through the vacuum chamber. A method of radical oxidation of silicon wherein the silicon is in the form of a wafer of semiconductor-pure silicon includes placing a silicon wafer in a heated chuck, wherein the heated chuck maintains the silicon wafer therein at a temperature of between about 400° C. and 500° C.
    Type: Application
    Filed: October 30, 2001
    Publication date: May 1, 2003
    Inventor: Yoshi Ono
  • Publication number: 20030082924
    Abstract: A method of converting a hydrophobic surface of a dielectric layer to a hydrophilic surface is described. That method comprises forming a dielectric layer on a substrate, then operating a PECVD reactor to generate a plasma that converts the surface of that layer from a hydrophobic surface to a hydrophilic surface. Also described is a method for making a semiconductor device that employs this technique.
    Type: Application
    Filed: October 25, 2001
    Publication date: May 1, 2003
    Inventors: Ebrahim Andideh, Kevin L. Peterson
  • Publication number: 20030077917
    Abstract: A method of fabricating a void-free barrier layer located on a semiconductor substrate. First, conductive structures are defined on the semiconductor substrate. Second, a barrier layer is deposited over the conductive structures, wherein the barrier layer has a void between the conductive structures. Third, argon gas is introduced into a HDPCVD chamber to sputter the barrier layer so that the void is eliminated.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventors: Ping-Wei Lin, Ming-Kuan Kao, Cheng Chung Hsieh
  • Publication number: 20030077920
    Abstract: A semiconductor device fabricating method for forming a boron doped silicon film includes the step of forming the boron doped silicon film on a substrate at an inner temperature of the reaction furnace ranging from about 460 to 600° C. or at an average velocity of reaction gases in the reaction furnace being not great than about 2200 cm/min. Further, a substrate processing apparatus for forming a boron doped silicon film on a substrate includes a gas supply line for supplying BCl3 to the reaction furnace. The gas supply line is installed in a portion of the reaction furnace opposite to a heater, and has an outlet for discharging BCl3. The outlet of the gas supply line is provided at an upstream side of gas flow in the reaction furnace.
    Type: Application
    Filed: September 27, 2002
    Publication date: April 24, 2003
    Applicant: Hitachi Kokusai Electric Inc.
    Inventors: Takaaki Noda, Akira Morohashi, Junji Asahi
  • Publication number: 20030077888
    Abstract: A high density plasma chemical vapor deposition (HDP-CVD) process is used to deposit silicon dioxide in trenches of various widths. The thickness of the silicon dioxide filling both narrow and wide trenches is made more uniform by reducing an HDP-CVD etch to deposition ratio. The lowered etch to deposition ratio is achieved by lowering a ratio of oxygen to silane gas, by lowering the power of a high frequency bias signal, and by lowering the total gas flow rate.
    Type: Application
    Filed: October 22, 2001
    Publication date: April 24, 2003
    Inventors: Tai-Peng Lee, Chuck Jang
  • Publication number: 20030070761
    Abstract: A plasma reactor has a reactor vessel and a pair of electrodes in the form of spaced apart and oppositely disposed metallic surfaces defining therebetween a plasma discharge space. At least one of the metallic surfaces is the surface of a metallic plate having a plurality of gas feed openings extending through the metallic surface towards said discharge space and from a distribution chamber extending along the plate opposite the discharge space. The distribution chamber has a wall opposite and distant from the plate and includes a gas inlet arrangement with a plurality of gas inlet openings distributed along the wall and connected to one or more gas feed lines to the reactor. A gas flow resistant coefficient between the one or more gas feed lines and at least a predominant portion of the connected inlet openings are at least substantially equal.
    Type: Application
    Filed: November 21, 2002
    Publication date: April 17, 2003
    Applicant: Unaxis Balzers Aktiengesellschaft
    Inventors: Emmanuel Turlot, Jean-Baptiste Chevrier, Jacques Schmitt, Jean Barreiro
  • Patent number: 6548342
    Abstract: The temperature at which an oxide dielectric thin film is formed can be made lower than conventional by reducing the concentration of oxygen in an atmosphere for forming the thin film. As a result, there can be formed an oxide dielectric thin film which has a crystal structure preferentially oriented at a crystal plane allowing a polarization axis to be directed in the vertical direction, which eliminates any reaction with an electrode material, and controls the growth of crystal grains. The use of such an oxide dielectric thin film can provide an oxide dielectric element having a high spontaneous polarization and a small coercive field. Consequently, it is possible to achieve a dielectric element having a high density of integration for detecting reading and writing operations, and a semiconductor device using the same.
    Type: Grant
    Filed: February 12, 1999
    Date of Patent: April 15, 2003
    Assignee: Hitachi, Ltd.
    Inventors: Takaaki Suzuki, Toshihide Nabatame, Kazutoshi Higashiyama
  • Publication number: 20030068902
    Abstract: A method for depositing an inter-metal-dielectric layer on a semiconductor substrate by plasma chemical vapor deposition without the layer cracking defect is disclosed. The semiconductor substrate is first heat-treated in the same plasma process chamber to a temperature of at least 300° C. for a length of time sufficient to outgas a surface of the semiconductor substrate. The impurity gases absorbed on the surface of the semiconductor substrate can be effectively outgassed during the heat treatment process such that they are not trapped under an IMD layer deposited in a subsequent plasma deposition process. The method effectively minimizes or eliminates completely the IMD layer cracking defect of the dielectric layer.
    Type: Application
    Filed: October 9, 2001
    Publication date: April 10, 2003
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shih-Ming Wang, Long-Shang Chuang, Jui-Ping Chuang, Chin-Hsiung Ho, Mei-Yen Li, Chien-Kang Chou
  • Publication number: 20030066487
    Abstract: To provide a plasma processing system capable of introducing a uniform microwave into a plasma processing chamber irrespective of conditions, and a surface processing method using the same. A plasma processing system in which air in a plasma processing chamber is exhausted by an exhaust unit, a microwave is supplied to the plasma processing chamber through an annular waveguide which is bored to be provided at predetermined intervals in a circumferential direction on the same plane facing a surface to be processed of an object to be processed on the plasma processing chamber side to generate plasma within the plasma processing chamber, wherein the annular waveguide is separated into two layers of an input side waveguide and an output side waveguide, and the slots are bored to be provided between these waveguides at predetermined intervals in a circumferential direction.
    Type: Application
    Filed: September 30, 2002
    Publication date: April 10, 2003
    Inventor: Nobumasa Suzuki
  • Patent number: 6544902
    Abstract: A method of creating a resist or other protective material pattern on a substrate using traversal of a focused energy beam such as a laser beam in a selected pattern over the substrate to cure a resin polymer, other resist material or other protective layer disposed over the substrate. The substrate may comprise a semiconductor wafer or other large-scale substrate comprising a large plurality of semiconductor die locations, may comprise a partial wafer or substrate, or a singulated semiconductor die.
    Type: Grant
    Filed: August 31, 2000
    Date of Patent: April 8, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Warren M. Farnworth
  • Patent number: 6541400
    Abstract: An improved process for depositing a robust fluorosilicate glass film on a substrate in a chamber includes maintaining a total pressure in the chamber of less than about 1.7 torr, introducing vapor phase chemicals such as N2, SiF4, SiH4, and N2O into the chamber, and reacting the vapor-phase chemicals with sufficiently supplied energy to deposit a thin film layer of the fluorosilicate glass on the substrate. Advantageously, the deposited fluorosilicate glass films are chemically, mechanically, and thermally stable without additional processing. Also advantageously, the films are deposited uniformly at rates greater than about 5000 Angstroms per minute with dielectric constants of about 3.4 to about 3.9.
    Type: Grant
    Filed: February 9, 2000
    Date of Patent: April 1, 2003
    Assignee: Novellus Systems, Inc.
    Inventors: Jason L. Tian, Harald Te Nijenhuis
  • Patent number: 6537929
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organosilane or organosiloxane compound and an oxidizing gas at a low RF power level from 10-250 W. The oxidized organosilane or organosiloxane film has good barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organosilane or organosiloxane film may also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organosilane or organosiloxane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organosilane film is produced by reaction of methylsilane, CH3SiH3, or dimethylsilane, (CH3)2SiH2, and nitrous oxide, N2O, at an RF power level from about 10 to 200 W or a pulsed RF power level from about 20 to 250 W during 10-30% of the duty cycle.
    Type: Grant
    Filed: May 25, 2000
    Date of Patent: March 25, 2003
    Assignee: Applied Materials, Inc.
    Inventors: David Cheung, Wai-Fan Yau, Robert R. Mandal
  • Patent number: 6537928
    Abstract: A CVD apparatus includes (i) a reaction chamber; (ii) a reaction gas inlet; (iii) a lower stage on which a semiconductor substrate is placed; (iv) an upper electrode for plasma excitation; (v) an intermediate electrode with plural pores through which the reaction gas passes, wherein a reaction space is formed between the upper electrode and the intermediate electrode; and (vi) a cooling plate disposed between the intermediate electrode and the lower stage, wherein a transition space is formed between the intermediate electrode and the cooling plate, and a plasma-free space is formed between the cooling plate and the lower stage.
    Type: Grant
    Filed: February 19, 2002
    Date of Patent: March 25, 2003
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Seijiro Umemoto, Yasuyoshi Hyodo
  • Patent number: 6534409
    Abstract: Methods of providing silicon oxide on a substrate in a single process step by simultaneously introducing both a silicon source gas and an etch gas into a CVD chamber. As a result, the method will typically involve simultaneous deposition and etching of the silicon oxide. The method is particularly useful for providing silicon oxide spacers with faceted surfaces.
    Type: Grant
    Filed: August 24, 1998
    Date of Patent: March 18, 2003
    Assignee: Micron Technology, Inc.
    Inventor: Anand Srinivasan
  • Patent number: 6534423
    Abstract: An inductively-coupled hydrogen plasma (ICP) is used to passivate a plasma-enhanced chemical vapor deposition reactor following an in situ cleaning step. The hydrogen ICP effectively removes the fluorine and hydrogen that typically become impregnated in the walls of the reaction chamber during the in situ clean and thereby reduces the amount of “outgassing” that occurs during subsequent deposition cycles. This outgassing may cause the film of deposition material that normally forms on the walls to flake, significantly reducing the yield of usable devices. The hydrogen ICP passivation process has been found particularly effective in conjunction with the deposition of heavily-doped silicon oxide layers.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: March 18, 2003
    Assignee: Novellus Systems, Inc.
    Inventor: Michael Turner
  • Patent number: 6528434
    Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.
    Type: Grant
    Filed: October 22, 2001
    Date of Patent: March 4, 2003
    Assignee: Macronix International Co. Ltd.
    Inventor: Wei-Wen Chen
  • Patent number: 6528435
    Abstract: An apparatus and method for depositing a thin film on a semiconductor substrate. The apparatus includes a chamber or housing suited for holding a plurality of wafer platforms. The wafer platforms are arranged stacked in the chamber equidistant and electrically isolated from each other wafer platform. At least two of the plurality of wafer platforms are electrically coupled to a power source to form a first electrode and a second electrode. The remainder of the plurality of wafer platforms are disposed therebetween. In this manner, the first electrode and the second electrode form a single series capacitor. At least one reactant gas is provided in the chamber and reacted with sufficiently supplied energy to form a plasma. Radicals or ions from the plasma react on the surface of the wafers to cause a thin film layer to be distributed on the equally dispersed wafers positioned on a surface of the wafer platforms.
    Type: Grant
    Filed: August 25, 2000
    Date of Patent: March 4, 2003
    Assignee: WaferMasters, Inc.
    Inventor: Woo Sik Yoo
  • Publication number: 20030038109
    Abstract: Disclosed is a method of protecting semiconductor areas while exposing a structures for processing on a semiconductor surface, the method comprising depositing a planarizing high density plasma film of a silicon compound, selected from the group silicon oxide and silicon nitride, depositing a planarized polymer film to a thickness effective in protecting said high density plasma film while leaving high density plasma excess exposed, and etching away said high density plasma excess.
    Type: Application
    Filed: August 23, 2001
    Publication date: February 27, 2003
    Applicant: International Business Machines Corporation, Armonk, New York,
    Inventors: Omer H. Dokumaci, Bruce B. Doris, Michael P. Belyansky
  • Patent number: 6521545
    Abstract: The invention shows a method of a surface treatment on a fluorine silicate glass film. At first a fluorine silicate glass layer is deposited on a semiconductor wafer. Partial fluorine ions in the fluorine silicate glass layer are in-situ removed to form a silicon oxide layer of a pre-determined thickness. Then, a photoresist layer is coated on the silicon oxide layer. After an exposing process, a pre-determined latent pattern is formed in the photoresist layer. Finally, after a developing process, the pre-determined latent pattern of the photoresist is removed so as to expose corresponding portions of the silicon oxide layer underneath the latent pattern of the photoresist layer. As a result, the present invention solves a problem that fluorine ions in the fluorine silicate glass layer 24 diffuse to a surface of the fluorine silicate glass layer 24 to combine with water to form hydrofluoric acid, that contaminates the photoresist and leads to reliability issues.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 18, 2003
    Assignee: United Microelectronics Corp.
    Inventors: Neng-Hui Yang, Chinh-Fu Lin, Yi-Fang Cheng, Cheng-Yuan Tsai
  • Patent number: 6521548
    Abstract: At least two neighboring metal lines are formed on a semiconductor substrate first, followed by the formation of a PE oxide layer on the semiconductor substrate, that uniformly covers the surface of the two neighboring metal lines and the gap between the two neighboring metal lines. A SOD layer on the PE oxide layer is created to fill the gap. Then the semiconductor substrate is directly heated by utilizing at least one hot plate fixed at a first predetermined temperature so as to expel the solvent out of the SOD layer. Finally, the semiconductor wafer is directly heated by utilizing a second hot plate fixed at a second predetermined temperature so as to cure the SOD layer for a predetermined time.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: February 18, 2003
    Assignee: Macronix International Co. Ltd.
    Inventor: Pei-Ren Jeng
  • Patent number: 6521546
    Abstract: A method of forming an integrated circuit using a fluoro-organosilicate layer is disclosed. The fluoro-organosilicate layer is formed by applying an electric field to a gas mixture comprising a fluoro-organosilane compound and an oxidizing gas. The fluoro-organosilicate layer is compatible with integrated circuit fabrication processes. In one integrated circuit fabrication process, the fluoro-organosilicate layer is used as a hardmask. In another integrated circuit fabrication process, the fluoro-organosilicate layer is incorporated into a damascene structure.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: February 18, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Michael Barnes, Hichem M'Saad, Huong Thanh Nguyen, Farhad Moghadam
  • Publication number: 20030022519
    Abstract: The invention provides a process for producing a semiconductor layer by introducing a raw gas into a discharge chamber and supplying high-frequency power to the chamber to decompose the raw gas by discharge, thereby forming a semiconductor layer on a substrate within the discharge chamber, the process comprising the steps of supplying high-frequency power of at least very high frequency (VHF) as the high-frequency power; supplying bias power of direct current power and/or high-frequency power of radio-frequency (RF) together with the high-frequency power of VHF to the discharge chamber; and controlling a direct current component of an electric current flowing into an electrode, to which the bias power is supplied, so as to fall within a range of from 0.1 A/m2 to 10 A/m2 in terms of a current density based on the area of an inner wall of the discharge chamber. A good-quality semiconductor layer can be deposited over a large area at a high speed.
    Type: Application
    Filed: September 11, 2002
    Publication date: January 30, 2003
    Inventors: Yasushi Fujioka, Shotaro Okabe, Masahiro Kanai, Akira Sakai, Tadashi Sawayama, Yuzo Yoda, Takahiro Yajima
  • Publication number: 20030022526
    Abstract: A high density plasma oxidation process is provided in which a dielectric film is formed having a predetermined thickness. Plasma oxidation conditions are provided such that the growth rate of the dielectric film is limited in order to produce dielectric layer having a precise thickness and uniformity. The high density plasma oxidation process can be used to fabricate gate oxide layers, passivation layers and antifuse layers in semiconductor devices such as semiconductor memory devices and multi-level memory arrays.
    Type: Application
    Filed: July 30, 2001
    Publication date: January 30, 2003
    Inventors: Michael A. Vyvoda, N. Johan Knall, James M Cleeves
  • Patent number: 6511921
    Abstract: A process for effectively reducing reactivity of a surface of a semiconductor substrate is described. The process includes: (1) oxidizing in an oxidizing environment the semiconductor substrate surface, the semiconductor substrate having a dopant concentration profile that extends across a depth of the semiconductor substrate; and (2) annealing the semiconductor substrate surface in an inert gas environment, wherein the oxidizing and the annealing of the semiconductor substrate surface are performed at a temperature that is sufficiently low to substantially preserve the dopant concentration profile in the semiconductor substrate. A surface passivation apparatus is also described. The apparatus includes: a heating source for heating a substrate surface; an ozone generator; and a chamber for exposing a substrate surface to an oxidizing environment that includes a gas composition, wherein the ozone generator is configured to produce ozone within the chamber using the gas composition.
    Type: Grant
    Filed: January 12, 1999
    Date of Patent: January 28, 2003
    Assignee: Sumco Phoenix Corporation
    Inventors: Christopher A. Panczyk, Jonathan M. Madsen, Walter Huber
  • Patent number: 6511924
    Abstract: A method for forming a silicon oxide layer for use in integrated circuit fabrication is provided. The silicon oxide layer is formed by reacting a first gas mixture and a second gas mixture. The first gas mixture comprises tetra-ethyl-ortho-silicate (TEOS), helium (He) and nitrogen (N2). The second gas mixture comprises ozone (O3) and optionally, oxygen (O2).
    Type: Grant
    Filed: April 20, 2001
    Date of Patent: January 28, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Kevin Mukai, Srinivas Nemani
  • Patent number: 6511903
    Abstract: A method and apparatus for depositing a low dielectric constant film by reaction of an organo silane compound and an oxidizing gas. The oxidized organo silane film has excellent barrier properties for use as a liner or cap layer adjacent other dielectric layers. The oxidized organo silane film can also be used as an etch stop or an intermetal dielectric layer for fabricating dual damascene structures. The oxidized organo silane films also provide excellent adhesion between different dielectric layers. A preferred oxidized organo silane film is produced by reaction of methyl silane, CH3SiH3, and N2O.
    Type: Grant
    Filed: December 16, 1999
    Date of Patent: January 28, 2003
    Assignee: Applied Materials, Inc.
    Inventors: Wai-Fan Yau, David Cheung, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Yu
  • Patent number: 6511925
    Abstract: In accordance with the invention a high-k gate dielectric is formed by the steps of first forming a silicon oxide layer over a silicon substrate and then exposing the silicon oxide to a flux of low energy plasma containing metal ions which, when inserted into silicon oxide, form a high-k dielectric material suitable for use as a high-k gate dielectric. In one embodiment, the silicon oxide is exposed to a first plasma containing a first species of metal ions and then to a plasma of another species of metal ions which, when inserted into the silicon oxide with the metal ions in the first plasma, further increase the dielectric constant of the silicon oxide.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: January 28, 2003
    Assignee: LSI Logic Corporation
    Inventors: Sheldon Aronowitz, Vladimir Zubkov, Helmut Puchner
  • Publication number: 20030017718
    Abstract: A method for forming an interlayer dielectric film includes the step of forming the interlayer dielectric film out of an organic/inorganic hybrid film by plasma-polymerizing a source material, including an organosilicon compound, at a relatively high pressure within an environment containing nitrogen gas as a dilute gas.
    Type: Application
    Filed: August 21, 2002
    Publication date: January 23, 2003
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventor: Nobuo Aoi
  • Publication number: 20030017715
    Abstract: A semiconductor device having composite dielectric layer formed between a silicon substrate and a gate electrode. The composite gate dielectric layer including a layer of silicon oxide, SiOx≦2, having a dielectric constant of greater than about 3.9 and about 12 or less, and a complementary dielectric layer for inhibiting the flow of leakage current through the composite dielectric layer.
    Type: Application
    Filed: August 23, 2002
    Publication date: January 23, 2003
    Inventors: David A. Muller, Gregory L. Timp, Glen David Wilk
  • Patent number: 6509283
    Abstract: Atomic oxygen, or a mixture of atomic oxygen and atomic nitrogen, is utilized in thermally oxidizing silicon to form a layer of silicon dioxide, or nitrogen-doped silicon dioxide, on a surface of the silicon. Use of atomic oxygen (or O−+N−) provides a better stoichiometric silicon dioxide structure with fewer dangling bonds than results from standard oxidation processes. The atomic oxygen (or O−+N−) may be generated within the oxidation furnace, for example by passing the gas through a heated ceramic material (e.g., Al2O3) or by using internal UV radiation of the oxygen gas. Alternatively, the atomic oxygen (or O−+N−) may be generated at a remote source, for example in a plasma reactor, and then introduced to the oxidation furnace. Atomic chlorine can be generated and used prior to the oxidation step for pre-cleaning the silicon surface.
    Type: Grant
    Filed: May 13, 1998
    Date of Patent: January 21, 2003
    Assignee: National Semiconductor Corporation
    Inventor: Michael E. Thomas
  • Patent number: 6506678
    Abstract: An aluminum layer formed over an integrated circuit structure is patterned to form a plurality of aluminum metal lines. The patterned aluminum metal lines are then anodized in an acid anodizing bath to form anodized aluminum oxide on the exposed sidewall surfaces of the patterned aluminum. The anodization may be carried out until the anodized aluminum films on horizontally adjacent aluminum metal lines contact one another, or may be stopped prior to this point, leaving a gap between the anodized aluminum oxide films on adjacent aluminum metal lines. This gap may then be either filled with other low k dielectric material or by standard (non-low k) dielectric material. A capping layer of non-porous dielectric material is then formed over the porous anodized aluminum oxide.
    Type: Grant
    Filed: May 19, 2000
    Date of Patent: January 14, 2003
    Assignee: LSI Logic Corporation
    Inventor: Valeriy Sukharev
  • Patent number: 6503818
    Abstract: A method for forming a composite dielectric layer comprising a low dielectric constant dielectric layer upon a substrate employed within a microelectronics fabrication. There is provided a patterned microelectronics layer upon a substrate employed within a microelectronics fabrication. There is then formed upon the microelectronics substrate a low dielectric constant dielectric layer. There is then treated the low dielectric constant dielectric layer with a plasma, forming a plasma treated low dielectric constant dielectric layer. There is then formed upon the plasma treated low dielectric constant dielectric layer a silicon containing dielectric layer with enhanced adhesion thereupon.
    Type: Grant
    Filed: April 2, 1999
    Date of Patent: January 7, 2003
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventor: Syun-Ming Jang
  • Patent number: 6500752
    Abstract: The present invention relates to a semiconductor device manufacturing method of forming an inter-wiring layer insulating film having a low dielectric constant to cover a copper wiring. In construction, in a semiconductor device manufacturing method of forming an insulating film 34 having a low dielectric constant on a substrate 20, the insulating film 34 is formed by plasmanizing a film forming gas, that consists of at least any one of alkyl compound having siloxane bonds and methylsilane (SiHn(CH3)4−n: n=0, 1, 2, 3), any one oxygen-containing gas selected from a group consisting of N2O, H2O, and CO2, and ammonia (NH3) to react.
    Type: Grant
    Filed: July 16, 2001
    Date of Patent: December 31, 2002
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Taizo Oku, Junichi Aoki, Youichi Yamamoto, Takashi Koromokawa, Kazuo Maeda
  • Publication number: 20020197885
    Abstract: A method described for making a semiconductor transistor having a thin gate dielectric layer with a high k-value but without any impurities in a channel in silicon directly below the gate dielectric layer. An apparatus is used which pulses a cathode to create a plasma generating voltage potential between the cathode and an anode provided by a wall of a chamber of the apparatus. The plasma generating voltage generates an ion plasma out of a gas in the chamber. The ion plasma is maintained transient which allows for better control of its energy. A portion of a wafer stand is pulsed with a small voltage which extracts and accelerates ions out of the plasma into a silicon dioxide gate dielectric layer formed on a wafer in the chamber.
    Type: Application
    Filed: June 22, 2001
    Publication date: December 26, 2002
    Inventors: Jack Hwang, Mitchell C. Taylor
  • Publication number: 20020197889
    Abstract: While a crucible containing an Si material and a substrate to be processed are set in a chamber, Ar gas is supplied into the chamber and the Si material is evaporated by heating, thereby forming a nanoparticle thin film of Si on the substrate. This substrate is then annealed in an oxygen atmosphere to oxidize Si, forming a nanoparticle oxide thin film consisting of SiO2.
    Type: Application
    Filed: June 12, 2002
    Publication date: December 26, 2002
    Applicant: Semiconductor Technology Academic Research Center
    Inventors: Shinji Nozaki, Kazuo Uchida, Hiroshi Morisaki
  • Patent number: 6498112
    Abstract: A method is provided, the method comprising forming a first dielectric layer above a structure layer, the first dielectric layer having an upper portion. The method also comprises grading the upper portion of the first dielectric layer using at least one of monomethyl silane, dimethyl silane, trimethyl silane, and tetramethyl silane with helium (He) and at least one of nitrous oxide (N2O) and molecular nitrogen (O2).
    Type: Grant
    Filed: July 13, 2001
    Date of Patent: December 24, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Jeremy I. Martin, Ting Yiu Tsui
  • Publication number: 20020192391
    Abstract: Method and apparatus for treating a surface of a substrate plate under irradiation of ultraviolet ray emitted from a dielectric barrier discharge lamp. Upon admission into a treating chamber, oxygen is removed from a treating surface and surrounding atmosphere of a substrate plate in order to suppress energy losses of ultraviolet ray to a minimum.
    Type: Application
    Filed: November 20, 2001
    Publication date: December 19, 2002
    Applicant: Hitachi Electronics Engineering Co., Ltd.
    Inventors: Kenya Wada, Kazuto Kinoshita, Kazuhiko Gommori
  • Patent number: 6495447
    Abstract: A method of manufacturing a semiconductor device includes forming a first level, forming a first barrier layer over the first level, forming a dielectric layer over the first barrier layer; decreasing the hydrophilic properties of a first portion of the dielectric layer, forming an opening through the dielectric layer, and filling the opening with metal to form a first metal feature. The hydrophilic properties of the first portion are lesser than a second portion of the dielectric layer. The hydrophilic properties of the first portion can be decreased by doping the first portion with hydrogen using ion implantation or plasma etching. An upper surface of the dielectric layer can also be roughened during the process of hydrogen doping. A semiconductor device produced by the method of manufacturing is also disclosed.
    Type: Grant
    Filed: June 26, 2001
    Date of Patent: December 17, 2002
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Lynne A. Okada, Calvin T. Gabriel
  • Publication number: 20020187280
    Abstract: A method and system for reducing damage to substrates (e.g., wafers) during plasma processing by using a high pressure source. A thin electrostatic shield enables a large number of thin slots to be formed in an electrostatic shield while still being able to excite the plasma. The bottom of the slots and the top of the substrate are separated such that the mean free path of the plasma particles is between 0.5% and 2% of the distance between the bottom of the slots and the substrate holder.
    Type: Application
    Filed: June 21, 2002
    Publication date: December 12, 2002
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Wayne L. Johnson, Murray D. Sirkis
  • Publication number: 20020187656
    Abstract: A method of forming a silicon oxide layer over a substrate disposed in a high density plasma substrate processing chamber. The silicon oxide layer is formed by flowing a process gas including a silicon-containing source, an oxygen-containing source, an inert gas and a hydrogen-containing source into the substrate processing chamber and forming a high density plasma (i.e., a plasma having an ion density of at least 1×1011 ions/cm3) from the process gas to deposit said silicon oxide layer over said substrate. In one embodiment, the hydrogen-containing source in the process gas is selected from the group of H2, H2O, NH3, CH4 and C2H6.
    Type: Application
    Filed: May 11, 2001
    Publication date: December 12, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Zhengquan Tan, Dongqing Li, Walter Zygmunt, Tetsuya Ishikawa
  • Publication number: 20020187627
    Abstract: A conducting layer is formed on a substrate and a first passivation layer is formed on the conducting layer. Following this, a first photo-chemical low dielectric constant (low-k) layer, a second passivation layer and a second low-k photo-chemical layer are formed in order on the substrate. Then, a first photolithographic process is performed to form a trench in the second low-k photo-chemical dielectric layer. A first etching process is performed to remove portions of the second passivation layer not covered by the second low-k photo-chemical layer down to the surface of the first low-k photo-chemical layer. Subsequently, a second photolithographic process is performed to form a via hole in the first low-k photo-chemical layer. Finally, a second etching process is performed to remove portions of the first passivation layer not covered by the first low-k photo-chemical layer down to the surface of the conducting layer.
    Type: Application
    Filed: June 6, 2001
    Publication date: December 12, 2002
    Inventor: Yu-Shen Yuang
  • Publication number: 20020187655
    Abstract: A method for forming a silicon oxide layer over a substrate disposed in a high density plasma substrate processing chamber. The method includes flowing a process gas that includes a silicon-containing source, an oxygen-containing source and a fluorine-containing source into the substrate processing chamber and forming a plasma from said process gas. The substrate is heated to a temperature above 450° C. during deposition of said silicon oxide layer and the deposited layer has a fluorine content of less than 1.0 atomic percent.
    Type: Application
    Filed: May 11, 2001
    Publication date: December 12, 2002
    Applicant: Applied Materials, Inc.
    Inventors: Zhengquan Tan, Dongqing Li, Walter Zygmunt
  • Patent number: 6486081
    Abstract: The present invention provides an apparatus for depositing a film on a substrate comprising a processing chamber, a substrate support member disposed within the chamber, a first gas inlet, a second gas inlet, a plasma generator and a gas exhaust. The first gas inlet provides a first gas at a first distance from an interior surface of the chamber, and the second gas inlet provides a second gas at a second distance that is closer than the first distance from the interior surface of the chamber. Thus, the second gas creates a higher partial pressure adjacent the interior surface of the chamber to significantly reduce deposition from the first gas onto the interior surface.
    Type: Grant
    Filed: November 24, 1999
    Date of Patent: November 26, 2002
    Assignee: Applied Materials, Inc.
    Inventors: Tetsuya Ishikawa, Padmanabhan Krishnaraj, Feng Gao, Alan W. Collins, Lily Pang
  • Patent number: 6479409
    Abstract: Disclosed is a method of fabricating a semiconductor device, in which an interlayer insulating film having a low dielectric constant is formed by coating a wiring, and either a via hole or a contact hole is formed in the interlayer insulating film. The method of fabricating a semiconductor device having the interlayer insulating film 25 formed on the film-formed substrate 21 with the exposed wiring 23, comprises the step of converting a silicon compound containing only the Si, O, C and H into a plasma gas as a film-forming gas to react the plasma gas, thus forming the block insulating film 24 containing silicon (Si), oxygen (O), carbon (C) and hydrogen (H) between the wiring 23 and the interlayer insulating film 25.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: November 12, 2002
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Kouichi Ohira, Kazuo Maeda, Tomomi Suzuki, Hiroshi Ikakura, Youichi Yamamoto, Yuichiro Kotake, Shoji Ohgawara, Makoto Kurotobi
  • Patent number: 6479407
    Abstract: An interlayer insulation film containing a dielectric component represented by a chemical formula having a Si—E bond or a Si—CH3 bond is formed on a substrate. Next, a photoresist is formed on the interlayer insulation film. The photoresist is then formed into a form of a contact hole. Thereafter, dry-etching of the interlayer insulation film is conducted by use of the photoresist as a mask. Subsequently, the photoresist is removed, and the interlayer insulation film is exposed to nitrogen plasma and hydrogen plasma, for example.
    Type: Grant
    Filed: January 23, 2001
    Date of Patent: November 12, 2002
    Assignee: NEC Corporation
    Inventors: Takashi Yokoyama, Tatsuya Usami