Abstract: A wafer is mounted on a mounting stand 3 that is provided with an electrostatic chuck. Then an SiOF film is formed by creating a plasma of a processing gas and heating the wafer W to approximately 350° C. while the surface of the mounting stand 3 is heated to 200° C. After ten wafers W have been processed, cleaning is performed to remove a film S that has adhered to the interior of the film-formation chamber, and then a pre-coat is formed. A protective plate 5 made of aluminum nitride is placed on the mounting stand 3 during the cleaning and pre-coating steps. The protective plate 5 protects the surface of the electrostatic chuck during the cleaning and prevents the formation of a film on the mounting stand 3 during the pre-coating. In addition, since the protective plate 5 is electrostatically attracted to the mounting stand 3 and it is also strong with respect to thermal shocks, there is no need to lower the temperature of the mounting stand 3 during the cleaning, which improves throughput.

Abstract: A process and system for forming a low dielectric film in a semiconductor fabrication process are disclosed. Initially, a carbon-doped silicon oxide film is deposited on a semiconductor wafer. Light energy, such as ultraviolet (UV) energy, is then applied to the deposited film to cure the film. In one embodiment, at least 30% of the light energy is at a frequency greater than that of visible light. In the preferred embodiment, the application of the light energy to the wafer does not significantly heat the wafer. The invention further contemplates a cluster tool or system suitable for forming and curing the dielectric film. The cluster tool includes a first chamber coupled to an organosilane source, a second chamber configured to apply light energy to a wafer received in the second chamber, and a robotic section suitable for controlling movement of wafers between the first chamber and the second chamber.

Abstract: A method for forming a semiconductor device is disclosed in which a fluorinated silicon dioxide layer is formed over a semiconductor substrate. A first undoped silicon dioxide layer, with a thickness preferably less than approximately 50 nanometers, is then formed on the fluorinated silicon dioxide layer with a PECVD process wherein a power ratio of a high frequency power source of the PECVD reactor to a low frequency power source is preferably in a range of approximately 0.2:1 to 0.4:1. In one embodiment, a second undoped silicon dioxide layer may be formed prior to forming the fluorinated silicon layer. The second undoped silicon dioxide, the fluorinated silicon dioxide layer, and the first undoped silicon dioxide layer may be formed sequentially in the same plasma enhanced chemical vapor deposition process chamber during a single chamber evacuation cycle. The first undoped silicon dioxide layer is preferably characterized as having a refractive index greater than approximately 1.460.

Abstract: A method and apparatus for reducing particle contamination in a substrate processing chamber during deposition of a film having at least two layers. The method of the present invention includes the steps of introducing a first process gas into a chamber to deposit a first layer of the film over a wafer at a first selected pressure, introducing a second process gas into the chamber to deposit a second layer of the film over the wafer, and between deposition of said first and second layers, maintaining pressure within the chamber at a pressure that is sufficiently high that particles dislodged by introduction of the second process do not impact the wafer.

Abstract: Embodiments of the present invention include a method of depositing an improved seasoning film. In one embodiment the method includes, prior to performing a substrate processing operation, forming a layer of silicon over an interior surface of the substrate processing chamber as opposed to a layer of silicon oxide. In certain embodiments, the layer of silicon comprises at least 70% atomic silicon, is deposited from a high density silane (SinH2n+2) process gas and/or is deposited from a plasma having a density of at least 1×1011 ions/cm3.

Abstract: The present invention provides a highly reliable polycrystal silicon thin film transistor with N2O plasma oxide having an excellent leakage current characteristics comparable to the thermal oxide film formed on the crystalline silicon. Also, the present invention provides a method of fabricating EEPROM or flash memory using N2O plasma oxide as a tunnel oxide, and N2O plasma oxide film as an interpoly dielectric between the floating gate and the control gate.

Abstract: A method for varying the resistance along a conductive layer. The method including the step of removing at least a portion of a resistance-altering constituent diffused within the conductive layer.

Abstract: A method for forming an interlayer dielectric film includes the step of forming the interlayer dielectric film out of an organic/inorganic hybrid film by plasma-polymerizing a source material, including an organosilicon compound, at a relatively high pressure within an environment containing nitrogen gas as a dilute gas.

Abstract: A method and system for forming a layer on a substrate in a process chamber are provided. Deposition gases are provided to the process chamber and permitted to mix in the desired relative concentrations prior to the deposition step, resulting in improved composition uniformity of the layer. This may be accomplished by generating a heating plasma from a first gaseous mixture. The plasma is then terminated and a second gaseous mixture is provided to the process chamber such that the second gaseous mixture is substantially uniformly mixed. A second plasma is then generated from the second gaseous mixture to deposit the layer on the substrate.

Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber. A “clean” silicate glass base layer substantially free of carbon particle impurities on an upper surface is formed in one of two ways. The first employs plasma-enhanced chemical vapor deposition using TEOS and diatomic oxygen gases as precursors to first deposit a “dirty” silicate glass base layer having carbon particle impurities imbedded on an upper surface thereof being transformed to a clean base layer by subjecting it to a plasma treatment, using a mixture of a diamagnetic oxygen-containing oxidant, such as ozone or hydrogen peroxide, and diatomic oxygen gas into the chamber and striking an RF plasma.

Abstract: The reliability, electromigration resistance, adhesion, and electrical contact resistance of planarized, in-laid metallization patterns, e.g., of copper, are enhanced by a process comprising selectively depositing on the planarized, upper surfaces of the metallization features at least one thin layer comprising at least one passivant element for the metal of the features, reacting the at least one passivant element to chemically reduce any deleterious oxide layer present at the upper surfaces of the metallization features, and diffusing the at least one passivant element for a distance below the upper surface to form a passivated top interface. The passivated top interfaces advantageously exhibit reduced electromigration and improved adhesion to overlying metallization with lower ohmic contact resistance. Planarization, as by CMP, may be performed subsequent to reaction/diffusion to remove any elevated, reacted and/or unreacted portions of the at least one thin layer.

Abstract: The present invention provides a method of forming different thickness” of a gate oxide layer simultaneously, by employing a pulse Nitrogen plasma implantation. The method provides a semiconductor substrate with the surface of the silicon in the semiconductor substrate separated into a first region and a second region at least. Then a thin surface on the surface of the silicon of the first region is implanted using a first predetermined concentration of the Nitrogen ions. The thin surface on the surface of the silicon in the second region is implanted using a second predetermined concentration of the Nitrogen ions. An oxidation process is subsequently performed. The first predetermined thickness and the second predetermined thickness of the silicon oxide layer are formed simultaneously on the surface of the silicon in the first region and in the second region. The Nitrogen ions are implanted in the surface of the silicon by forming the pulse nitrogen plasma in-situ.

Abstract: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an the presence of ultraviolet light and ozone gas, an ambient containing ozone gas or an ambient containing an NF3/ozone gas mixture.

Abstract: A method and apparatus for reducing fluorine and other sorbable contaminants in plasma reactor used in chemical vapor deposition process such as the deposition of silicon oxide layer by the reaction of TEOS and oxygen. According to the method of the present invention, plasma of an inert gas is maintained in plasma reactor following chamber clean to remove sorbable contaminants such as fluorine. The plasma clean is typically followed by seasoning of the reactor to block or retard remaining contaminants. According to one embodiment of the invention, the combination of chamber clean, plasma clean, and season film is conducted before PECVD oxide layer is deposited on wafer positioned in the plasma reactor.

Abstract: A method for using low dielectric SiOF in a process to manufacture semiconductor products, comprising the steps of obtaining a layer of SiOF, and depleting fluorine from a surface of the SiOF layer. In a preferred embodiment, the depleting step comprises the step of treating the surface of the layer of SiOF with a plasma containing ammonia. It is further preferred that the treated surface be passivated by a nitrite plasma. The invention also encompasses a semiconductor chip comprising an integrated circuit with at least a first and second layers, and with a dielective layer of SiOF disposed between the layers, wherein the SiOF dielectric layer includes a first region at one edge thereof which depleted of fluorine to a predetermined depth.

Abstract: A method and apparatus for reducing plasma-induced charging damage in a semiconducting device are provided. The method includes exposing an article having a dielectric material susceptible to plasma-induced charging, to vacuum-ultraviolet (VUV) radiation of an energy greater than the bandgap energy of the dielectric material during or after plasma processing of the device. The plasma-induced charge is conducted from, or recombined at, the charging site.

Abstract: The present invention relates to a method of reducing Si consumption during a self-aligned silicide process which employs a M—Si or M—Si—Ge alloy, where M is Co, Ni or CoNi, and a blanket layer of Si. The present invention is particularly useful in minimizing Si consumption in shallow junction and thin silicon-on-insulator (SOI) electronic devices.

Abstract: A method is given to form a thin film on a surface of a semiconductor wafer. The surface has at least a first region, containing an inner portion of the wafer, and a second region, containing an outer portion of the wafer, and slopes outward from the first region to the second region. The method starts with performing an in-situ inert gas plasma treatment on the surface of the semiconductor wafer to generate different temperatures from the first region to the second region. Different deposition rates of a precursor A from the first region to the second region are thus generated so as to form a flat surface. Then a precursor A-chemical vapor deposition (CVD) process is performed to form the thin film with the flat surface immediately after performing the inert gas plasma treatment.

Abstract: In a method for manufacturing an insulating film using a fluid source material without inviting corrosion of metal wiring or the problem of poisoned via, after making a SiO2 film as a base layer on an Si substrate defining an uneven surface with an Al alloy wiring by plasma CVD using SiH4 and N2O, and further making an inter-layer insualting film having a fluidity on the SiO2 film by low pressure CVD using SiH4 or organosilane and H2O2, O2 plasma processing is applied to the inter-layer insulating film. After that, a SiO2 film as a cap layer is made on the inter-layer insulating film by plasma CVD using SiH4 and N2O. Rapid thermal annealing using lamp heating or O3 annealing may be done in lieu of O2 plasma processing.

Abstract: A disclosed process use low pressure chemical vapor deposition (LPCVD) of doped oxide film on a substrate. The process includes the steps of providing a substrate in an LPCVD reactor and flowing BTBAS and oxygen into the LPCVD reactor to react on the substrate to deposit an oxide film on the substrate. A doped precursor is flowed into the LPCVD reactor to dope the oxide film as it is deposited on the substrate. This process produces doped oxide film at a relatively low LPCVD reaction temperature.

Abstract: A method of selectively forming either an epi-Si-containing or a silicide layer on portions of a Si-containing substrate wherein a nitrogen-containing layer formed by a low-temperature nitridation process is employed to prevent formation of the epi-Si-containing or silicide layer in predetermined areas of the substrate. The method of the present invention includes the steps of subjecting at least one exposed surface of a Si-containing substrate to a low- temperature nitridation process so as to form a nitrogen-containing layer at or near the at least one exposed surface, wherein other surfaces of the Si-containing substrate are protected by a patterned photoresist; removing the patterned photoresist from the other surfaces of the Si-containing substrate; and forming an epi-Si-containing layer or a silicide layer on the other surfaces of the substrate which do not contain the nitrogen-containing layer.

Abstract: A process for forming a composite intermetal dielectric, (IMD), layer, with reduced tensile stress, eliminating defects that can be induced by highly stressed, IMD layers, to underlying dielectric layers, and metal interconnect structures, has been developed. The process features the use of a capping, or overlying, silicon oxide component, obtained via PECVD procedures, using TEOS as a source, and using a set of power, and frequency conditions, resulting in a high compressive stress for the capping silicon oxide layer. The high compressive stress of the capping silicon oxide layer, balances the high tensile stress, inherent in an underlying silicon oxide component, of the composite IMD layer, eliminating stress related defects to underlying dielectric layers, and to underlying metal interconnect structures.

Abstract: A method for significantly reducing plasma damage during the deposition of inter-layer dielectric (ILD) gapfills on topographic substrates by high density plasma chemical vapor deposition (HDP-CVD). The method can also be applied to the deposition of dielectric layers on silicon oxide covered substrates. The method provides a modification of current state of the art practices in HDP-CVD by a novel variation in the RF input power to the plasma processing chamber during certain portions of the processing cycle. Specifically, top/side RF power is reduced from 3000W/4000W to 1300W/3100W during the heat-up portion of the cycle and plasma lift is eliminated during the wafer release and lift portion of the cycle by turning off the 1000W/2000W top/side RF power. A method for determining the degree of plasma induced damage by measurement of a flatband voltage is also provided.

Abstract: A method of improving adhesion of a cap oxide to nanoporous silica for integrated circuit fabrication. In one embodiment, the method comprises several steps. The first step is to receive a wafer in a deposition chamber. Then a porous layer of material is deposited on the wafer. Next, a portion of the porous layer is densified in order to make it more compatible for adhesion to a cap layer. Finally, a cap layer is deposited onto the porous layer.

Abstract: A discharge electrode improves the uniformity of discharge such as plasma. The electrical discharge electrode, which receives high-frequency power and produces a discharge, comprises an electrode body adapted to receive high-frequency power, and a member for preventing the reflection of high-frequency power from the electrode body. The electrical discharge may comprise plasma generated by an electrical discharge.

Abstract: This invention discloses a method and apparatus where a pre-treatment which reduce interfacial level density is carried out before thin film deposition on a substrate utilizing a catalytic gas phase reaction. The catalytic gas phase reaction is generated with a treatment gas which is supplied with the substrate via a thermal catalysis body provided near the substrate surface. Thin film deposition on the substrate surface is carried out after this pre-treatment. The thermal catalysis body is made of tungsten, molybdenum, tantalum, titanium or vanadium, and is heated by a heater. And, this invention also discloses a semiconductor device having a semiconductor-insulator junction with its interfacial level density is 1012 eV −1cm−2 or less, which is brought by the above pre-treatment in the insulator film deposition process.

Abstract: The invention relates to a method for fabricating a microtechnical structure (28) having a depression (25), which has a high aspect ratio. In order to achieve a good filling behavior, it is proposed to increase the quantity of the passivating particles which are present in the reactor and passivate the surface of the structure (28) against further addition of the filling material (30). With suitable process control, the additional passivation has an effect essentially only on the side walls (27) of the depression (25).

Abstract: Processing of applying ultraviolet rays to a front face of an insulating film material formed on a wafer W is performed, whereby a contact angle of the front face thereof becomes smaller. Accordingly, when an insulating film material is applied on the aforesaid front face, the material smoothly spreads, and projections and depressions never occur on a front face of an upper layer insulating film material. Thereby, it is possible to form the insulating film thick and flatter on a substrate.

Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.

Abstract: A method of formation of a damascene FSG film with good adhesion to silicon nitride in an HDP-CVD system. Silane (SiH4), silicon tetrafluoride (SiF4), oxygen (O2) and argon (Ar) are used as the reactant gases. SiH4, SiF4, and O2 react to form the FSG. Ar is introduced to promote gas dissociation. All four gases are used for depositing most of the FSG film. SiH4 is not used during deposition of the interfacial part of the FSG film. The interfacial part of the FSG film refers either to the topmost portion, if silicon nitride is to be deposited on top of the FSG or the bottom portion if the FSG is to be deposited on top of silicon nitride. Using SiH4 with the SiF4 tends to mitigate the destructive effects of SiF4 throughout most of the deposition. By removing the SiH4 from the deposition of the interfacial part of the FSG film less hydrogen is incorporated into the film in the interfacial region and adhesion to overlying or underlying silicon nitride is improved.

Abstract: A method of producing a low-k interconnect dielectric material, using PECVD processes and readily available precursors to produce carbon-doped silicon oxide (SiOC). SiOC dielectric materials are produced using conventional silane based gas precursors, of silane and nitrous oxide, along with hydrocarbon gas. The use of methane and acetylene in combination with silane based gas precursors is provided. Methane produces network terminating species, specifically methyl, which replaces oxygen in an Si—O bond within a silicon dioxide network. This increases the volume, reduces the density and the dielectric constant of the material. Acetylene acts as a possible source of carbon and as a modifier, reducing or eliminating undesirable bridging species, such as carbene, or enhancing desireable network terminating species, such as methyl. Following implantation, the material is annealed to reduce the—OH and to potentially further lower the dielectric constant.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: Within a method for forming a dielectric layer within a microelectronic fabrication there is first provided a substrate. There is then formed over the substrate a carbon doped silicon containing dielectric layer. There is then treated the carbon doped silicon containing dielectric layer with an oxidizing plasma to form from the carbon doped silicon containing dielectric layer an oxidizing plasma treated carbon doped silicon containing dielectric layer.

Abstract: The method for manufacturing a silicon oxide film is characterized in that the method includes the steps of forming the silicon oxide film by a vapor deposition method or the like and of irradiating infrared light onto this silicon oxide film. Thus, according to the present invention, a silicon oxide film of relatively low quality formed at relatively low temperature can be improved to be a silicon oxide film of high quality. When the present invention is applied to a thin-film semiconductor device, a semiconductor device of high operational reliability and high performance can be manufactured.

Abstract: A method of forming an organic low k layer, for use as an interlevel dielectric layer in semiconductor integrated circuits, has been developed. An organic low k layer, such as a poly arylene ether layer, with a dielectric constant between about 2.6 to 2.8, is applied on an underlying metal interconnect pattern. The moisture contained in the as applied, organic low k layer, or the moisture absorbed by the organic low k layer, due to exposure to the environment, is then reduced via a high density plasma treatment, performed in a nitrogen ambient. The reduction in moisture can be accomplished, even when the organic low k layer had been exposed to the environment for a period of time as great as three months. The dielectric constant, of the organic low k layer, remains unchanged, as a result of the high density plasma treatment.

Abstract: A method is provided that conditions the chamber walls of a HDP CVD reactor by forming a layer of doped material prior to depositing dielectric layers of the doped material onto wafers. A consistent deposition rate can be maintained during subsequent deposition. When deposition is halted, the chamber is cleaned and a thin layer of the doped material is formed on the walls. Consequently, the chamber is kept at equilibrium even during periods of idle, thereby allowing the deposition rates to be consistent even after deposition resumes after the idle periods. For prolonged idle times, the chamber is re-cleaned and the doped material is re-deposited periodically, such as every 12 hours.

Abstract: A method of forming a PE-silane oxide layer with a greatly reduced particle count is described. A semiconductor substrate is provided over which a silicon oxide film is to be formed. The silicon oxide film is formed by the steps of: 1) pre-flowing a non-silane gas into a deposition chamber for at least two seconds whereby the pre-flowing step prevents formation of particles on the silicon oxide film, and 2) thereafter depositing a silicon oxide film by chemical vapor deposition by flowing a silane gas into the deposition chamber to complete formation of a silicon oxide film using plasma-enhanced chemical vapor deposition in the fabrication of an integrated circuit.

Abstract: In an atmosphere of processing gas, on a wafer W consisting mainly of silicon, through a planar-array antenna RLSA 60 having a plurality of slits, microwaves are irradiated to generate plasma containing oxygen, or nitrogen, or oxygen and nitrogen and to implement therewith on the surface of the wafer W direct oxidizing, nitriding, or oxy-nitriding to deposit an insulator film 2 of a thickness of 1 nm or less in terms of oxide film. A manufacturing method and apparatus of semiconductors that can successfully regulate film quality of the interface between a silicon substrate and a SiN film and can form SiN film of high quality in a short time can be obtained.

Abstract: An apparatus for fabricating a semiconductor device includes: a plasma torch having a hollow convey tube of which one end portion is made of a conductor so as to serve as an inner electrode, for injecting plasma generating gas through one end portion, conveying and spraying a plasma frame through the other end portion; an energy applying unit for applying a microwave to the gas conveyed through the convey tube and adds an energy thereto; an outer electrode for surrounding the other end portion of the convey tube and its extended portion coaxially; an insulation tube positioned between the convey tube and the outer electrode for electrically insulating the other end portion of the convey tube and the outer electrode and surrounding partially the convey tube coaxially; a power source for applying a voltage to the inner electrode and the outer electrode; a suscepter installed facing the plasma frame sprayed from the plasma torch; a suscepter moving unit for moving the suscepter in the vertical and horizontal dir

Abstract: A substrate processing system includes a housing defining a chamber for forming a film on the substrate surface of a substrate disposed within the chamber. The system includes a first plurality of nozzles that extend into the chamber for injecting a first chemical at a first distance from a periphery of the substrate surface, and a second plurality of nozzles that extend into the chamber for injecting a second chemical at a second distance from the periphery of the substrate surface. The second distance is substantially equal to or smaller than the first distance. In one embodiment, the first chemical contains a dielectric material and the second chemical contains dopant species which react with the first chemical to deposit a doped dielectric material on the substrate. Injecting the dopant species closer to the substrate surface than previously done ensures that the dopant species are distributed substantially uniformly over the substrate surface and the deposition of a stable doped dielectric layer.

Abstract: A deposition method for filling recesses in a substrate is described. In the method, the substrate is exposed to an energized deposition gas comprising first and second components, to deposit a first layer of a material in the recess, and thereafter, the ratio of the first component to the second component is reduced, to deposit a second layer of the material over the first layer in the recess. The deposition method may be used to fill recesses in a substrate and smoothen out reentrant cavities in a silicon nitride liner, in the fabrication of polysilicon gates in a substrate.

Abstract: Silicon nitride is formed on a supporting substrate by chemical vapor deposition using an antenna outside a vacuum reaction chamber to apply RF power to form an inductively coupled plasma from a reactant gas.

Abstract: A barrier layer is formed at a bottom portion, for example, of a through hole. The thickness of the barrier layer at an upper area, for example, of the through hole is made uniform. The method of manufacturing a semiconductor device includes the steps of: forming a barrier layer by sputtering on a main surface of a silicon substrate while maintaining a first distance between a main surface of the target and the main surface of the silicon substrate; and forming a titanium nitride layer by sputtering on and adjacent to a titanium nitride layer by scattering a target material while maintaining a second distance longer than the first distance between the main surface of the target and the main surface of the silicon substrate.

Abstract: Polycrystalline silicon film forming methods to improve movement of electrons and holes and thus allow the fabrication of high performance semiconductor elements is needed. In a method of the present invention, polycrystalline is formed utilizing as a material, a chemical compound comprising at least one type of impurity from among tin (Sn), germanium (Ge) and lead (Pb) and a polycrystalline silicon film doped with impurities from at least one type from among tin (Sn), germanium (Ge) and lead (Pb) thus formed. In another method, polycrystalline silicon is formed, and the polycrystalline silicon film thus obtained is afterwards then doped with an impurity consisting of at least one type from among tin (Sn), germanium (Ge) and lead (Pb).

Abstract: A variable high frequency rf bias is applied to a substrate during a high density plasma CVD process for filling gaps in integrated circuits with low dielectric material. The rf bias is varied by applying it as a pulse or by tailoring the magnitude of the rf bias. Preferably, a gasified organic precursor compound comprising silicon, oxygen and carbon atoms is flowed into the plasma CVD reaction chamber. Preferably, no reactive oxygen gas is used in the reaction chamber.

Abstract: Disclosed is a method for forming an interlayer insulating film which comprises the steps of forming an underlying insulating film on a substrate; forming a porous SiO2 film on the underlying insulating film by chemical vapor deposition method using Si2H6 and an oxidative gas as a reaction gas; subjecting the porous SiO2 film to H (hydrogen) plasma treatment; forming a plasma SiO2 film and a fluidic SiO2 film formed by TEOS+O3 on the porous SiO2 film; then smoothing a surface of the SiO2 film by etching; and forming a cover insulating film on the smoothed surface.

Abstract: A dielectric layer of silica glass is formed by plasma enhanced chemical vapor deposition (PECVD) wherein a gaseous precursor of the dielectric layer is supplied to a deposition chamber in the presence of an electromagnetic field. The supply of the gaseous precursor is discontinued while continuing to maintain the electromagnetic field for a delay time exceeding 0.5 seconds after the discontinuation of the supply of the gaseous precursor. This improves the hydrophilic properties of said film. A siloxane-based SOG film is deposited on the dielectric layer.

Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a dieletric layer with improved physical properties. There is first provided a substrate. There is then formed over the substrate a series of lines which constitute a patterned microelectronics layer. There is then formed over the patterned microelectronics layer and substrate a conformal dielectric layer. There is then formed over the substrate a second dielectric layer. There is then formed over the substrate a third dielectric layer formed of silicon oxide dielectric material employing high density plasma chemical vapor deposition (HDP-CVD) to complete a composite inter-level metal dielectric (IMD) layer. A fourth dielectric layer formed employing silicon containing dielectric material may be formed over the substrate and third dielectric layer to complete an inter-level metal dielectric (IMD) layer.

Abstract: A method for fabricating gate electrodes and gate interconnects with a protective silicon oxide or silicon nitride cap and spacer formed by high density plasma chemical vapor deposition (HDPCVD). Silicon oxide or silicon nitride is deposited in a reaction zone of a HDPCVD reactor while providing two or more selected substrate bias powers, source powers and/or selected gas mixtures to tailor the shape and thickness of the film for desired applications. In one embodiment, a low bias power of below 500 Watts is provided in a first stage HDPCVD and the bias power is then increased to between 500 and 3000 Watts for a second stage to produce a protective film having thin sidewall spacers for enhanced semiconductor device density and a relatively thick cap.

Abstract: A method and apparatus for depositing a film by chemical vapor deposition comprises a showerhead for dispersing reactant gases into the processing space wherein the showerhead has a first space therein operable for receiving and dispersing the first reacting gas, and has a second space therein, generally isolated from the first space, and operable for receiving and dispersing the second reactant gas separate from the first gas dispersion for maintaining segregation of reactant gases and generally preventing premature mixture of the gases prior to their introduction into the processing space to prevent premature deposition in the system.