Using Electromagnetic Or Wave Energy (e.g., Photo-induced Deposition, Plasma, Etc.) Patents (Class 438/788)
  • Patent number: 6897163
    Abstract: A method for depositing a low dielectric constant film is provided. The low dielectric constant film includes at least one silicon oxycarbide layer and at least one substantially silicon-free layer comprising carbon and hydrogen. The layers are deposited from a gas mixture including an organosilicon compound and a silicon-free hydrocarbon-based compound. The low dielectric constant film is deposited by a plasma process than includes pulses of RF power.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: May 24, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Frederic Gaillard, Srinivas D. Nemani
  • Patent number: 6890597
    Abstract: A combination of deposition and polishing steps are used to permit improved uniformity of a film after the combination of steps. Both the deposition and polishing are performed with processes that vary across the substrate. The combination of the varying deposition and etching rates results in a film that is substantially planar after the film has been polished. In some instances, it may be easier to control the variation of one of the two processes than the other so that the more controllable process is tailored to accommodate nonuniformities introduced by the less controllable process.
    Type: Grant
    Filed: May 9, 2003
    Date of Patent: May 10, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Padmanabhan Krishnaraj, Bruno Geoffrion, Michael S. Cox, Lin Zhang, Bikram Kapoor, Anchuan Wang, Zhenjiang Cui
  • Patent number: 6881590
    Abstract: First, a spin-on process is performed for forming a first dielectric layer over a plurality of metal interconnecting wires that are located on a semiconductor wafer. Then, an examining step is performed on the first dielectric layer, and the first dielectric layer is made to conform to a predetermined condition. Thereafter, an etching process is performed for completely removing the first dielectric layer. Subsequently, the semiconductor wafer is cleaned through use of a wet scrubber, and is dried. Finally, the spin-on process is re-performed for forming a second dielectric layer on the semiconductor wafer.
    Type: Grant
    Filed: August 25, 2003
    Date of Patent: April 19, 2005
    Assignee: Powerchip Semiconductor Corp.
    Inventor: Ching-Hsiu Wu
  • Patent number: 6881681
    Abstract: Heating a reaction chamber or other apparatus in the absence of product wafers to a “curing” temperature above a deposition temperature between the deposition of a film on a first set of semiconductor product wafers and the deposition of a film on a second set of semiconductor product wafers. In some embodiments, a boat with filler wafers is in the reaction chamber when the reaction chamber is heated to the curing temperature. In some examples, the films are deposited by a low pressure chemical vapor deposition (LPCVD) process. With some processes, if the deposition of a film on product wafers is at a temperature below a certain temperature, the film deposited with the product wafer on a boat, filler wafers, and/or other structures in the reaction chamber can cause contamination of product wafers subsequently deposited with a film in the presence of the boat and filler wafers.
    Type: Grant
    Filed: November 22, 2002
    Date of Patent: April 19, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Marc Rossow, Anna M. Phillips
  • Patent number: 6881683
    Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus. The silicon-containing hydrocarbon compound includes a cyclosiloxan compound or a linear siloxan compound, as a basal structure, with reactive groups for form oligomers using the basal structure. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant.
    Type: Grant
    Filed: December 11, 2002
    Date of Patent: April 19, 2005
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yasuyoshi Hyodo, Masashi Yamaguchi, Yoshinori Morisada, Atsuki Fukazawa, Manabu Kato, Shinya Kaneko, Devendra Kumar, Seijiro Umemoto
  • Patent number: 6878644
    Abstract: A method of filling a plurality of trenches etched in a substrate. In one embodiment the method includes depositing a layer of spin-on glass material over the substrate and into the plurality of trenches; curing the layer of spin-on glass material by exposing the spin-on glass material to electron beam radiation at a first temperature for a first period and subsequently exposing the spin-on glass material to an electron beam at a second temperature for a second period, where the second temperature is greater than the first temperature. The method concludes by depositing a layer of silica glass over the cured spin-on glass layer using a chemical vapor deposition technique.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: April 12, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Zhenjiang Cui, Rick J. Roberts, Michael S. Cox, Jun Zhao, Khaled Elsheref, Alexandros T. Demos
  • Patent number: 6875670
    Abstract: In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.
    Type: Grant
    Filed: February 1, 2001
    Date of Patent: April 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Han-Sin Lee, Moon-Han Park
  • Patent number: 6867086
    Abstract: High density plasma chemical vapor deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots are provided. This deposition part of the process may involve the use of any suitable high density plasma chemical vapor deposition (HDP CVD) chemistry. The etch back part of the process involves an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality gap fill operations.
    Type: Grant
    Filed: March 13, 2003
    Date of Patent: March 15, 2005
    Assignee: Novellus Systems, Inc.
    Inventors: David Chen, Robert A. Shepherd, Jr., Vishal Gauri, George D. Papasouliotis
  • Patent number: 6855644
    Abstract: The present invention provides a deposition method and deposition apparatus capable of forming a fluorine-containing silicon inorganic insulating film of stable film properties and a method of manufacturing a semiconductor device. Deposition apparatus 10 comprises parallel plate type electrodes 16, 22 arranged within reaction chamber 12, gas supply sources 20, 32, 34 for feeding process gas containing SiH4, SiF4 and oxygen source substance into reaction chamber 12, valves 36, 38, 40, gas mixing chamber 28 and power source 44 that supplies RF power for generating the plasma of the process gas. In this deposition apparatus 10, power source 44 is capable of supplying RF power of at least 1000 Watts to parallel plate type electrodes 16, 22. In this apparatus 10, fluorine-containing silicon oxide film is deposited on wafer 14 by generating the plasma of process gas containing SiH4, SiF4 and N2O.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: February 15, 2005
    Assignee: Applied Materials Inc.
    Inventors: Yoichi Suzuki, Tsutomu Shimayama
  • Patent number: 6849562
    Abstract: A method for depositing a low k dielectric film comprising silicon, carbon, and nitrogen is provided. The low k dielectric film is formed by a gas mixture comprising a silicon source, a carbon source, and NR1R2R3, wherein R1, R2, and R3 are selected from the group consisting of alkyl and phenyl groups. The low k dielectric film may be used as a barrier layer, an etch stop, an anti-reflective coating, or a hard mask.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: February 1, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Chi-I Lang, Li-Qun Xia, Ping Xu, Louis Yang
  • Patent number: 6838397
    Abstract: An object of the present invention is to apply an insulating film of cure and high quality that is suitably applicable as gate insulating film and protective film to a technique that the insulation film is formed on the glass substrate under a temperature of strain point or lower, and to a semiconductor device realizing high efficiency and high reliability by using it. In a semiconductor device of the present invention, a gate insulating film of a field effect type transistor with channel length of from 0.35 to 2.5 ?m in which a silicon nitride film is formed over a crystalline semiconductor film through a silicon oxide film, wherein the silicon nitride film contains hydrogen with the concentration of 1×1021/cm3 or less and has characteristic of an etching rate of 10 nm/min or less with respect to mixed solution containing an ammonium hydrogen fluoride (NH4HF2) of 7.13% and an ammonium fluoride (NH4F) of 15.4%.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: January 4, 2005
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toru Takayama, Shunpei Yamazaki, Kengo Akimoto
  • Patent number: 6838393
    Abstract: Methods are provided for depositing a silicon carbide layer having significantly reduced current leakage. The silicon carbide layer may be a barrier layer or part of a barrier bilayer that also includes a barrier layer. Methods for depositing oxygen-doped silicon carbide barrier layers are also provided. The silicon carbide layer may be deposited by reacting a gas mixture comprising an organosilicon compound, an aliphatic hydrocarbon comprising a carbon-carbon double bond or a carbon-carbon triple bond, and optionally, helium in a plasma. Alternatively, the silicon carbide layer may be deposited by reacting a gas mixture comprising hydrogen or argon and an organosilicon compound in a plasma.
    Type: Grant
    Filed: September 19, 2002
    Date of Patent: January 4, 2005
    Assignee: Applied Materials, Inc.
    Inventors: Kang Sub Yim, Melissa M. Tam, Dian Sugiarto, Chi-I Lang, Peter Wai-Man Lee, Li-Qun Xia
  • Publication number: 20040266221
    Abstract: Provided is a method of manufacturing a semiconductor device. According to the present invention, it is possible that an interlayer insulating film is planarized by forming the interlayer insulating film using multiple simultaneous deposition-and-etch processes without carrying out a subsequent planarization process. In addition, smoothness can be variably controlled by adjusting the deposition and etch rate.
    Type: Application
    Filed: December 22, 2003
    Publication date: December 30, 2004
    Inventor: Sang Deok Kim
  • Publication number: 20040266218
    Abstract: Methods of forming a gap filling layer using high density plasma are disclosed.
    Type: Application
    Filed: June 25, 2004
    Publication date: December 30, 2004
    Inventor: Young Min Kwon
  • Publication number: 20040259384
    Abstract: A two-stage plasma enhance dielectric deposition with a first stage of low capacitively-coupled RF bias with conformal deposition (202) followed by high capacitively-coupled RF bias for planarizing deposition (204) limits the charge build up on the underlying structure (104, 106, 108).
    Type: Application
    Filed: August 5, 2003
    Publication date: December 23, 2004
    Inventors: Somnath S. Nag, Girish A. Dixit, Srikanth Krishnan
  • Publication number: 20040256664
    Abstract: Methods for preparing a silicon oxynitride layer where the silicon oxynitride layer is deposited atop a substrate and have a low concentration of nitrogen at the interface of the silicon oxynitride layer and the substrate. The silicon oxynitride layer is formed by pulsing at least one interface precursor onto a substrate, where said substrate chemisorbs a portion of said at least one interface precursor to form a monolayer of said at least one interface precursor; and pulsing a nitrogen-containing precursor onto said substrate containing said monolayer of interface precursor, where said monolayer of said at least one interface precursor chemisorbs a portion of said nitrogen-containing precursor to form a monolayer of said nitrogen-containing precursor. The interface precursor includes oxygen-containing or silicon-containing precursor gasses.
    Type: Application
    Filed: June 18, 2003
    Publication date: December 23, 2004
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Anthony I. Chou, Michael P. Chudzik, Toshiharu Furukawa, Oleg Gluschenkov, Paul D. Kirsch, Kristen C. Scheer, Joseph Shepard
  • Patent number: 6830786
    Abstract: A silicon oxide film has a ratio of A1 to A2 which is not higher than 0.21, where A1 is a first peak integrated intensity of a first peak belonging to Si—OH and appearing in the vicinity of a wave-number of 970 cm−1, and A2 is a second peak integrated intensity of a second peak belonging to O—Si—O and appearing in the vicinity of a wave-number 820 cm−1, and each of the first and second peak integrated intensities is defined as a product of peak width at half height and a peak height of a Raman spectrum obtained by a Raman scattering spectroscopic analysis of the silicon oxide film. The silicon oxide film is deposited under a condition that a ratio of a first flow rate Fo of oxygen gas to a second flow rate Fsi of a silicon source gas is not lower than 20.
    Type: Grant
    Filed: July 18, 2002
    Date of Patent: December 14, 2004
    Assignee: NEC Corporation
    Inventors: Katsuhisa Yuda, Hiroshi Tanabe
  • Patent number: 6825562
    Abstract: A damascene structure, and a method of fabricating same, containing relatively low dielectric constant materials (e.g., k less than 3.8). A silicon-based, photosensitive material, such as plasma polymerized methylsilane (PPMS), is used to form both single and dual damascene structures containing low k materials. During the manufacturing process that forms the damascene structures, the silicon-based photosensitive material is used as both a hard mask and/or an etch stop.
    Type: Grant
    Filed: November 8, 2002
    Date of Patent: November 30, 2004
    Assignee: Applied Materials Inc.
    Inventors: Mehul B. Naik, Tim Weidman, Dian Sugiarto, Allen Zhao
  • Patent number: 6825134
    Abstract: A method of film layer deposition is described. A film layer is deposited using a cyclical deposition process. The cyclical deposition process consists essentially of a continuous flow of one or more process gases and the alternate pulsing of a precursor and energy to form a film on a substrate structure.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: November 30, 2004
    Assignee: Applied Materials, Inc.
    Inventors: Kam S. Law, Quanyuan Shang, William R. Harshbarger, Dan Maydan, Soo Young Choi, Beom Soo Park, Sanjay Yadav, John M. White
  • Patent number: 6825079
    Abstract: In order to form an oxide cover on a conductive filling in a trench in a semiconductor substrate an HDP oxide is deposited on the conductive filling using a PECVD method. In this case, the layer thickness on the horizontal surface of the conductive material is greater than the layer thickness on the sidewalls of the trench. Furthermore, the layer thickness is limited in such a way that the surface of the HDP oxide within the trench has a depth with respect to the surface of the semiconductor substrate surrounding the trench, or a layer disposed thereon. In a subsequent CMP step, the HDP oxide is removed from the surrounding surface. In an isotropic etching step, the HDP oxide is removed from the sidewalls. The result is a horizontal insulation layer with a layer thickness that varies only to a slight extent over the semiconductor substrate.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: November 30, 2004
    Assignee: Infineon Technologies AG
    Inventor: Martin Popp
  • Patent number: 6815373
    Abstract: A method for depositing a low dielectric constant film having a dielectric constant of about 3.5 or less is provided by blending one or more cyclic organosilicon compounds, one or more aliphatic organosilicon compounds, and one or more low molecular weight aliphatic hydrocarbon compounds. In one aspect, a gas mixture comprising one or more cyclic organosilicon compounds, one or more aliphatic organosilicon compounds, one or more aliphatic hydrocarbon compounds, one or more oxidizing gases, and a carrier gas is reacted at conditions sufficient to deposit a low dielectric constant film on a substrate surface.
    Type: Grant
    Filed: April 16, 2002
    Date of Patent: November 9, 2004
    Assignee: Applied Materials Inc.
    Inventors: Vinita Singh, Srinivas D. Nemani, Yi Zheng, Lihua Li, Tzu-Fang Huang, Li-Qun Xia, Ellie Yieh
  • Patent number: 6815374
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Grant
    Filed: June 9, 2003
    Date of Patent: November 9, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 6815350
    Abstract: A method for forming a ternary thin film using an atomic layer deposition process includes supplying a first and a second reactive material to a chamber containing a wafer, the first and second reactive materials being adsorbing on a surface of the wafer, supplying a first gas to the chamber to purge the first and second reactive materials that remain unreacted, supplying a third reactive material to the chamber to cause a reaction between the first and second reactive materials and the third reactive material to form a thin film monolayer, supplying a second gas to purge the third reactive material that remains unreacted and a byproduct, and repeating the above steps for forming the thin film monolayer a predetermined number of times to form a ternary thin film having a predetermined thickness on the wafer. Preferably, the ternary thin film is a SiBN film.
    Type: Grant
    Filed: March 5, 2003
    Date of Patent: November 9, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Young-Seok Kim, Yong-Woo Hyung, Man-Sung Kang, Jae-Young Ahn
  • Patent number: 6812159
    Abstract: A method of forming a dielectric layer that may be used as a dielectric separating a gate electrode from a channel region of a field effect transistor is provided which allows a high capacitive coupling while still maintaining a low leakage current level. This is achieved by introducing a dopant, for example nitrogen, that increases the resistance of the dielectric layer by means of low energy plasma irradiation, wherein an initial layer thickness is selected to substantially avoid penetration of the dopant into the underlying material. Subsequently, dielectric material is removed by an atomic layer etch to finally obtain the required design thickness.
    Type: Grant
    Filed: April 22, 2003
    Date of Patent: November 2, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Karsten Wieczorek, Falk Graetsch, Lutz Herrmann
  • Patent number: 6812164
    Abstract: A method for ionization film formation to form a deposited film by ionizing vaporized particles with an ionization mechanism of the hot-cathode system and injecting the ionized particles into a substrate is provided. The method includes the step of introducing He gas inside the ionization mechanism.
    Type: Grant
    Filed: January 24, 2003
    Date of Patent: November 2, 2004
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hirohito Yamaguchi, Masahiro Kanai, Atsushi Koike, Katsunori Oya
  • Publication number: 20040214413
    Abstract: By-products inside a furnace body of a CVD film forming apparatus after gas cleaning is performed in the furnace body are provided from being generated. The gas cleaning is performed in the furnace body by a plasma of a gas containing a halogen system gas and an Ar gas in an atmosphere in which the temperature of a heater disposed in the furnace body is approximately 500° C. or lower. Thereafter, a rise of the temperature of the heater is started. While the temperature of the heater is maintained constant, a film forming gas is introduced into the furnace body during a time period before the raised temperature reaches a temperature at which radicals or ions of a halogen system element are activated.
    Type: Application
    Filed: April 22, 2004
    Publication date: October 28, 2004
    Applicant: Trecenti Technologies, Inc.
    Inventors: Tomoyasu Nakamine, Kenichi Yamaguchi, Kenichi Satoh
  • Publication number: 20040214451
    Abstract: A method and system for forming a low defect oxide in a plasma processing chamber. By pulsing at least one of an RF power source and a processing gas, the growth of the oxide can be regulated. During periods in which the processing gas is not injected, an inert gas is injected to keep a substantially constant flow rate.
    Type: Application
    Filed: May 2, 2003
    Publication date: October 28, 2004
    Inventor: Wayne L. Johnson
  • Patent number: 6809043
    Abstract: A silicon oxide layer is deposited at a thickness of about 50 Å or less by a multi-stage method comprising depositing a sub-layer of silicon oxide in each stage by PECVD at a low deposition rate. Embodiments include depositing a silicon dioxide liner over a gate electrode in at least four stages, each stage comprising depositing a sub-layer at a thickness of 10 Å or less.
    Type: Grant
    Filed: June 19, 2002
    Date of Patent: October 26, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Minh Van Ngo, Robert A. Huertas, Hieu Pham
  • Patent number: 6809022
    Abstract: A method for forming dielectric layers is described. Wiring lines are formed on a provided semiconductor substrate. Spacers are formed on the sidewalls of the wiring lines. A liner layer is formed on the wiring lines and on the spacers by a first HDPCVD step, such as unbiased, unclamped HDPCVD. A dielectric layer is formed on the liner layer to cover the wiring lines and to fill gaps between the wiring lines by a second HDPCVD step.
    Type: Grant
    Filed: March 25, 2003
    Date of Patent: October 26, 2004
    Assignee: United Microelectronics Corp.
    Inventors: Chih-Chien Liu, Juan-Yuan Wu, Water Lur
  • Publication number: 20040209005
    Abstract: Disclosed is a film-forming method, comprising supplying into a plasma processing chamber at least three kinds of gases including a silicon compound gas, an oxidizing gas, and a rare gas, the percentage of the partial pressure of the rare gas (Pr) based on the total pressure being not smaller than 85%, i.e., 85%≦Pr<100%, and generating a plasma within the plasma processing chamber so as to form a film of silicon oxide on a substrate to be processed.
    Type: Application
    Filed: April 12, 2004
    Publication date: October 21, 2004
    Inventors: Masashi Goto, Kazufumi Azuma, Yukihiko Nakata
  • Publication number: 20040209487
    Abstract: A method of depositing a gate dielectric layer for a thin film transistor is provided. The gate dielectric layer is deposited using a plasma enhanced deposition with a gas mixture comprising a silicon and chlorine containing compound.
    Type: Application
    Filed: April 21, 2003
    Publication date: October 21, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Soo Young Choi, Beom Soo Park, Quanyuan Shang
  • Publication number: 20040198071
    Abstract: In a method of forming a silicon oxide film, the silicon oxide film is formed on a substrate by the use of a plasma CVD method. A plasma-generating region is separated from a deposition region which includes excitation oxygen molecules and excitation oxygen atoms. Plasma of first gas containing oxygen atoms is formed in the plasma-generating region while second gas containing silicon atoms is supplied into the deposition region. First quantity of the excitation oxygen molecules and second quantity of the excitation oxygen atoms are controlled intentionally.
    Type: Application
    Filed: April 27, 2004
    Publication date: October 7, 2004
    Inventors: Katsuhisa Yuda, Ge Xu
  • Patent number: 6800546
    Abstract: The present invention comprises the steps of performing a reforming process on a surface of a low dielectric constant insulation film formed on a substrate which includes one of a porous low dielectric constant insulation film and a non-porous low dielectric constant insulation film and forming an insulation film as at least one of an etching mask and a Chemical Mechanical Polishing stopper (CMP stopper) on the reformed surface of the low dielectric constant insulation film. For example, plasma is radiated as a reforming process mentioned above, the surface roughness of a low dielectric insulation film is increased and, as a result, adhesion between the films and also between the inter-layer insulation film and other neighboring films can be improved with so-called “anchor effect”.
    Type: Grant
    Filed: March 12, 2002
    Date of Patent: October 5, 2004
    Assignee: Tokyo Electron Limited
    Inventors: Nobuo Konishi, Mitsuaki Iwashita, Hiroki Ohno, Shigeru Kawamura, Masahito Sugiura
  • Patent number: 6800512
    Abstract: With keeping an atmosphere including oxygen within a chamber and with a wafer kept at a low temperature, plasma generated within the chamber is biased toward the wafer, and the wafer is subjected to the plasma. A semiconductor layer exposed on the wafer is oxidized into an oxide film. Thus, an oxide film can be formed even at room temperature differently from thermal oxidation. This oxidation is applicable to recovery of an implantation protection insulating film having been etched in cleaning a photoresist film, relaxation of a step formed between polysilicon films, relaxation of a step formed within trench and the like. Also, before removing a photoresist film used for forming a gate electrode including a metal, a contamination protection film can be formed by this oxidation with the photoresist film kept.
    Type: Grant
    Filed: September 14, 2000
    Date of Patent: October 5, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Kazuichiro Itonaga, Akihiro Yamamoto, Hiroaki Nakaoka, Isao Miyanaga, Yoshinao Harada
  • Patent number: 6797646
    Abstract: Embodiments of the present invention provide nitrogen doping of a fluorinated silicate glass (FSG) layer to improve adhesion between the nitrogen-containing FSG layer and other layers such as barrier layers. In some embodiments, a nitrogen-containing FSG layer is deposited on a substrate in a process chamber by supplying a gaseous mixture to the process chamber. The gaseous mixture comprises a silicon-containing gas, a fluorine-containing gas, an oxygen-containing gas, and a nitrogen-containing gas. Energy is provided to the gaseous mixture to deposit the nitrogen-containing FSG layer onto the substrate. A plasma may be formed from the gaseous mixture to deposit the layer. In some embodiments, an FSG film that has been formed is doped with nitrogen by a plasma treatment using a nitrogen-containing chemistry. For example, nitrogen ashing in a damascene process may introduce nitrogen dopants into the surface of the FSG layer.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: September 28, 2004
    Assignee: Applied Materials Inc.
    Inventors: Christopher Ngai, Christopher D. Bencher, Joe Feng, Peter Chen
  • Patent number: 6794270
    Abstract: A method for forming thoroughly deposited shallow trench isolation. A first oxide layer is formed conformally over the surface of a semiconductor substrate and on a trench thereon with an aspect ratio greater than 3. A liquid etching shield is filled in the trench by spin-spraying to cover the oxide layer in the trench. An etchant is then sprayed over the surface of the semiconductor substrate to remove the uncovered oxide layer and expose the surface of the semiconductor substrate. The density of the etchant is less than that of the liquid etching shield. A second oxide layer is deposited in the trench to form isolation without voids or seams.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: September 21, 2004
    Assignee: Nanya Technology Corporation
    Inventors: Pei-Ing Lee, Chang Rong Wu, Tzu En Ho, Yi-Nan Chen, Hsien Wen Su
  • Patent number: 6787483
    Abstract: Chemical vapor deposition processes are employed to fill high aspect ratio (typically at least 3:1), narrow width (typically 1.5 microns or less and even sub 0.15 micron) gaps with significantly reduced incidence of voids or weak spots. This deposition process involves the use of hydrogen as a process gas in the reactive mixture of a plasma containing CVD reactor. The process gas also includes dielectric forming precursor molecules such as silicon and oxygen containing molecules.
    Type: Grant
    Filed: May 20, 2003
    Date of Patent: September 7, 2004
    Assignee: Novellus Systems, Inc.
    Inventors: Atiye Bayman, Md Sazzadur Rahman, Weijie Zhang, Bart van Schravendijk, Vishal Gauri, George D. Papasoulitotis, Vikram Singh
  • Patent number: 6787445
    Abstract: A fluorine-containing organic film is deposited on a semiconductor substrate using a material gas containing fluorocarbon as a main component in a reactor chamber of a plasma processing apparatus. The fluorine-containing organic film is then exposed to plasma of a rare gas in the same reactor chamber to densify the fluorine-containing organic film.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: September 7, 2004
    Assignee: Matsushita Electric Industry Co., Ltd.
    Inventors: Nobuhiro Jiwari, Shinichi Imai
  • Patent number: 6787482
    Abstract: An embodiment of the present invention teaches a capacitor dielectric in a wafer cluster tool for semiconductor device fabrication formed by a method by the steps of: forming nitride adjacent a layer by rapid thermal nitridation; and subjecting the nitride to an ozone ambient, wherein the ozone ambient is selected from the group consisting of an ambient containing an ultraviolet/ozone mixture, an ambient containing an ozone or an ambient containing an NF3/ozone mixture.
    Type: Grant
    Filed: August 14, 2002
    Date of Patent: September 7, 2004
    Assignee: Micron Technology, Inc.
    Inventors: Randhir P. S. Thakur, Brett Rolfson
  • Publication number: 20040171224
    Abstract: A semiconductor device having a self-aligned contact hole is formed by providing a side wall oxide film on a gate electrode, covering the gate electrode and the side wall oxide film by an oxide film and further covering the oxide film by a nitride film, wherein the oxide film is formed by a plasma CVD process with a reduced plasma power such that the H2O content in the oxide film is less than about 2.4 wt %.
    Type: Application
    Filed: March 8, 2004
    Publication date: September 2, 2004
    Applicant: FUJITSU LIMITED
    Inventors: Kousuke Suzuki, Katsuyuki Karakawa
  • Patent number: 6784122
    Abstract: A method for depositing highly conformal silicate glass layers via chemical vapor deposition through the reaction of TEOS and O3 comprises placing an in-process semiconductor wafer having multiple surface constituents in a plasma-enhanced chemical vapor deposition chamber.
    Type: Grant
    Filed: February 21, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventor: Ravi Iyer
  • Patent number: 6784123
    Abstract: An insulation film is formed on a semiconductor substrate by vaporizing a silicon-containing hydrocarbon compound to provide a source gas, introducing a reaction gas composed of the source gas and an additive gas such as an inert gas and oxidizing gas to a reaction space of a plasma CVD apparatus, and depositing a siloxan polymer film by plasma polymerization at a temperature of −50° C.-100° C. The residence time of the reaction gas in the reaction space is lengthened by reducing the total flow of the reaction gas in such a way as to form a siloxan polymer film with a low dielectric constant such as 2.5.
    Type: Grant
    Filed: March 27, 2003
    Date of Patent: August 31, 2004
    Assignee: ASM Japan K.K.
    Inventors: Nobuo Matsuki, Yoshinori Morisada, Yasuyoshi Hyodo, Seijiro Umemoto
  • Patent number: 6784119
    Abstract: A method for processing a substrate comprising depositing a dielectric layer comprising silicon, oxygen, and carbon on the substrate by chemical vapor deposition, wherein the dielectric layer has a carbon content of at least 1% by atomic weight and a dielectric constant of less than about 3, and depositing a silicon and carbon containing layer on the dielectric layer. The dielectric constant of a dielectric layer deposited by reaction of an organosilicon compound having three or more methyl groups is significantly reduced by further depositing an amorphous hydrogenated silicon carbide layer by reaction of an alkylsilane in a plasma of a relatively inert gas.
    Type: Grant
    Filed: July 31, 2003
    Date of Patent: August 31, 2004
    Assignee: Applied Materials Inc.
    Inventors: Frederic Gaillard, Li-Qun Xia, Tian-Hoe Lim, Ellie Yieh, Wai-Fan Yau, Shin-Puu Jeng, Kuowei Liu, Yung-Cheng Lu
  • Patent number: 6784092
    Abstract: Disclosed is a method for forming an insulating layer, including coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight, and heating the coated film while irradiating the coated film with an electron beam.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
  • Patent number: 6784083
    Abstract: The present invention provides a method and apparatus for an atomic layer deposition process. The apparatus includes a chamber adapted to receive a first precursor gas, at least one surface interior to the chamber, and an acoustic wave driver coupled to the at least one surface and adapted to drive acoustic waves along the interior surface.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: August 31, 2004
    Assignee: Micron Technology, Inc.
    Inventors: F. Dan Gealy, Cem Basceri
  • Patent number: 6784095
    Abstract: Improved dielectric layers are formed by surface treating the dielectric layer with a phosphine plasma prior to forming a barrier layer thereon. Embodiments include forming a trench in a low k dielectric layer and modifying the side surfaces of the trench by subjecting the dielectric to a phosphine plasma produced in PECVD chamber. A conductive feature is formed by depositing a conformal barrier layer on the low k dielectric including the treated side surfaces of the dielectric and depositing a copper containing layer within the trench.
    Type: Grant
    Filed: February 12, 2002
    Date of Patent: August 31, 2004
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Suzette K. Pangrle, Minh Van Ngo, Dawn Hopper, Lu You
  • Publication number: 20040166694
    Abstract: High-density plasma CVD processes with improved gap filling characteristics are provided. In one exemplary process, the process includes loading a semiconductor substrate into a process chamber. First main process gases, including a silicon source gas, an oxygen gas, a nitrogen free chemical etching gas and a hydrogen gas, are then injected into the process chamber. Thus, a high-density plasma is generated over the semiconductor substrate, and the semiconductor substrate is heated to a temperature in the range of about 550° C. to about 700° C. by the high-density plasma. Thus, a silicon oxide layer is formed to completely fill a gap region without any voids or defects in the semiconductor substrate. In addition, the first main process gases can be replaced with second main process gases including a silicon source gas, an oxygen gas, a nitrogen free chemical etching gas, a hydrogen gas and a helium gas.
    Type: Application
    Filed: November 26, 2003
    Publication date: August 26, 2004
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jai-Hyung Won, Young-Kyou Park
  • Publication number: 20040166695
    Abstract: A method of filling a gap which is defined by adjacent raised features on a substrate includes providing a flow of a silicon-containing processing gas to a chamber housing the substrate, providing a flow of an oxidizing processing gas to the chamber, and providing a flow of a phosphorous-containing processing gas to the chamber. The method also includes depositing a first portion of a P-doped silicon oxide film as a substantially conformal layer in the gap by causing a reaction between the silicon-containing processing gas, the phosphorous-containing processing gas, and the oxidizing processing gas. Depositing the conformal layer includes varying over time a ratio of the (silicon-containing processing gas plus phosphorous-containing processing gas):(oxidizing processing gas) and maintaining the temperature of the substrate below about 500° C. throughout deposition of the conformal layer. The method also includes depositing a second portion of the P-doped silicon oxide film as a bulk layer.
    Type: Application
    Filed: January 14, 2004
    Publication date: August 26, 2004
    Applicant: Applied Materials, Inc.
    Inventors: Zheng Yuan, Shankar Venkataraman, Cary Ching, Shang Wong, Kevin Mikio Mukai, Nitin K. Ingle
  • Patent number: 6780790
    Abstract: A semiconductor device having a barrier insulating film covering a copper wiring is formed by a plasma enhanced CVD method. The method includes supplying high frequency power of a frequency of 1 MHz or more to a first electrode, and holding a substrate on which copper wiring is formed on a second electrode facing the first electrode; supplying a film forming gas containing an alkyl compound and an oxygen-containing gas between the first and second electrodes while regulating gas pressure of the film forming gas to 1 Torr or less; and supplying high frequency power to either of the first and second electrodes to convert the film forming gas into a plasma, and allowing the alkyl compound and the oxygen-containing gas of the film forming gas to react to form a barrier insulating film covering the surface of the substrate.
    Type: Grant
    Filed: November 5, 2002
    Date of Patent: August 24, 2004
    Assignees: Canon Sales Co., Inc., Semiconductor Process Laboratory Co., Ltd.
    Inventors: Yoshimi Shioya, Yuhko Nishimoto, Tomomi Suzuki, Kazuo Maeda
  • Patent number: 6777354
    Abstract: The present invention provides a semiconductor device capable of preventing deterioration in carrier mobility of a semiconductor layer, which is a quality of the interface between the semiconductor layer and an insulating layer, and a method of manufacturing the semiconductor device. In the semiconductor device, an interface layer is provided between a semiconductor layer made of active polycrystalline silicon and an insulating layer made of silicon oxide. The nitrogen element in silicon nitride diffuses into the semiconductor layer made of active polycrystalline silicon to compensate for lattice strain of the active polycrystalline silicon film, to satisfy the desired quality of the interface between the semiconductor layer and the insulating layer.
    Type: Grant
    Filed: August 20, 2003
    Date of Patent: August 17, 2004
    Assignee: LG Philips LCD Co., Ltd.
    Inventor: Chae Gee Sung