Abstract: A step of preparing a stack is performed to position each single-crystal substrate in a first single-crystal substrate group and a first base substrate face to face with each other, position each single-crystal substrate in a second single-crystal substrate group and a second base substrate face to face with each other, and stack the first single-crystal substrate group, the first base substrate, an insertion portion, the second single-crystal substrate group, and the second base substrate in one direction in this order. Next, the stack is heated so as to allow a temperature of the stack to reach a temperature at which silicon carbide can sublime and so as to form a temperature gradient in the stack with the temperature thereof getting increased in the above-described direction. In this way, silicon carbide substrates can be manufactured efficiently.

Abstract: One embodiment of the present invention provides a semiconductor device manufacturing method, including: performing a laser spike annealing, by irradiating light, whose wavelength is 10 ?m to 11 ?m, onto a semiconductor substrate including: an active area; a circuit pattern; and a dummy pattern formed at a position, whose distance from an end of the active area is equal to or more than 10 ?m and equal to or less than 11 ?m, at a pitch equal to or more than 10 nm and equal to or less than 510 nm, while setting an angle formed between an arrangement direction of the dummy pattern and a projection direction of the light to be equal to or more than 0° and equal to or less than 30°.

Abstract: A process is disclosed for annealing a single crystal silicon wafer having a front surface and a back surface, and an oxide layer disposed on the front surface of the wafer extending over substantially all of the radial width. The process includes annealing the wafer in an annealing chamber having an atmosphere comprising oxygen. The process also includes maintaining a partial pressure of water above a predetermined value such that the wafer maintains the oxide layer through the annealing process. The annealed front surface is substantially free of boron and phosphorus.

Abstract: A method that is performed for heat treating a semiconductor wafer in a process chamber, as an intermediate part of an overall multi-step technique for processing the wafer, includes applying an energy transfer layer to at least a portion of the wafer, and exposing the wafer to an energy source in the process chamber in a way which subjects the wafer to a thermal profile such that the energy transfer layer influences at least one part of the thermal profile. The thermal profile has at least a first elevated temperature event. The method further includes, in time relation to the thermal profile, removing the energy transfer layer in the process chamber at least sufficiently for subjecting the wafer to a subsequent step. An associated intermediate condition of the wafer is described.

Abstract: A method of fabricating a semiconductor device is provided. The method includes forming a bottom electrode material layer containing aluminum and cupper over the substrate. An insulating material layer and a top electrode material layer are sequentially formed on the surface of the bottom electrode material layer. A photoresist pattern is formed on the top electrode material layer, and then the top electrode material layer is patterned to form a top electrode by using the photoresist pattern as mask. The photoresist pattern is removed by plasma ash and then an alloy process is performed to the bottom electrode material layer. Thereafter, the insulating material layer, and the bottom electrode material layer are patterned to form a patterned insulating layer and a patterned bottom electrode layer.

Abstract: A process for producing a carbon nanotube resistor that is capable of providing a highly reliable resistor or fuse. The process comprises the step of introducing a carbon nanotube in a volatile solvent to a first concentration and conducting ultrasonic treatment thereof to thereby obtain an initial solution; the dilution step of stepwise diluting the initial solution with a volatile solvent under ultrasonication so as to adjust the same to a second concentration, thereby obtaining a coating solution; and the step of applying the coating solution between a first electrode and a second electrode, wherein the first concentration is 1(E10?4 g/ml or higher and the second concentration lower than 1(E10?5 g/ml.

Abstract: A method of forming a semiconductor structure comprises providing a substrate and forming an insulator layer on the substrate. A first film is formed on the insulator layer. Thus, the first film can correspond to a device region of the semiconductor structure. A second film, comprising a second material that is different from the first material, is also formed on the insulator layer adjacent to the first film. The second material can comprise an isolation material (e.g., an oxide and/or nitride material) and can, for example comprise the same dielectric material as the insulator layer (e.g., silicon dioxide). The second film can correspond to an isolation region (e.g., a shallow trench isolation region) of the semiconductor structure. The second film is specifically formed with a first section having a first thickness and a second section having a second thickness that is different from the first thickness.

Abstract: In a substrate processing method, a substrate to be processed is mounted on a mounting table in a processing chamber of a substrate processing apparatus, and while heating the substrate by a heating unit through the mounting table to a processing temperature of 700° C. or higher, the substrate is processed. The substrate to be processed is loaded into the processing chamber, a first preliminary heating is performed until the substrate reaches a prescribed temperature while being mounted on the mounting table. Then, substrate supporting pins of the mounting table are elevated, and a second preliminary heating is performed in a state where the substrate is held on the substrate supporting pins. Then, the substrate supporting pins are moved down to mount the substrate on the mounting table and a process such as plasma oxidation is performed thereon.

Abstract: Provided are apparatuses and method for the thermal processing of a substrate surface, e.g., controlled laser thermal annealing (LTA) of substrates. The invention typically involves irradiating the substrate surface with first and second images to process regions of the substrate surface at a substantially uniform peak processing temperature along a scan path. A first image may serve to effect spike annealing of the substrates while another may be used to provide auxiliary heat treatment to the substrates before and/or after the spike annealing. Control over the temperature profile of the prespike and/or postspike may also reduce stresses and strains generated in the wafers. Also provided are microelectronic devices formed using the inventive apparatuses and methods.

Abstract: To simplify a peeling step in a method for manufacturing a semiconductor device including the peeling step. A first layer having a metal film is formed over a substrate; a second layer having a transistor is formed over the first layer having the metal film; a resin material is applied over the layer having the transistor; the resin material is cured by a heat treatment at a first heat treatment temperature to form a resin layer; the layer having the transistor is peeled from the substrate by a heat treatment at a second heat treatment temperature which is higher than the first heat treatment temperature; and the resin layer is peeled from the layer having the transistor by a heat treatment at a third heat treatment temperature which is higher than the second heat treatment temperature.

Abstract: A method of manufacturing an image sensor is provided. In this method, a photoelectric conversion unit may be formed within a semiconductor substrate, wherein the semiconductor substrate includes an active pixel region and an optical black region. An annealing layer may be formed on the active pixel region and the optical black region and etched so that the annealing layer covers at least a portion of the optical black region. A wiring pattern may be formed on the annealing layer. A light-blocking pattern may be formed on the wiring pattern so as to cover the entire photoelectric conversion unit of the optical black region, thereby blocking light from being incident upon the optical black region.

Abstract: Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.

Abstract: A thermal cycle includes: increasing a temperature from an initial temperature to a temperature T1 at an arbitrary rate R1 (° C./sec); holding the temperature at the temperature T1 for an arbitrary period t1 (sec); increasing the temperature from the temperature T1 to a temperature T2 at a rate R2 (° C./sec) of 1.0×107 (° C./sec) or less; and holding the temperature at the temperature T2 for a period t2 (sec) of 50 msec or less. The thermal cycle thereafter includes: decreasing the temperature from the temperature T2 to the temperature T1 at a rate R1? (° C./sec) of 1.0×107 (° C./sec) or less; holding the temperature T1 for an arbitrary period t3 (sec); and decreasing the temperature from the temperature T1 to a final temperature at an arbitrary rate R2? (° C./sec). Such a thermal cycle is successively repeated in a plurality of iterations.

Abstract: An object of the present invention is to perform temperature setting of a heating plate so that a wafer is uniformly heated in an actual heat processing time. The temperature of a wafer is measured during a heat processing period from immediately after a temperature measuring wafer is mounted on the heating plate to the time when the actual heat processing time elapses. Whether the uniformity in temperature within the wafer is allowable or not is determined from the temperature of the wafer in the heat processing period, and if the determination result is negative, a correction value for a temperature setting parameter of the heating plate is calculated using a correction value calculation model from the measurement result, and the temperature setting parameter is changed.

Abstract: A Configurable device comprising, a logic die connected by at least one through silicon-via (TSV), to an input/output (I/O) die.

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract: A wafer laser processing method for forming deteriorated layers in the inside of a wafer having a device area and a peripheral excess area surrounding the device area, the surface of the device area being higher than the surface of the peripheral excess area, involving a first step for forming a deteriorated layer in the insides of the peripheral excess area and device area by applying a laser beam to the peripheral excess area and the device area with its focal point set in the material of the peripheral excess area and the device area from the front surface side of the wafer; and a second step for forming a deteriorated layer in the inside of the device area by applying a laser beam to the device area with its focal point set in the material of the device area without applying the laser beam to the peripheral excess area.

Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.

Abstract: Provided is a silicon wafer including: a first denuded zone formed with a predetermined depth from a top surface of the silicon wafer; and a bulk area formed between the first denuded zone and a backside of the silicon wafer, wherein the first denuded zone is formed with a depth ranging from approximately 20 um to approximately 80 um from the top surface, and wherein a concentration of oxygen in the bulk area is uniformly distributed within a variation of 10% over the bulk area.

Abstract: A method for selective oxidation of silicon containing materials in a semiconductor device is disclosed and claimed. In one aspect, a rapid thermal processing apparatus is used to selectively oxidize a substrate by in-situ steam generation at high pressure in a hydrogen rich atmosphere. Other materials, such as metals and barrier layers, in the substrate are not oxidized.

Abstract: A method for wafer bonding two substrates activated by ion implantation is disclosed. An in situ ion bonding chamber allows ion activation and bonding to occur within an existing process tool utilized in a manufacturing process line. Ion activation of at least one of the substrates is performed at low implant energies to ensure that the wafer material below the thin surface layers remains unaffected by the ion activation.

Abstract: A method of manufacturing a semiconductor device including a substrate; an insulating film formed thereon; a first semiconductor layer where strain is induced in the directions parallel to the surface of the substrate, the first semiconductor layer being on the insulating film; a source region and a drain region formed in the first semiconductor layer; and a gate layered body formed of a gate insulating film and a gate electrode on the first semiconductor layer is disclosed. The method includes the steps of (a) forming a second semiconductor layer by epitaxial growth on the first semiconductor layer; (b) heating the second semiconductor layer; and (c) removing the second semiconductor layer. The second semiconductor layer is different in lattice constant in an in-plane direction from the first semiconductor layer. Step (b) induces the strain in the first semiconductor layer by exposing the surface of the second semiconductor layer to energy lines.

Abstract: A semiconductor manufacturing process is provided. First, a wafer with a material layer and an exposed photoresist layer formed thereon is provided, wherein the wafer has a center area and an edge area. Thereafter, the property of the exposed photoresist layer is varied, so as to make a critical dimension of the exposed photoresist layer in the center area different from that of the same in the edge area. After the edge property of the exposed photoresist layer is varied, an etching process is performed to the wafer by using the exposed photoresist layer as a mask, so as to make a patterned material layer having a uniform critical dimension formed on the wafer.

Abstract: A technique for fabricating an array of imaging pixels includes fabricating front side components on a front side of the array. After fabricating the front side components, a dopant layer is implanted on a backside of the array. A mask is formed over the dopant layer to selectively expose portions of the dopant layer. Next, the exposed portions of the dopant layer are laser annealed. Alternatively, the mask may be disposed over the backside prior to the formation of the dopant layer and the dopants implanted through the exposed portions and subsequently laser annealed.

Abstract: Apparatus and method for performing laser thermal annealing (LTA) of a substrate using an annealing radiation beam that is not substantially absorbed in the substrate at room temperature. The method takes advantage of the fact that the absorption of long wavelength radiation (1 micron or greater) in some substrates, such as undoped silicon substrates, is a strong function of temperature. The method includes heating the substrate to a critical temperature where the absorption of long-wavelength annealing radiation is substantial, and then irradiating the substrate with the annealing radiation to generate a temperature capable of annealing the substrate.

Abstract: A substrate treating device comprising a treatment chamber for storing and treating substrates and a heating device having a heating element and a heat insulator and heating the substrates in the treatment chamber by the heating element. The heating element is so formed that only its one end is held by a holding part, and a projection projected to the treatment chamber side at the intermediate part of the heating element and positioned in proximity to or in contact with the heating element is formed on the heat insulator. A pin with an enlarged part is passed through the heating element and the heat insulator at the intermediate part of the heating element and the enlarged part is positioned in proximity to or in contact with the heating element. The plurality of projections may be formed on the heat insulator and the pins may be disposed between these plurality of projections.

Abstract: Provided is a method for producing an SOI substrate having a thick-film SOI layer, in which an ion-implanted layer is formed by implanting at least one kind of ion of hydrogen ion and a rare gas ion into a surface of a bond wafer, an SOI substrate having an SOI layer is produced by, after the ion-implanted surface of the bond wafer and a surface of a base wafer are bonded together via an oxide film, delaminating the bond wafer along the ion-implanted layer, heat treatment is performed on the SOI substrate having the SOI layer in a reducing atmosphere containing hydrogen or an atmosphere containing hydrogen chloride gas, and, after the surface of the SOI layer is polished by CMP, a silicon epitaxial layer is grown on the SOI layer of the SOI substrate.

Abstract: A method for manufacturing heterostructures for applications in the fields of electronics, optics or opto-electronics. This method includes providing a silicon oxide layer with a thickness of less than or equal to 25 nanometers on one of a donor substrate or a receiver substrate or on both substrates, heat treating the substrate(s) that contains the silicon oxide layer at 900° C. to 1,200° C. under a neutral or reducing atmosphere that contains at least one of argon or hydrogen to form layer trapping through-holes inside the silicon oxide, bonding the substrates together at a bonding interface with the silicon oxide layer(s) positioned between them, reinforcing the bonding by annealing the substrates at 25° C. to 500° C. such that the trapping holes retaining gas species at the bonding interface, and transferring an active layer as a portion of the donor substrate onto the receiver substrate to obtain the heterostructure.

Abstract: A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds.

Abstract: An arrangement, process and mask for implementing single-scan continuous motion sequential lateral solidification of a thin film provided on a sample such that artifacts formed at the edges of the beamlets irradiating the thin film are significantly reduced. According to this invention, the edge areas of the previously irradiated and resolidified areas which likely have artifacts provided therein are overlapped by the subsequent beamlets. In this manner, the edge areas of the previously resolidified irradiated areas and artifacts therein are completely melted throughout their thickness. At least the subsequent beamlets are shaped such that the grains of the previously irradiated and resolidified areas which border the edge areas melted by the subsequent beamlets grow into these resolidifying edges areas so as to substantially reduce or eliminate the artifacts.

Abstract: A method for configuring J electromagnetic radiation sources (J?2) to simultaneously irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. For simultaneous exposure of the I stacks to radiation from the J sources, Pj is computed such that an error E being a function of |W1?S1|, |W2?S2, . . . , |WI?SI| is about minimized with respect to Pj=1, . . . , J). Wi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i (i=1, . . . , I). The stacks are exposed to the radiation from the sources characterized by the computed Pj (j=1, . . . , J).

Abstract: A silicon dioxide-based dielectric layer is formed on a substrate surface by a sequential deposition/anneal technique. The deposited layer thickness is insufficient to prevent substantially complete penetration of annealing process agents into the layer and migration of water out of the layer. The dielectric layer is then annealed, ideally at a moderate temperature, to remove water and thereby fully densify the film. The deposition and anneal processes are then repeated until a desired dielectric film thickness is achieved.

Abstract: A method of fabricating an integrated circuit includes providing a gate conductor spaced above a semiconductor substrate by a gate dielectric, a pair of dielectric spacers disposed on sidewall surfaces of the gate conductor, and source and drain regions disposed in the substrate on opposite sides of the dielectric spacers, wherein the gate conductor and the source and drain regions comprise dopants; and subjecting at least a portion of the dopants to at least 3 consecutive anneal exposures to activate the dopants, wherein a duration of each exposure is about 200 microseconds to about 5 milliseconds.

Abstract: An accelerated and simple-to-realize fast method for thermally converting metallic precursor layers on any desired substrates into semiconducting layers, and also an apparatus suitable for carrying out the method and serving for producing solar modules with high efficiency are provided. The substrates previously prepared at least with a metallic precursor layer are heated in a furnace, which is segmented into a plurality of temperature regions, at a pressure at approximately atmospheric ambient pressure in a plurality of steps in each case to a predetermined temperature up to an end temperature between 400° C. and 600° C. and are converted into semiconducting layers whilst maintaining the end temperature in an atmosphere comprising a mixture of a carrier gas and vaporous chalcogens.

Abstract: A method for forming a poly-silicon film, using sequential lateral solidification (SLS) by laser irradiation through an optical device to pattern the laser beam and provide a periodic energy profile on the edges of transparent regions so as to widen the poly-silicon grains and achieve grain size uniformity. The optical device comprises a plurality of first transparent regions with a length of L, wherein at least one side of the edge of each of the first transparent regions has a first periodic shape.

Abstract: By performing sophisticated anneal techniques, such as laser anneal, flash anneal and the like, for a metal silicide formation, such as nickel silicide, the risk of nickel silicide defects in sensitive device regions, such as SRAM pass gates, may be significantly reduced. Also, the activation of dopants may be performed in a highly localized manner, so that undue damage of gate insulation layers may be avoided when activating and re-crystallizing drain and source regions.

Abstract: A semiconductor device is fabricated while mitigating conductive void formation in metallization layers. A substrate is provided. A first dielectric layer is formed over the substrate. A conductive trench is formed within the first dielectric layer. An etch stop layer is formed over the first dielectric layer. A second dielectric layer is formed over/on the etch stop layer. A resist mask is formed over the device and via openings are etched in the second dielectric layer. The resist mask is removed by an ash process. A clean process is performed that mitigates/reduces surface charge on exposed portions of the etch stop layer. Additional surface charge reduction techniques are employed. The via openings are filled with a conductive material and a planarization process is performed to remove excess fill material.

Abstract: A method and apparatus are provided for treating a substrate. The substrate is positioned on a support in a thermal treatment chamber. Electromagnetic radiation is directed toward the substrate to anneal a portion of the substrate. Other electromagnetic radiation is directed toward the substrate to preheat a portion of the substrate. The preheating reduces thermal stresses at the boundary between the preheat region and the anneal region. Any number of anneal and preheat regions are contemplated, with varying shapes and temperature profiles, as needed for specific embodiments. Any convenient source of electromagnetic radiation may be used, such as lasers, heat lamps, white light lamps, or flash lamps.

Abstract: In one embodiment, a gate insulating layer, a conductive layer, and a metal layer are formed over a semiconductor substrate. An ion implantation region is formed in an interface of the conductive layer and the metal layer by performing an ion implantation process. A flash annealing process is performed on the ion-implanted semiconductor substrate. The metal layer, the conductive layer, and the gate insulating layer are patterned.

Abstract: A substrate, thermal treatment assembly and method of operating the thermal treatment assembly are described for controlling the temperature of a substrate. An electrical potential is applied across two or more locations on the substrate in order to generate an electrical current through a portion of the substrate, thereby altering a temperature of the substrate. The electrical current may dissipate electrical energy in the form of thermal energy due to the intrinsic resistance of the portion of substrate to the flow of electrical current.

Abstract: The objects of the present invention are to form MEMS structures of which stress is controlled while maintaining the performance of high-performance LSI, to integrate MEMS Structures and LSI on a single chip, to electrically and chemically protect the MEMS structure and to reduce the stress of the whole movable part of the MEMS structure. To achieve the above objects, a silicide film formable at a low temperature is used for the MEMS structure. The temperature at the silicide film deposition T1 is selected optionally with reference the heat treatment temperature T2 and the pseudo-crystallization temperature T3. T2, the temperature of manufacturing process after the silicide film deposition, is determined does not cause the degradation of the characteristics of the high-performance LSI indispensable. Thus, the residual stress of the MEMS structures may be controlled.

Abstract: Disclosed are a method for forming a silicon thin-film on a substrate, and more particularly a method for forming a polycrystalline silicon thin-film of good quality on a flexible metal substrate. A metal substrate (110) is prepared and a surface of the metal substrate (110) is flattened. An insulation film (120) is formed on the metal substrate (110). An amorphous silicon layer (130) is formed on the insulation film (120). A metal layer (140) is formed on the amorphous silicon layer (130). A sample on the metal substrate (110) is heated and crystallized.

Abstract: A method for configuring J electromagnetic radiation sources (J?2) to serially irradiate a substrate. Each source has a different function of wavelength and angular distribution of emitted radiation. The substrate includes a base layer and I stacks (I?2; J?I) thereon. Pj denotes a same source-specific normally incident energy flux on each stack from source j. in each of I independent exposure steps, the I stacks are concurrently exposed to radiation from the J sources, Vi and Si respectively denote an actual and target energy flux transmitted into the substrate via stack i in exposure step i (i=1, . . . , I). t(i) and Pt(i) are computed such that: Vi is maximal through deployment of source t(i) as compared with deployment of any other source for i=1, . . . , I; and an error E being a function of |V1?S1|, |V2?S2|, . . . , |Vi?Si| is about minimized with respect to Pi (i=1, . . . , I).

Abstract: A method of forming an integrated circuit is provided. The method includes performing a multiple-time flash anneal process to a wafer, wherein the multiple-time flash anneal process comprises preheating the wafer to a first preheat temperature; performing a first flash on the wafer with a first flash energy; preheating the wafer to a second preheat temperature; and performing a second flash on the wafer with a second flash energy.

Abstract: Methods and systems are provided for low pressure baking to remove impurities from a semiconductor surface prior to deposition. Advantageously, the short, low temperature processes consume only a small portion of the thermal budget, while still proving effective at removing interfacial oxygen from the semiconductor surface. The methods and systems are particularly well suited for treating semiconductor surfaces before epitaxy.

Abstract: A method to laser anneal a silicon stack (or a silicon-rich alloy) including a heavily doped region buried beneath an undoped or lightly doped region is disclosed. By F selecting laser energy at a wavelength that tends to be transmitted by crystalline silicon and absorbed by amorphous silicon, crystallization progresses through the silicon layers in a manner that minimizes or prevents diffusion of dopants upward from the doped region to the undoped or lightly doped region. In preferred embodiments, the laser energy is pulsed, and a thermally conductive structure beneath the heavily doped layer dissipates heat, helping to control the anneal and limit dopant diffusion.

Abstract: A water processing method for providing a gettering sink effect to a wafer having a plurality of streets which are formed in a lattice pattern on the front surface of a substrate and devices which are formed in a plurality of areas sectioned by the plurality of streets, comprising the steps of removing distortion produced on the rear surface of the substrate of the wafer whose rear surface of the substrate has been ground to a predetermined thickness; forming a gettering sink effect layer by applying a laser beam of a wavelength having permeability for the substrate of the wafer which has undergone the distortion removing step, with its focal point set to the inside of the substrate to form a deteriorated layer in the inside of the substrate; and dividing the wafer which has undergone the gettering sink effect layer forming step, into individual chips along the streets.

Abstract: A method for manufacturing thin film semiconductor device is provided. The semiconductor thin film includes a semiconductor thin film and a gate electrode and has an active region turned into a polycrystalline region through irradiation with an energy beam. The gate electrode is provided to traverse the active region. In a channel part that is the active region overlapping with the gate electrode, a crystalline state is changed cyclically in a channel length direction, and areas each having a substantially same crystalline state traverse the channel part.

Abstract: A method for manufacturing a semiconductor structure is provided which includes the following operations: supplying a crystalline semiconductor substrate, providing a porous region adjacent to a surface of the semiconductor substrate, introducing a dopant into the porous region from the surface, and thermally recrystallizing the porous region into a crystalline doping region of the semiconductor substrate whose doping type and/or doping concentration and/or doping distribution are/is different from those or that of the semiconductor substrate. A corresponding semiconductor structure is likewise provided.

Abstract: A method for fabricating a semiconductor element includes the steps of: providing a semiconductor wafer; forming an oxide layer on the semiconductor wafer; carrying out a high-temperature thermal treatment to the semiconductor wafer at least once, wherein the high-temperature thermal treatment comprises a final high-temperature treatment, which is carried out lastly as the high-temperature thermal treatment; lowering a temperature of the semiconductor wafer, following the final high-temperature treatment, to a predetermined lower temperature; and exposing the semiconductor wafer to an oxidizing atmosphere after the temperature lowering process.