Abstract: In accordance with the invention, the structure of a patterned nanoscale or near nanoscale device (“nanostructure”) is repaired and/or enhanced by liquifying the patterned device in the presence of appropriate guiding conditions for a period of time and then permitting the device to solidify. Advantageous guiding conditions include adjacent spaced apart or contacting surfaces to control surface structure and preserve vertically. Unconstrained boundaries to permit smoothing of edge roughness. In an advantageous embodiment, a flat planar surface is disposed overlying a patterned nanostructure surface and the surface is liquified by a high intensity light source to repair or enhance the nanoscale features.

Abstract: A semiconductor device fabrication method comprises (1) forming a patterned mask layer on an oxide layer of a Mn-containing perovskite type oxide; (2) heat-treating the oxide layer; and (3) patterning the oxide layer with an etching solution containing at least one of hydrochloric acid, sulfuric acid, and nitric acid after the heat treatment of the oxide layer.

Abstract: An embodiment of a multilayer wafer according to the invention includes a base substrate, a first layer associated with the base substrate, and a second layer on the first layer on side opposite from the base substrate in an axial direction and having a lateral edge. The first layer includes a ridge that protrudes axially and is disposed laterally adjacent the second layer measured in a direction normal to the axial direction for protecting the lateral edge. This ridge can surround portion the lateral edge in an axial cross-section for preventing edge falls. Also, the ridge can have an axial height greater than the axial thickness of the second layer. In one embodiment, the second layer includes an oxydizable semiconductor and the first layer includes an oxidized insulator.

Abstract: A method of forming polycrystalline silicon with ultra-small grain sizes employs a differential heating of the upper and lower sides of the substrate of a CVD apparatus, in which the lower side of the substrate receives considerably more power than the upper side, preferable more than 75% of the power; and in which the substrate is maintained during deposition at a temperature more than 50° C. above the 550° C. crystallization temperature of silicon.

Abstract: A method of forming a polycrystalline silicon layer. An amorphous silicon layer on a substrate is completely melted using a laser beam passed through a mask so as to form a polycrystalline silicon layer. The upper portion of the polycrystalline silicon layer is then re-melted and re-crystallized using a laser beam passed through a mask. The mask includes a high transmittance region for completely melting the amorphous silicon layer and a low transmittance region for re-melting the upper portion of the polycrystalline silicon layer.

Abstract: A semiconductor structure includes a silicon substrate layer, a relaxed silicon-germanium layer on the silicon substrate layer and a strained single crystal silicon layer on the silicon-germanium layer. The silicon-germanium layer may include a thickness of 500 angstroms or less. The method for forming the semiconductor structure includes epitaxially forming the silicon-germanium layer and the single crystal silicon layer. The silicon-germanium layer is stressed upon formation. After the single crystal silicon layer is formed over the silicon-germanium layer, an RTA or laser heat treatment process selectively melts the silicon-germanium layer but not the single crystal silicon layer. The substantially molten silicon-germanium relaxes the compressive stresses in the silicon-germanium layer and yields a relaxed silicon-germanium layer and a strained single crystal silicon layer upon cooling.

Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.

Abstract: To provide a TFT that can operate at a high speed by forming a crystalline semiconductor film while controlling the position and the size of a crystal grain in the film to use the crystalline semiconductor film for a channel forming region of the TFT. Instead of a metal or a highly heat conductive insulating film, only a conventional insulating film is used as a base film to introduce a temperature gradient. A level difference of the base insulating film is provided in a desired location to generate the temperature distribution in the semiconductor film in accordance with the arrangement of the level difference. The starting point and the direction of lateral growth are controlled utilizing the temperature distribution.

Abstract: One embodiment of the present invention is a method for generating patterned features on a substrate that includes: (a) forming a first layer on at least a portion of a surface of the substrate, the first layer comprising at least one layer of a first material, which one layer abuts the surface of the substrate; (b) forming a second layer of a second material on at least a portion of the first layer, which second layer is imprinted with the patterned features; (c) removing at least portions of the second layer to extend the patterned features to the first layer; and (d) removing at least portions of the first layer to extend the patterned features to the substrate; wherein the first layer and the second layer may be exposed to an etching process that undercuts the patterned features, and the first material may be lifted-off.

Abstract: A method and apparatus for processing a thin metal layer on a substrate to control the grain size, grain shape, and grain boundary location and orientation in the metal layer by irradiating the metal layer with a first excimer laser pulse having an intensity pattern defined by a mask to have shadow regions and beamlets. Each region of the metal layer overlapped by a beamlet is melted throughout its entire thickness, and each region of the metal layer overlapped by a shadow region remains at least partially unmelted. Each at least partially unmelted region adjoins adjacent melted regions. After irradiation by the first excimer laser pulse, the melted regions of the metal layer are pemitted to resolidify. During resolidification, the at least partially unmelted regions seed growth of grains in adjoining melted regions to produce larger grains.

Abstract: A apparatus and method for determining minimum line widths of free standing structures built by a semiconductor (S/C) manufacturing process. Free standing structures are created in a semiconductor device and subjected to an aerosol process which is tuned and centered with respect to a critical line width for the free standing structures. The S/C manufacturing process is tuned responsive to failure of free standing structures of sub-critical line widths.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: A device and method for annealing a wafer. The preferred embodiment includes applying a basic thermal budget to a weakened zone of a wafer, substantially evenly over the weakened zone. The basic thermal budget is insufficient to detach a detachment layer from a remainder of the wafer at the weakened zone. An additional thermal budget is applied locally in an initiation region of the weakened zone to initiate the detachment of the detachment layer at the weakened zone.

Abstract: A method of forming a polycrystalline silicon layer. An amorphous silicon layer on a substrate is completely melted using a laser beam passed through a mask so as to form a polycrystalline silicon layer. The upper portion of the polycrystalline silicon layer is then re-melted and re-crystallized using a laser beam passed through a mask. The mask includes a high transmittance region for completely melting the amorphous silicon layer and a low transmittance region for re-melting the upper portion of the polycrystalline silicon layer.

Abstract: A process of lateral crystallization comprises providing a silicon film on a substrate surface, exposing a localized substrate region at the substrate surface to a laser heating source, and annealing a portion of the silicon film in thermal contact with the localized substrate region by exposing the silicon film to a low-fluence optical annealing source.

Abstract: In order to achieve temperature distribution, in particular a homogeneous temperature distribution in, for example, a substrate during a thermal treatment process of said substrate, a method is disclosed for the thermal treatment of substrates, in particular semi-conductor wafers, in a process chamber comprising at least one temperature distribution influencing element located in the process chamber. During thermal treatment, the spatial arrangement of the element is altered relative to the substrate and/or to the process chamber. A device for the thermal treatment of substrates in a process chamber is also disclosed, comprising at least one temperature distribution influencing element located in a process chamber wherein a device is provided in order to alter the spatial arrangement of the element relative to the substrate and/or to the process chamber during the thermal treatment process.

Abstract: There is provided a method for manufacturing a silicon wafer or a silicon epitaxial wafer capable of imparting an excellent IG capability thereto in a stable manner by simultaneously realizing higher density of oxide precipitates and larger sizes thereof at a stage prior to a device fabrication process. The present invention is a method for manufacturing a silicon wafer wherein the silicon wafer is subjected to heat treatment to impart a gettering capability thereto comprising at least the following three steps of: a temperature raising step A for generating oxygen precipitation nuclei; a temperature raising step B for growing the oxygen precipitation nuclei; and a constant temperature keeping step C for growing the oxygen precipitation nuclei into oxide precipitates of larger sizes.

Abstract: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time duration heats the substrate to a desired temperature. The desired temperature is then maintained by distancing the heated surfaces from the substrate and holding the heated surface at the increased distance to minimize further substrate heating.

Abstract: The invention provides a method of reducing the roughness of the free surface of a wafer of semiconductor material by applying a rapid thermal annealing process under a pure argon atmosphere for a time sufficient to uniformly heat and smooth the free surface of the wafer.

Abstract: A method and apparatus for controlling the temperature of at least one gas flowing into a processing chamber is provided. In one embodiment, a gas temperature control apparatus for semiconductor processing includes a gas delivery line coupled between a processing chamber and a gas source. An enclosure substantially encloses the gas delivery line and is adapted to flow a heat transfer fluid away from the processing chamber.

Abstract: By preparing fully-embedded interconnect structure samples for a cross-section analysis by means of electron microscopy or x-ray microscopy, degradation mechanisms may be efficiently monitored. Moreover, displaying some of the measurement results as a quick motion representation enables the detection of subtle changes of characteristics of an interconnect structure in a highly efficient manner.

Abstract: Pulsed processing methods and systems for heating objects such as semiconductor substrates feature process control for multi-pulse processing of a single substrate, or single or multi-pulse processing of different substrates having different physical properties. Heat is applied a controllable way to the object during a background heating mode, thereby selectively heating the object to at least generally produce a temperature rise throughout the object during background heating. A first surface of the object is heated in a pulsed heating mode by subjecting it to at least a first pulse of energy. Background heating is controlled in timed relation to the first pulse. A first temperature response of the object to the first energy pulse may be sensed and used to establish at least a second set of pulse parameters for at least a second energy pulse to at least partially produce a target condition.

Abstract: A method of forming an oxide film having high insularity capability is performed within an ultra clean environment, using charged particles.

Abstract: A floating substrate reactor allows heat treatment of a series of semiconductor substrates, one by one. The heat treatment occurs while flowing gas suspends a substrate between two heated surfaces of the reactor. The two heated surfaces each have multiple heating zones. The heating zones are heated to desired temperature(s) and a substrate is then loaded into the reactor for heat treatment. Upon loading, the relatively cold substrate absorbs heat and cools the process chamber. A heat spike, which can be varied, is applied to the heating zones to heat the reactor to the desired temperature again. The substrate, however, is unloaded from the reactor before the temperatures of the heating zones have reached the desired temperature. After the heating zones have reached the desired temperature, the next substrate in the series of substrates is loaded into the reactor for heat treatment.

Abstract: A conductive layer which is formed on an insulative layer on a semiconductor substrate is connected to the semiconductor substrate via a through portion which passes through the insulative layer and reaches the semiconductor substrate. In a state where the conductive layer is electrically connected to the semiconductor substrate via the through portion, a patterning process using a plasma etching is performed on the conductive layer, thereby forming a conductive path. After the formation of the conductive path, a heating process is performed on the substrate or the conductive path in order to disconnect the electrical connection between the through portion and the substrate by a reaction between the through portion and the semiconductor substrate which is in contact therewith.

Abstract: A batch-type etching method includes applying microwaves from the outside of a reaction chamber to semiconductor wafers after HF gas etching of the wafers to remove residual substances including H2O, CH3OH, CH3COOH and/or other by-products from surfaces of the wafers. Microwaves oscillate polar molecules of the substances and generate heat, thereby removing the substances.

Abstract: An apparatus of manufacturing a semiconductor device is disclosed which comprises at least one heat/light source opposing at least one major surface of a to-be-processed substrate, the heat/light source emitting light rays with a heating function onto the major surface of the to-be-processed substrate, and at least one light intensity adjusting member interposed between the heat/light source and the to-be-processed substrate, the light intensity adjusting member being made of a material which can pass therethrough the light rays, the light intensity adjusting member adjusting, to a substantially predetermined value, an intensity of the light rays at the major surface of the to-be-processed substrate.

Abstract: A method is proposed for locally heating a region that is disposed in a substrate. A substrate is provided and at least one region is produced in the substrate with a lower specific resistance than the surrounding substrate. The region is then locally heated by inducing eddy currents by irradiation with electromagnetic energy.

Abstract: A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas. The gas enters the internal cavity through a first passage at a first temperature, and exits the internal cavity at a second temperature through a second passage.

Abstract: A method and apparatus for fabrication of passivated microfluidic structures is disclosed. The method includes providing a substrate having a microfluidic structure formed therein. The microfluidic structure is embedded by an embedding layer. The method further includes passivating the embedded microfluidic structure by locally heating the microfluidic structure surface in a reactive atmosphere, wherein the passivated microfluidic structure is suitable for transporting a fluid.

Abstract: Provided is a process for manufacturing a silicon wafer employing heat treatment which is applied on the silicon wafer in inert gas atmosphere represented by Ar annealing to annihilate Grown-in defects in a surface layer region of the silicon wafer as well as to cause no degradation of haze and micro-roughness on a surface thereof. In a process for manufacturing a silicon wafer having a step of heat treating the silicon wafer in inert gas atmosphere, using a purge box with which the silicon wafer heat treated in the inert gas atmosphere can be unloaded to outside a reaction tube of a heat treatment furnace without being put into contact with the open air, the purge box is filled with mixed gas of nitrogen and oxygen or 100% oxygen gas, and the heat treated silicon wafer is unloaded into the purge box.

Abstract: A method of forming a polycrystalline silicon layer. An amorphous silicon layer on a substrate is completely melted using a laser beam passed through a mask so as to form a polycrystalline silicon layer. The upper portion of the polycrystalline silicon layer is then re-melted and re-crystallized using a laser beam passed through a mask. The mask includes a high transmittance region for completely melting the amorphous silicon layer and a low transmittance region for re-melting the upper portion of the polycrystalline silicon layer.

Abstract: An SOG film 16 obtained by heat-treating a polysilazan type SOG film at high temperature of about 800° C. is used as a planarized insulating film to be formed on the gate electrode (9; see FIGS. 31 and 32) of a MISFET (Qs, Qn, Qp) A polysilazan SOG film (57) not subjected to such a heat treatment is used as interlayer insulating film arranged among upper wiring layers (54, 55, 56, 62, 63).

Abstract: A method of crystallizing silicon including preparing a substrate having an amorphous silicon film formed thereon, aligning a mask having a first energy region and a second energy region over a first region of the amorphous silicon film formed on the substrate, irradiating a laser beam through the first and second energy regions of the mask onto the first region of the amorphous silicon film, crystallizing the first region of the amorphous silicon film by irradiating the laser beam through the first energy region of the mask, and activating the crystallized first region by irradiating the laser beam through the second energy region.

Abstract: A process for detaching two layers of material according to a weakened zone defined between the layers. This process includes the thermal annealing of a structure that incorporates the layers, with the annealing bringing the temperature from a starting temperature to a final annealing temperature while evolving according to a first phase up to a transition temperature, then according to a second phase during which the rise in temperature per unit of time is greater than that of the first phase. The invention also concerns an application for using this process in a particular semiconductor fabrication technique.

Abstract: A method of fabricating an annealed wafer of high quality by forming a defect-free active region of a device and controlling an irregular resistivity characteristic. The method includes a first annealing step of pre-heating a silicon wafer at a temperature of about 500° C. in a furnace in an ambience of a gas selected from the group consisting of Ar, N2 and an inert gas including Ar and N2; a second annealing step of changing the ambience of the gas into a 100% H2 gas ambience, increasing the temperature to 850° C.-1,150° C., and carrying out annealing for about an hour by maintaining the increased temperature; a third annealing step of changing the ambience of the gas into a 100% Ar gas ambience, increasing the temperature to about 1,200° C., and carrying out annealing for about an hour while the temperature of about 1,200° C. is maintained; and a temperature dropping step of decreasing the temperature in the furnace below about 500° C.

Abstract: A laser annealing method includes preparing a plurality of polycrystalline silicon film samples having different grains sizes, obtaining the energy density condition corresponding to the polycrystalline silicon film sample having the highest degree of scattering, adding a certain value of the energy density to the energy density condition obtained in the preceding step so as to determine a set value of the energy density, and irradiating the amorphous silicon thin film with a laser beam at the set value of the energy density determined in the preceding step so as to carry out the laser annealing.

Abstract: An ultraviolet-light-emitting semiconductor diode comprising an n-type ZnO layer with luminous characteristics formed on a transparent substrate, and a p-type semiconductor layer selected from the group consisting of SrCu2O2, CuAlO2 and CuGaO2, which is formed on the n-type ZnO layer to provide a p-n junction therebetween. The transparent substrate is preferably a single crystal substrate having atomically flat yttria-stabilized zirconia (YSZ) (III) surface. The n-type ZnO layer is formed on the transparent substrate having a temperature of 200 to 1200° C., and the p-type semiconductor layer selected from the group of SrCu2O2, CuAlO2 and CuGaO2 is formed on the n-type ZnO layer. The n-type ZnO layer may be formed without heating the substrate, and then the surface of the ZnO layer may be irradiated with ultraviolet light to promote crystallization therein.

Abstract: Methods of forming metal-doped chalcogenide layers and devices containing such doped chalcogenide layers include using a plasma to induce diffusion of metal into a chalcogenide layer concurrently with metal deposition. The plasma contains at least one noble gas of low atomic weight, such as neon or helium. The plasma has a sputter yield sufficient to sputter a metal target and a UV component of its emitted spectrum sufficient to induce diffusion of the sputtered metal into the chalcogenide layer. Using such methods, a conductive layer can be formed on the doped chalcogenide layer in situ. In integrated circuit devices, such as non-volatile chalcogenide memory devices, doping of the chalcogenide layer concurrently with metal deposition and formation of a conductive layer in situ with the doping of the chalcogenide layer reduces contamination concerns and physical damage resulting from moving the device substrate from tool to tool, thus facilitating improved device reliability.

Abstract: The object of the invention is to measure temperature using pyrometers, in a simple and economic way, enabling precise temperature measurement, even for low temperatures. The invention presents a device and method for thermally treating substrates, wherein the substrate is exposed to at least a first and at least a second radiation; the predetermined wavelengths of the first radiation are absorbed between the first radiation source and the substrate; a radiation from the substrate is measured in the predetermined wavelength using a radiation detector arranged on the same side as a second radiation source; the second radiation from the second radiation source is modulated and determined.

Abstract: A metal induced lateral crystallization (MILC) poly-silicon material is produced by depositing a metal in a predefined pattern on amorphous silicon, and heat treating the silicon at a first temperature to form a MILC poly-Si material. The MILC poly-Si material is further heat treated at a second temperature higher than the first temperature to induce recrystallization. The second high temperature recrystallization step significantly enhances the material structure, and in particular the grain structure, of the poly-Si material with substantial benefits to the performance of semiconductor devices made therefrom.

Abstract: In a method of forming a ferroelectric film according to the present invention, pulsed laser light or pulsed lamp light is applied to an amorphous oxide film formed over a substrate to form microcrystalline nuclei of oxide in the film. Crystallization of the oxide is performed by applying pulsed laser light or pulsed lamp light to the film including the microcrystalline nuclei to form the ferroelectric film.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely-spaced regions, such as a memory transistor array, and widely-spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely-spaced regions and a second thickness over the widely-spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely-spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely-spaced regions.

Abstract: A method for generating electrically conducting and/or semiconducting structures in three dimensions in a matrix that includes two or more materials in spatially separated material structures is disclosed. An electric field is applied to the separate material structure and the field is modulated spatially according to a protocol. The protocol represents a predetermined pattern of electrically conducting and/or semiconducting structures that are generated in the material structure in response to the field. The matrix composed by the material structures includes structures of this kind in three dimensions.

Abstract: A technique capable of preventing breakage of a semiconductor wafer in a single-wafer RTP apparatus is provided. Open-loop control is made in a temperature rising process, in which the temperature of the semiconductor wafer is 500° C. or lower, and a revolution speed of the semiconductor wafer is relatively reduced to 100 rpm or lower even if the bowing of the semiconductor wafer occurs. Therefore, a centrifugal force exerted on the semiconductor wafer is reduced, whereby it becomes possible to prevent the semiconductor wafer from dropping from a stage of the single-wafer RTP apparatus. Additionally, closed-loop control is made in the temperature rising process, in which the temperature of the semiconductor wafer is higher than 500° C., and in a main treatment process, and further the revolution speed of the semiconductor wafer is relatively increased.

Abstract: A device and method for annealing a wafer. The preferred embodiment includes applying a basic thermal budget to a weakened zone of a wafer, substantially evenly over the weakened zone. The basic thermal budget is insufficient to detach a detachment layer from a remainder of the wafer at the weakened zone. An additional thermal budget is applied locally in an initiation region of the weakened zone to initiate the detachment of the detachment layer at the weakened zone.

Abstract: An apparatus and method supports thermal processing of a microelectronic device such as a semiconductor chip in a substrate by heating the substrate with secondary radiation from an energy transfer device 40, which has a first set of energy transfer regions comprised of an emissive and thermally conductive material, and a second set of thermally insulating regions comprised of a reduced emissivity and reduced thermal conductivity material or free space. A multi-zone-radiant energy source 30 provides radiative energy to energy transfer device 40, with a process controller 36, preferably a multi-zone controller, altering the amount of energy provided by each heat zone associated with each emissive region of energy transfer device 40. Sensors detect the thermal energy level of each energy transfer region to allow controller 36 to adjust the secondary radiation emitted by each region in real time, resulting in a predetermined and controlled distribution of thermal energy on substrate 20.

Abstract: A first semiconductor layer is formed on a mother substrate, and the mother substrate is irradiated with irradiation light from a surface opposite to the first semiconductor layer, so that a thermally decomposed layer formed by thermally decomposing the first semiconductor layer between the first semiconductor layer and the mother substrate. Then, a second semiconductor layer including an active layer is formed on the first semiconductor layer in which the thermally decomposed layer is formed.

Abstract: An apparatus for and a method of heat-treating a wafer for use in producing a semiconductor device ensures a desired distribution of surface temperatures across the wafer. Spacers are used to space the wafer above a heat transfer plate. The spacers can be used to adjust the spacing and inclination of the wafer relative to the heat transfer plate by predetermined amounts determined in advance to produce the desired distribution of surface temperatures across the wafer during heat-treatment. With the present invention, wafers can be heat-treated during production using a plurality of bake units disposed in parallel because each of the bake units can be precisely adjusted using the spacers to produce surface temperature distributions similar to a standard surface temperature distribution. Accordingly, the productivity of the semiconductor manufacturing process can be markedly enhanced.

Abstract: A method for minimizing slip line faults on a surface of a semiconductor wafer that has been obtained using a transfer technique. The method includes heating the semiconductor wafer from an ambient temperature to a first higher temperature and pausing the heating at the first higher temperature for a time sufficient to stabilize the wafer. Then the wafer is heated further from the first higher temperature to a target higher temperature during a predetermined time interval. The further heating during an initial portion of the time interval is conducted at a relatively low heating rate and the heating during a final portion of the time interval is conducted at a relatively higher heating rate to thus minimize slip line faults in the surface of the wafer.

Abstract: An expansion joint for interior or exterior use including a fire barrier comprised of a fire resistant inorganic refractory fiber fabric sheet which supports resilient fire resistant inorganic refractory fibers. The support sheet may be closed to form a sleeve. When used as an exterior expansion joint a weather resistant cover comprising a bellows or a cover plate is employed. When used in an interior application a cover plate may be employed to form a bridge over the expansion joint to provide a continuous flooring or to provide additional fire resistance. The fabric is attached to adjacent structure by mounting flanges in the form of a bifurcated clamp, and one of the fabric-engaging clamp faces may be crimped and pierced to better grip the fabric.