Abstract: Provided is a method of manufacturing a semiconductor device. A first gate oxide layer is formed on a semiconductor substrate in which a core region and an input/output region are defined. The first gate oxide layer of the core region is selectively removed, and a second gate oxide layer is formed under the first gate oxide layer of the input/output region and on the semiconductor substrate of the core region. Nitrogen annealing is performed to form a nitrogen-rich oxide layer under the second gate oxide layer. An additional thermal process is performed to diffuse nitrogen segregated on an interface between the first gate oxide layer and the second gate oxide layer of the input/output region to a surface of the semiconductor substrate. Impurities generated during the additional thermal process are discharged to the outside.

Abstract: The invention provides methods for applying high temperature treatments to semiconductor wafers that limit surface tearing-off defects and surface particle contamination. In preferred embodiments, the high temperature treatments begin at boat-in temperatures of less than about 550° C. and include a first temperature ramp-up to the HT treatment temperatures at rates of 6° C./min or less. These methods are advantageously applied to semiconductor wafers comprising layers of different thermal properties, and in particular to semiconductor wafers comprising silicon-on-insulator structures.

Abstract: In conducting laser annealing using a CW laser or a quasi-CW laser, productivity is not high as compared with an excimer laser and thus, it is necessary to further enhance productivity. According to the present invention, a fundamental wave is used without putting laser light into a non linear optical element, and laser annealing is conducted by irradiating a semiconductor thin film with pulsed laser light having a high repetition rate. A laser oscillator having a high output power can be used for laser annealing, since a non linear optical element is not used and thus light is not converted to a harmonic. Therefore, the width of a region having large grain crystals that is formed by scanning once can be increased, and thus the productivity can be enhanced dramatically.

Abstract: A method of forming a semiconductor device. The method comprises steps of providing a substrate having a first transistor, a second transistor and non-salicide device formed thereon and the conductive type of the first transistor is different from that of the second transistor. A buffer layer is formed over the substrate and a tensile material layer is formed over the buffer layer. A portion of the tensile material layer over the second transistor is thinned and a spike annealing process is performed. The tensile material layer is removed to expose the buffer layer over the substrate and a patterned salicide blocking layer is formed over the non-salicide device. A salicide process is performed for forming a salicide layer on a portion of the first transistor and the second transistor.

Abstract: A silicon substrate having a first silicon oxide film formed via thermal oxidation and a second silicon oxide film formed via chemical vapor deposition and the like is subjected to preprocessing prior to selective epitaxial growth, wherein both the first and second silicon oxide films are etched with the same etching rate so as to completely remove the first silicon oxide film. Thus, it is possible to precisely control the sizes of contact holes formed in the silicon substrate, thus preventing contact plugs from short-circuiting with silicon epitaxial layers.

Abstract: The invention is related to an ALD method for depositing a layer including the steps of a) providing a semiconductor substrate in a reactor; b) providing a pulse of a first precursor gas into the reactor; c) providing a pulse of a second precursor gas into the reactor; d) providing an inert atmosphere in the reactor; and e) repeating step b) through step d), wherein at least once during step d) the semiconductor substrate is exposed to UV irradiation.

Abstract: An impurity-activating thermal process is performed after a target is subjected to an impurity introduction step. In this thermal process, while a spike RTA process including a holding period for holding a temperature at a predetermined temperature is performed, at least one iteration of millisecond annealing at a temperature higher than the predetermined temperature is performed during the holding period of the spike RTA process.

Abstract: Embodiments of the present invention are provided for improved contact doping and annealing systems and processes. In embodiments, a plasma ion immersion implantation (PIII) process is used for contact doping of nanowires and other nanoelement based thin film devices. According to further embodiments of the present invention, pulsed laser annealing using laser energy at relatively low laser fluences below about 100 mJ/cm2 (e.g., less than about 50 mJ/cm2, e.g., between about 2 and 18 mJ/cm2) is used to anneal nanowire and other nanoelement-based devices on substrates, such as low temperature flexible substrates, e.g., plastic substrates.

Abstract: A semiconductor device in one embodiment has a first connection region, a second connection region and a semiconductor volume arranged between the first and second connection regions. Provision is made, within the semiconductor volume, in the vicinity of the second connection region, of a field stop zone for spatially delimiting a space charge zone that can be formed in the semiconductor volume, and of an anode region adjoining the first connection region. The dopant concentration profile within the semiconductor volume is configured such that the integral of the ionized dopant charge over the semiconductor volume, proceeding from an interface of the anode region which faces the second connection region, in the direction of the second connection region, reaches a quantity of charge corresponding to the breakdown charge of the semiconductor device only near the interface of the field stop zone which faces the second connection region.

Abstract: Embodiments of the invention contemplate a method, apparatus and system that are used to support and position a substrate on a surface that is at a different temperature than the initial, or incoming, substrate temperature. Embodiments of the invention may also include a method of controlling the transfer of heat between a substrate and substrate support positioned in a processing chamber. The apparatus and methods described herein generally may also provide an inexpensive and simple way of accurately positioning a substrate on a substrate support that is positioned in a semiconductor processing chamber. Substrate processing chambers that can benefit from the various embodiments described herein include, but are not limited to RTP, CVD, PVD, ALD, plasma etching, and/or laser annealing chambers.

Abstract: A method of manufacturing a semiconductor device has forming a ferroelectric film over a substrate, placing the substrate having the ferroelectric film in a chamber substantially held in vacuum, introducing oxygen and an inert gas into the chamber, annealing the ferroelectric film in the chamber, and containing oxygen and the inert gas while the chamber is maintained sealed.

Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.

Abstract: A first layer (an insulating layer), a second layer (a metal layer), and a third layer (an insulating layer) are formed over a substrate. Then, a fourth layer including a semiconductor element is formed over the third layer. After applying an organic resin film covering the fourth layer, laser light is irradiated to sections of a rear surface side of the substrate. By irradiating the second layer with laser light, the state of being covered with the organic resin film can be maintained at the same time as forming a space under the organic resin film by ablating (alternatively, evaporating or breaking down) an irradiated region of the second layer, to cause a lift in the film in a periphery thereof.

Abstract: Semiconductor devices, structures and systems that utilize a polysilazane-based silicon oxide layer or fill, and methods of making the oxide layer are disclosed. In one embodiment, a polysilazane solution is deposited on a substrate and processed with ozone in a wet oxidation at low temperature to chemically modify the polysilazane material to a silicon oxide layer.

Abstract: In a production process for a semiconductor device employing an SiC semiconductor substrate (1), the SiC semiconductor substrate (1) is mounted on a susceptor (23), and a C heating member (3) of carbon is placed on a surface of the SiC semiconductor substrate (1). An annealing process is performed to form an impurity region in the surface of the SiC semiconductor substrate (1) by causing the susceptor (23) and the C heating member (3) to generate heat at high temperatures.

Abstract: A method of manufacturing a semiconductor device having damascene structures with air gaps is provided. In one embodiment, the method comprises the steps of depositing and patterning a disposable layer, depositing a first barrier layer on top of the patterned disposable layer, depositing a metal layer, planarizing the metal layer, depositing a second barrier layer, planarizing the second barrier layer until substantially no barrier layer material is present on top of the disposable layer, depositing a permeable layer, removing the disposable layer through the permeable layer to form air gaps.

Abstract: A method by which solid phase crystallization (SPC) thermal budget for crystallizing an undoped (or a lightly doped) amorphous Si (a-Si) is significantly reduced. First, a composite layer structure consisting of an undoped (or a lightly doped) a-Si layer and a heavily doped (either p-type or n-type) a-Si layer is formed and it is subsequently annealed at an elevated temperature. The solid phase crystallization starts from the heavily doped amorphous silicon layer at a substantially reduced thermal budget and proceeds to crystallize the undoped amorphous silicon layer in contact with the heavily doped film at reduced thermal budget. The method can be applied to form poly silicon thin film transistor at reduced thermal budgets.

Abstract: The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.

Abstract: The present invention relates to a method of fabricating a semiconductor-on-insulator-type heterostructure that includes at least one insulating layer interposed between a receiver substrate of semiconductor material and an active layer derived from a donor substrate of semiconductor material. The method includes the steps of bonding and active layer transfer. Prior to bonding, an atomic species which is identical or isoelectric with the insulating layer material is implanted in the insulating layer. The implantation forms a trapping layer, which can retain gaseous species present in the various interfaces of the heterostructure, thereby limiting formation of defects on the surface of the active layer.

Abstract: A semiconductor substrate is inserted into a heat treatment apparatus at a low temperature ranging from room temperature to about 50° C., and organic substances included in a metal on the semiconductor substrate are released without carbonization in an annealing process before CMP. Further, organic substances capable of preventing the corrosion of the metal are decomposed, and the organic substances themselves and chlorine, sulfuric acid, and ammonia which are included in the organic substances are diffused out of the metal film by setting the heat treatment apparatus at a rate of temperature rise of 15° C./min or less until a prescribed heat treatment temperature is reached.

Abstract: A method of heating-treating a semiconductor wafer is provided. In one embodiment, a first layer is formed over a first side of a substrate. A second layer is formed over the first layer and over a second side of the substrate and the wafer is then flash annealed. In another embodiment, a first layer is formed over a first side of a substrate and over a second side of the substrate. A second layer is formed over the first layers and the wafer is then flash annealed.

Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Abstract: The invention provides methods and systems for laser assisted wirebonding. One or more conditioning laser pulses are used to prepare a bonding surface for wirebonding by removing impurities such as residues from manufacturing processes, oxides, or irregularities on the bonding surface. Subsequently, a free air ball is brought into contact with the conditioned bonding surface to form a weld.

Abstract: A method of thermally treating a magnetic layer of a wafer, includes annealing, for a predetermined short duration, a magnetic layer of a single wafer, applying at least one local magnetic field to the magnetic layer obtained without making electrical contact to the wafer, and cooling the single wafer using argon. The annealing includes heating only a local area on the single wafer at a temperature of 280 degrees C for 60 seconds in the presence of a magnetic field using a rapid thermal anneal (RTA) lamp. The applying a magnetic field to the magnetic layer is conducted after the annealing and ancludes applying local fields in different directions to different areas of the single wafer. The single wafer includes a magnetic stack formed thereon, the magnetic stcak having a structure of 50TaN/50Ta/175PtMn/15CoFe/9Al/50Py/100TaN.

Abstract: A device for use in a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the wafer at an weakened zone. During annealing, the device applies (1) a basic thermal budget to the wafer, with the basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the weakened zone; and (2) an additional thermal budget is also applied to the wafer locally in a set region of the weakened zone so as to initiate the detachment of the layer in this region.

Abstract: A method for detaching a layer from a wafer. A weakened zone is created in the wafer to define the layer to be detached and a remainder portion of the wafer, such that the weakened zone includes a main region and a localized super-weakened region that is more weakened than the main region. Detachment of the layer from the remainder portion of the wafer is initiated at the super-weakened region such that the detachment properties to the main region to detach the layer from the remainder portion.

Abstract: There is described a method for producing a packaged integrated circuit. The method comprises a first step of building an integrated circuit having a micro-structure suspended above a micro-cavity, and having a heating element on the micro-structure capable of heating itself and its immediate surroundings. A layer of protective material is then deposited on said micro-structure such that at least a top surface of the micro-structure and an opening of the micro-cavity is covered, wherein the protective material is in a solid state at room temperature and can protect the micro-structure during silicon wafer dicing procedures and subsequent packaging. The integrated circuit is packaged and an electric current is passed through the heating element such that a portion of the protective material is removed and an unobstructed volume is provided above and below the micro-structure.

Abstract: A thermal treatment apparatus and method for processing a wafer are provided. The thermal treatment apparatus includes a process chamber for thermally treating the wafer, a heating unit for heating the wafer in the process chamber, and a gas supply unit for supplying a gas and controlling a gas pressure differently by sections of the wafer. The heating unit is provided in at least one of the upper side and the lower side of the process chamber. The heating unit includes a plurality of heater blocks capable of controlling a temperature for sections of the wafer.

Abstract: A method for fabricating a buried metallic layer at a predetermined vertical position in a semiconductor body having a first and second side includes a step of applying a metal layer to one of the first and second sides at least in sections. The method also includes establishing a positive temperature gradient in a vertical direction of the semiconductor body proceeding from the one side. The temperature in the region of the one side is higher than the eutectic temperatures of system, so that the metal of the metal layer migrates in the vertical direction into the semiconductor body. The method also includes discontinuing the temperature gradient once the metal reaches the predetermined vertical position in the semiconductor body, in order thereby to obtain the metallic layer at the predetermined position.

Abstract: The main object of the present invention is to provide a method for manufacturing efficiently a pattern formed structure which has a surface having a property-varied pattern and can be used to manufacture a color filter or the like. In order to achieve the object, the present invention provides a method for manufacturing a pattern formed structure, comprising: a patterning substrate preparing process of preparing a patterning substrate having a base material and a photocatalyst-containing property variable layer which is formed on the base material, comprises at least a photocatalyst and a binder, and has a property variable by action of the photocatalyst based on irradiation with energy; and an energy radiating process of radiating energy onto the patterning substrate at an intensity of 0.1 to 10 mW/cm2, thereby forming a property variable pattern in which the property of the photocatalyst-containing property variable layer is varied.

Abstract: Process and system for processing wafer-shaped objects, such as semiconductor wafers is disclosed. In accordance with the present disclosure, a multiple of two wafers are processed in a thermal processing chamber. The thermal processing chamber is in communication with at least one heating device for heating the wafers. The wafers are placed in the thermal processing chamber in a face-to-face configuration or in a back-to-back configuration.

Abstract: Methods for forming a dense dielectric layer over the surface of an opening in a porous inter-layer dielectric having an ultra-low dielectric constant are disclosed. The disclosure provides methods for exposing the sidewall surface and the bottom surface of the opening to a plurality of substantially parallel ultra-violet (UV) radiation rays to form a dense dielectric layer having a substantially uniform thickness over both the sidewall surface and the bottom surface.

Abstract: A substrate undergoes a semiconductor fabrication process at different temperatures in a reactor without changing the temperature of the reactor. The substrate is held suspended by flowing gas between two heated surfaces of the reactor. Moving the two heated surfaces in close proximity with the substrate for a particular time duration heats the substrate to a desired temperature. The desired temperature is then maintained by distancing the heated surfaces from the substrate and holding the heated surface at the increased distance to minimize further substrate heating.

Abstract: A method for forming a semiconductor device comprises forming a dielectric layer over a semiconductor wafer substrate assembly having closely spaced regions, such as a memory transistor array, and widely spaced regions, such as a periphery. Under conditions specified, the dielectric layer forms to have a first thickness over the closely spaced regions and a second thickness over the widely spaced regions. The second thickness is much thinner than the first thickness and dielectric over the widely spaced regions may be etched away with a blanket etch which leaves the majority of the dielectric layer over the closely spaced regions.

Abstract: Methods are disclosed for depositing materials selectively and controllably from liquid, near-critical, and/or supercritical fluids to a substrate or surface controlling the location and/or thickness of material(s) deposited to the surface or substrate. In one exemplary process, metals are deposited selectively filling feature patterns (e.g., vias) of substrates. The process can be further used to control deposition of materials on sub-surfaces of composite or structured silicon wafers, e.g., for the deposition of barrier films on silicon wafer surfaces. Materials include, but are not limited to, overburden materials, metals, non-metals, layered materials, organics, polymers, and semiconductor materials. The instant invention finds application in such commercial processes as semiconductor chip manufacturing.

Abstract: Methods of forming a nano-structure for electron extraction are disclosed. One method of forming a nano-structure comprises irradiating an area on a first surface of a thermal conductive film to melt the area across the film. The film is insulated on a second surface to provide two-dimensional heat transfer across the film. The liquid density of the film is greater than the solid density thereof. The method further comprises cooling the area inwardly from the periphery thereof to form a nano-structure having an apical nano-tip for electron extraction.

Abstract: A method for enhancing photoluminescence includes providing a film disposed over a substrate, the film including at least one of a semiconductor and a dielectric material. A first annealing step is performed at a first temperature in a processing chamber or annealing furnace; and, thereafter, a second annealing step is performed at a second temperature in the processing chamber or annealing furnace. The second temperature is greater than the first temperature, and the photoluminescence of the film after the second annealing step is greater than the photoluminescence of the film without the first annealing step.

Abstract: A first laser beam is emitted from a first laser oscillator in a pulsed manner at a high repetition frequency, and converged onto a substrate by a first intermediate optical system 2 so as to form a slit-like first beam spot. A second laser beam is emitted from a second laser beam oscillator in a pulsed manner to rise precedent to and fall subsequent to the first laser beam, and converged onto the substrate by a second intermediate optical system so as to form a second beam spot similar in configuration to the first beam spot and to contain the first beam spot. Crystallization of a semiconductor thin film on the substrate is carried out while the substrate or the first, second beam spots are moved. Thereby, the whole semiconductor thin film is formed into a crystal surface that has grown in one direction and free from ridges. Thus, the semiconductor thin film has an extremely flat surface, extremely few defects, large crystal grains and high throughput.

Abstract: A manufacturing apparatus for a semiconductor device that includes a bake chamber for a wafer with a coating film formed thereon to be baked at a predetermined temperature, a cooling chamber connected to the bake chamber, a first carrying unit for the baked wafer to be carried in the cooling chamber, a first temperature control unit for the wafer carried by the first carrying unit to be cooled down, and an unloading gate for unloading the wafer cooled down from the cooling chamber.

Abstract: A sequential lateral solidification apparatus includes a laser generator for generating and emitting a laser beam; an X-Y stage movable in two orthogonal axial directions; and a mask arranged between the laser generator and the X-Y stage. The mask has a plurality of slits through which the laser beam passes. An objective lens for scaling down the laser beam is arranged between the mask and the X-Y stage. A mask stage is connected to the mask for controlling minute movement of the mask for crystallizing amorphous silicon in one block.

Abstract: A system, method and apparatus for processing a semiconductor device including a processing chamber and a heating assembly positioned within the processing chamber. The heating assembly including at least a plate defining an internal cavity configured to receive gas. The gas enters the internal cavity through a first passage at a first temperature, and exits the internal cavity at a second temperature through a second passage.

Abstract: A degas apparatus for fabricating a semiconductor device is provided. The degas apparatus includes a chamber into which a wafer is loaded, a heating unit, disposed within the chamber, for heating the wafer to activate impurities remaining on the wafer, and a vacuum suction unit for sucking gases within the chamber by means of vacuum suction to discharge the activated impurities on the wafer to the outside. The degas apparatus also includes a hydrogen supply unit for supplying a hydrogen (H2) gas to the chamber, which is heated by the heating unit, to remove and/or prevent formation of a metal oxide layer on the wafer.

Abstract: A method for crystallizing an amorphous silicon layer is provided. (A) A substrate with an amorphous silicon layer thereon is provided. (B) A mask with a mask pattern is provided. The mask pattern includes a first region pattern and a second region pattern in mirror symmetry. (C) The first region pattern is selected as a first scanning region and the substrate is moved toward a first direction, such that a laser beam passes through the first region pattern to crystallize the amorphous silicon layer along the first direction. (D) The second region pattern is selected as a second scanning region and the substrate is moved toward a second direction, such that the laser beam passes through the second region pattern to crystallize the amorphous silicon layer along the second direction. (E) The steps of (C) and (D) are repeated to convert the whole amorphous silicon layer into a polysilicon layer.

Abstract: A manufacturing method of a semiconductor device, comprises; a process of heat-treating a semiconductor substrate under the ordinary pressure and in an oxidizing atmosphere; and a process of heat-treating the semiconductor substrate under the ordinary pressure and in an inert atmosphere, wherein heat-treating time or heat-treating temperature in heat treatment in the oxidizing atmosphere is changed based on the fluctuation of atmospheric pressure, and the heat-treating time in the inert atmosphere is determined based on the heat-treating time or the heat-treating temperature in the oxidizing atmosphere.

Abstract: The present invention provides a method for producing a nitrogen-doped annealed wafer, wherein before a wafer sliced from a silicon single crystal doped with at least nitrogen and polished is subjected to a high temperature heat treatment at 1100° C. to 1350° C. in an atmosphere of argon, hydrogen or a mixed gas thereof, a step of maintaining the wafer at a temperature lower than the treatment temperature of the high temperature heat treatment is conducted to allow growth of oxygen precipitation nuclei having such a size that the nuclei should be annihilated by the high temperature heat treatment to such a size that the nuclei should not be annihilated by the high temperature heat treatment, and then the high temperature heat treatment is performed.

Abstract: A strained semiconductor layer is achieved by a method for transferring stress from a dielectric layer to a semiconductor layer. The method comprises providing a substrate having a semiconductor layer. A dielectric layer having a stress is formed over the semiconductor layer. A radiation anneal is applied over the dielectric layer of a duration not exceeding 10 milliseconds to cause the stress of the dielectric layer to create a stress in the semiconductor layer. The dielectric layer may then be removed. At least a portion of the stress in the semiconductor layer remains in the semiconductor layer after the dielectric layer is removed. The radiation anneal can be either by using either a laser beam or a flash tool. The radiation anneal can also be used to activate source/drain regions.

Abstract: Monocrystalline semiconductor wafers have defect-reduced regions, the defect-reduced regions having a density of GOI-relevant defects within the range of 0/cm2 to 0.1/cm2 and occupy overall an areal proportion of 10% to 100% of the planar area of the semiconductor wafer, wherein the remaining regions of the semiconductor wafer have a significantly higher defect density than the defect-reduced regions. The wafers may be produced by a method for annealing GOI relevant defects in the wafer, by irradiating defined regions of a side of the semiconductor wafer by laser wherein each location is irradiated with a power density of 1 GW/m2 to 10 GW/m2 for at least 25 ms, wherein the laser emits radiation of a wavelength above the absorption edge of the wafer semiconductor material and wherein the temperature of the wafer rises by less than 20 K as a result of irradiation.

Abstract: The invention relates to a method for fabricating a reference layer for MRAM memory cells and an MRAM memory cell equipped with a reference layer of this type. A reference layer of this type comprises two magnetically coupled layers having a different Curie temperature. When cooling from a temperature above the Curie temperature TC1 of the first layer in an external magnetic field, the magnetization of the second layer is oriented by a second-order phase transition along the field direction of the external magnetic field. Upon further cooling below the Curie temperature TC2 of the second layer, the latter is oriented antiparallel with respect to the first layer as a result of the antiferromagnetic coupling between the two layers.

Abstract: A process for detaching two layers of material according to a weakened zone defined between the layers. This process includes the thermal annealing of a structure that incorporates the layers, with the annealing bringing the temperature from a starting temperature to a final annealing temperature while evolving according to a first phase up to a transition temperature, then according to a second phase during which the rise in temperature per unit of time is greater than that of the first phase. The invention also concerns an application for using this process in a particular semiconductor fabrication technique.

Abstract: A method of processing a substrate, comprising forming a chemically amplified resist film on a substrate, irradiating energy beams to the chemically amplified resist film to form a latent image therein, carrying out heat treatment with respect to the chemically amplified resist film, heating treatment being carried out in a manner of relatively moving a heating section for heating the chemically amplified resist film and the substrate forming a gas stream flowing reverse to the relatively moving direction of the heating section between the lower surface of the heating section and the chemically amplified resist film.